KR100497239B1 - Driving apparatus of plasma display panel - Google Patents

Abstract

The transistor connected between the scan electrode and the capacitor is turned on to transfer charge from the panel capacitor to the capacitor. In this way, the voltage applied to the panel capacitor decreases rapidly, causing a discharge in the panel capacitor. As the voltage of the capacitor increases due to the transferred charges, the gate-source voltage of the transistor decreases, thereby turning off the transistor and floating the scan electrode. The discharge then abruptly disappears and the wall charge is finely controlled. Next, after partially discharging the electric charge charged in the capacitor, the above operation is repeated a predetermined number of times. In this way, the wall charge can be finely controlled to create a desired wall charge state. A diode is connected in parallel to the capacitor to prevent the capacitor from being charged by the current formed by the body diode of the transistor. In this way, the transistor can be prevented from being destroyed by the voltage charging of the capacitor.

Description

Driving device of plasma display panel {DRIVING APPARATUS OF PLASMA DISPLAY PANEL}

The present invention relates to a driving apparatus and a driving method of a plasma display panel (PDP).

A plasma display panel is a flat panel display device that displays characters or images using plasma generated by gas discharge, and tens to millions or more of pixels are arranged in a matrix form according to their size. The plasma display panel is classified into a direct current type (DC type) and an alternating current type (AC type) according to the shape of the driving voltage waveform applied and the structure of the discharge cell.

In general, a driving method of an AC plasma display panel includes a reset period, an addressing period, and a sustain period, which is expressed as a change in time.

The reset period is a period of erasing the wall charge state formed by the previous sustain discharge and initializing the state of each cell in order to allow the next addressing operation to be performed smoothly. The addressing period is a period in which a wall charge is accumulated in a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on in the panel. The sustain period is a period in which discharge for actually displaying an image is performed on the addressed cells. When the sustain period is reached, sustain pulses are alternately applied to the scan electrode and the sustain electrode to perform sustain discharge, thereby displaying an image.

Conventionally, a ramp waveform was applied to the scan electrode as described in US Pat. No. 5,745,086 to set the wall charge in the reset period. That is, a slowly rising ramp waveform was applied to the scan electrode and then a slowly descending ramp waveform was applied. In the case of applying such a ramp waveform, since the control accuracy of the wall charge is strongly dependent on the inclination of the lamp, there is a problem that the wall charge cannot be precisely controlled within a predetermined time.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method and a driving apparatus for a plasma display panel capable of precisely controlling wall charges.

In order to solve this problem, according to an aspect of the present invention, there is provided an apparatus for driving a plasma display panel in which a capacitive load is formed between at least two electrodes. The drive device is turned on in response to a first level of control signal applied to the control terminal and the first main terminal is electrically connected to the capacitive load and the second main terminal is electrically connected to the power supply for supplying the first voltage. A capacitor formed in a path formed by the transistor, the capacitive load, the transistor and the power source, a discharge path for discharging at least a portion of the voltage stored in the capacitor in response to the second level of the control signal, and a current in the body diode of the transistor. Includes a first diode that blocks the flow to the capacitor. The control signal alternately has a first level and a second level. The transistor is turned on in response to the first level of the control signal applied to the control terminal of the transistor to change the voltage of the capacitive load.If the capacitor is charged with the second voltage while the voltage of the capacitive load is changed, the transistor is turned on. Is off.

According to an embodiment of the present invention, the first diode is electrically connected in parallel to the capacitor and may be formed in the same direction as the body diode of the transistor.

According to another embodiment of the present invention, the first diode is formed in a path formed by the capacitive load, the transistor, and the power supply, and may be formed in the opposite direction to the body diode of the transistor.

According to another embodiment of the present invention, the transistor may be turned off by the difference between the control terminal voltage of the transistor by the second voltage charged in the capacitor and the control signal of the first level.

According to another embodiment of the present invention, the transistor is turned on after the discharge of the capacitor to change the voltage of the capacitive load. The transistor may be turned off while the control signal is maintained at the first level.

According to another embodiment of the present invention, the second level of the control signal may be a level at which the transistor can be turned off.

According to another embodiment of the present invention, the discharge path further includes a resistor, and the capacitor may be discharged in a path formed by the capacitor and the resistor.

According to another embodiment of the present invention, the voltage of the capacitive load is reduced by turning on the transistor, and the capacitor can be electrically connected between the second main terminal of the transistor and the power supply.

According to another embodiment of the present invention, the voltage of the capacitive load is increased by turning on the transistor, and the capacitor can be electrically connected between the first main terminal of the transistor and the capacitive load.

According to another feature of the invention, there is provided an apparatus for driving a plasma display panel in which a capacitive load is formed between at least two electrodes. The drive device includes a transistor having a first main terminal electrically connected to a capacitive load, a capacitor electrically connected between a second main terminal of the transistor and a power supply for supplying a first voltage, and a first end electrically connected to the capacitor. A discharge path to be connected, a first diode to block current flowing in the body diode of the transistor from flowing through the capacitor, and a control voltage source to supply a control voltage to the control terminal of the transistor. The state of the transistor is determined by the voltage charged in the capacitor.

According to an embodiment of the present invention, the first diode is electrically connected in parallel to the capacitor and may be formed in the same direction as the body diode of the transistor.

According to another embodiment of the present invention, the first diode may be electrically connected in the opposite direction to the body diode of the transistor between the capacitive load and the transistor, or between the transistor and the capacitor, or between the capacitor and the power supply.

According to another feature of the invention, there is provided an apparatus for driving a plasma display panel in which a capacitive load is formed between at least two electrodes. The drive device includes a transistor having a first main terminal electrically connected to a power supply for supplying a first voltage, a capacitor electrically connected between a second main terminal of the transistor and a capacitive load, and a first end electrically connected to the capacitor. A discharge path to be connected, a first diode to block current flowing in the body diode of the transistor from flowing through the capacitor, and a control voltage source to supply a control voltage to the control terminal of the transistor. The state of the transistor is determined by the voltage charged in the capacitor.

According to an embodiment of the present invention, the first diode is electrically connected in parallel to the capacitor and may be formed in the same direction as the body diode of the transistor.

According to another embodiment of the present invention, the first diode may be electrically connected in the opposite direction to the body diode of the transistor between the power supply and the transistor, or between the transistor and the capacitor, or between the capacitor and the capacitive load.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification. When a part is connected to another part, this includes not only a directly connected part but also a case where another part is connected in between.

Now, a driving apparatus and a driving method of a plasma display panel according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic diagram of a plasma display panel according to an embodiment of the present invention.

As shown in FIG. 1, a plasma display panel according to an exemplary embodiment of the present invention includes a plasma panel 100, a controller 200, an address driver 300, and a sustain electrode driver (hereinafter referred to as an “X electrode driver”) 400. ) And a scan electrode driver (hereinafter referred to as a 'Y electrode driver') 500.

The plasma panel 100 includes a plurality of address electrodes A1-Am arranged in the column direction, a plurality of sustain electrodes (hereinafter referred to as 'X electrodes') (X1-Xn) and scan electrodes arranged in the row direction. (Hereinafter referred to as 'Y electrode') (Y1-Yn). The X electrodes X1-Xn are formed corresponding to the respective Y electrodes Y1-Yn, and generally have one end connected in common to each other. The plasma panel 100 includes a glass substrate (not shown) on which the X and Y electrodes X1-Xn and Y1-Yn are arranged, and a glass substrate (not shown) on which the address electrodes A1-Am are arranged. . The two glass substrates are disposed to face each other with the discharge space therebetween so that the Y electrodes Y1-Yn and the address electrodes A1-Am and the X electrodes X1-Xn and the address electrodes A1-Am are orthogonal to each other. At this time, the discharge space at the intersection of the address electrodes A1-Am and the X and Y electrodes X1-Xn and Y1-Yn forms a discharge cell.

The controller 200 receives an image signal from the outside and outputs an address driving control signal, an X electrode driving control signal, and a Y electrode driving control signal. The controller 200 divides and drives one frame into a plurality of subfields, and each subfield includes a reset period, an addressing period, and a sustain period.

The address driver 300 receives an address drive control signal from the controller 200 and applies a display data signal for selecting a discharge cell to be displayed to each address electrode A1-Am. The X electrode driver 400 receives the X electrode driving control signal from the controller 200 to apply a driving voltage to the X electrodes X1 to Xn, and the Y electrode driver 500 controls the Y electrode driving from the controller 200. The signal is received and a driving voltage is applied to the Y electrodes Y1-Yn.

Hereinafter, driving waveforms applied to the address electrodes A1-Am, the X electrodes X1-Xn, and the Y electrodes Y1-Yn in each subfield will be described with reference to FIGS. 2 and 3. The following description will be made based on the discharge cells formed by one address electrode, the X electrode, and the Y electrode.

2 is a driving waveform diagram of a plasma display panel according to an exemplary embodiment of the present invention, and FIG. 3 is a diagram illustrating a voltage and a discharge current of an electrode according to the driving waveform according to an exemplary embodiment of the present invention.

Referring to FIG. 2, one subfield includes a reset period Pr, an address period Pa, and a sustain period Ps, and the reset period Pr includes an erase period Pr1, a ramp rising period Pr2, and And ramp down period Pr3.

In general, after the last sustain discharge in the sustain period, a positive charge is formed at the X electrode and a negative charge at the Y electrode. Therefore, in the erase period Pr1 of the reset period Pr, a ramp waveform rising from the reference voltage to the Ve voltage is applied to the X electrode while the Y electrode is maintained at the reference voltage after the sustain period is over. At this time, in the embodiment of the present invention, it is assumed that the reference voltage is 0V. Then, the charges accumulated on the X electrode and the Y electrode are gradually erased.

Next, in the ramp up period Pr2 of the reset period Pr, a rising ramp waveform that increases from Vs voltage to Vset voltage is applied to the Y electrode while the X electrode is maintained at 0V. Then, a weak reset discharge occurs from the Y electrode to the address electrode and the X electrode, respectively, so that negative charges accumulate on the Y electrode and positive charges accumulate on the address electrode and the X electrode.

As shown in FIGS. 2 and 3, in the ramp falling period Pr3 of the reset period Pr, while the X electrode is maintained at the Ve voltage, the Y electrode is floated while decreasing by a predetermined voltage from the Vs voltage to the reference voltage. The falling / floating voltage is applied repeatedly. That is, the voltage applied to the Y electrode is rapidly reduced by a predetermined amount during the T _r period, and then the Y electrode is floated by cutting off the voltage supplied to the Y electrode during the T _f period. And this operation (T _r , T _f ) is repeated.

If the voltage difference between the voltage Vx of the X electrode and the voltage Vy of the Y electrode becomes equal to or more than the discharge start voltage Vf while repeating the operations T _r and T _f , the discharge is performed between the X electrode and the Y electrode. This happens. That is, the discharge current Id flows in the discharge space. When the Y electrode floats after the discharge is started between the X electrode and the Y electrode, the wall charges formed in the X and Y electrodes decrease, and the voltage in the discharge space rapidly decreases, thereby quenching strong discharge in the discharge space. ) Occurs. Then, when a falling voltage is applied to the Y electrode again to form a discharge, and then in a floating state, the wall charge decreases as before, and strong discharge disappears inside the discharge space. When the falling voltage application and the floating state are repeated a predetermined number of times, a desired amount of wall charges is formed on the X electrode and the Y electrode.

At this time, in order to appropriately control the wall charges, it is preferable to set the falling voltage application period T _r shorter than the floating period T _f . That is, when the voltage application period T _r is long, the discharge is formed too large, and the amount of wall charges that can be controlled by one discharge and floating becomes large. As such, when the amount of wall charges controlled at one time increases, the wall charges cannot be controlled in a desired state.

In the following, strong discharge disappearance due to floating will be described in detail with reference to FIGS. 4A to 4E. Since discharge occurs between the X electrode and the Y electrode, the discharge cell will be described based on the X electrode and the Y electrode.

4A is a diagram of a discharge cell formed by an X electrode and a Y electrode, and FIG. 4B is an equivalent circuit diagram of FIG. 4A. 4C is a diagram illustrating a case where no discharge occurs in the discharge cell of FIG. 4A. 4D is a diagram illustrating a state in which a voltage is applied when a discharge occurs in the discharge cell of FIG. 4A, and FIG. 4E is a diagram illustrating a floating state when a discharge occurs in the discharge cell of FIG. 4A. In FIG. 4A, the Y electrode 10 and the X electrode 20 are initially − for the convenience of description. And + It is assumed that a charge of is formed. The charge is formed on the dielectric layer of the electrode, but will be described below as being formed on the electrode for convenience of description.

As shown in FIG. 4A, the Y electrode 10 is electrically connected to the current source I _in through the switch SW, and the X electrode 20 is electrically connected to the V _e voltage. And the input voltage (V _in ) is a voltage falling fast by a certain amount. Dielectric layers 30 and 40 are formed inside the Y electrode 10 and the X electrode 20, respectively. Discharge gas (not shown) is injected between the dielectric layers 30 and 40, and a region between the dielectric layers 30 and 40 forms a discharge space 50.

In this case, since the Y and X electrodes 10 and 20, the dielectric layers 30 and 40, and the discharge space 50 form a capacitive load, they may be equivalently represented by the panel capacitor Cp as shown in FIG. 4B. . And the dielectric constants of the two dielectric layers 30 and 40 The voltage across the discharge space 50 is referred to as V _g . In addition, the thicknesses of the two dielectric layers 30 and 40 are equal (d ₁ ), and the distance (distance of the discharge space) between the two dielectric layers 30 and 40 is d ₂ .

The switch SW is turned on and the voltage Vy applied to the Y electrode 10 of the panel capacitor Cp decreases in proportion to the time when the switch SW is turned on, as shown in Equation 1 below. That is, when the switch SW is turned on, the falling voltage is applied to the Y electrode 10.

Here, Vy (0) is the Y electrode voltage Vy when the switch SW is turned on, and C _p is the capacitance of the panel capacitor Cp.

Referring to FIG. 4C, when no discharge occurs while the switch SW is turned on, the voltage V _g applied to the discharge space 50 is calculated. In addition, it is assumed that the voltage applied to the Y electrode 10 in the state of FIG. 4C is V _in .

As such, when the V _in voltage is applied to the Y electrode 10, As much charge is applied to the X electrode 20 as + As much charge is applied. In this case, the Gauss's law (Gaussian theorem) to when the dielectric 30 and 40, the interior of the electric field (electric field) (E ₁₎ and the discharge space 50 of the internal electric field (E ₂₎ is as shown in the respective formula 2 and 3 apply Is given.

here, Represents the amount of charge applied to the Y electrode and the X electrode, Is the dielectric constant inside the discharge space.

The voltage V _e -V _y applied to the outside is given by Equation 4 by the relationship between the electric field and the distance, and similarly, the voltage V _g of the discharge space 50 is expressed by Equation 5.

The amount of charge applied to the Y or X electrodes 10 and 20 from Equations 2 to 5 ) And the voltage V _{g in the} discharge space 50 are represented by Equations 6 and 7, respectively.

Where V _w is the wall charge in the discharge space 50 ( Is the voltage formed by

In fact, the length d ₂ inside the discharge space 50 is a very large value compared to the thickness d ₁ of the dielectrics 30 and 40. Is close to one. That is, it can be seen from Equation 7 that the voltage V _e -V _in applied from the outside is directly applied to the discharge space 50.

Next, the discharge occurs due to the voltage V _e -V _in applied from the outside with reference to FIG. 4D, and the wall charges formed on the Y electrode 10 and the X electrode 20 The voltage V _{g1 in} the discharge space 50 at the time of extinction is calculated. In FIG. 4D, since the charge is supplied from the power supply V _in to maintain the potential of the electrode at the time of wall charge formation, the amount of charge applied to the Y electrode 10 and the X electrode 20 is To increase.

When the Gaussian theorem is applied in FIG. 4D, the electric field E _{1 in} the dielectrics 30 and 40 and the electric field E _{2 in the} discharge space 50 are represented by Equations 8 and 9, respectively.

From equations (8) and (9), the amount of charges applied to the Y electrode 10 and the X electrode 20 ( ) And the voltage V _{g1 in the} discharge space are as shown in Equations 10 and 11, respectively.

In equation (11) Since is nearly 1, when a voltage V _in is applied from the outside, only a very small voltage drop occurs inside the discharge space 50 when discharge occurs. Thus, the amount of wall charge dissipated by the discharge ( ) Is large enough to reduce the internal voltage (V _g1 ) of the discharge space 50 to dissipate the discharge.

Next, the discharge is caused by the voltage V _in applied from the outside with reference to FIG. 4E, and the wall charges formed on the Y electrode 10 and the X electrode 20 After disappearing as much as possible, the voltage V _{g2 in} the discharge space 50 when the switch SW is turned off (floating the discharge space 50) is calculated. At this time, since there is no charge flowing from the outside, the amount of charge applied to the Y electrode 10 and the X electrode 20 is the same as that of FIG. 4C. Becomes Similarly, applying the Gaussian law of the dielectric (30, 40) of the internal electric field (E ₁₎ and the electric field in the discharge space (50), (E ₂₎ are each such as equation (2) and Equation (12).

From equations (12) and (6), the voltage V _g2 of the discharge space 50 is given by equation (13).

As can be seen from Equation 13, it can be seen that there is a large voltage drop due to the wall charge which disappears in the state in which the switch SW is turned off (floating state). That is, in the equations (12) and (13), the voltage drop due to the wall charge is 1 / (1- It can be seen that it is larger by). As a result, in the floating state, even if the wall charges are slightly dissipated, the voltage in the discharge space 50 decreases rapidly, so that the voltage between the electrodes becomes less than or equal to the discharge start voltage, and the discharge is extinguished rapidly. That is, it can be seen that the floating state of the electrode after the start of discharge serves as a sudden quenching mechanism of the discharge. When the voltage inside the discharge space 50 decreases, the X electrode is fixed to the Ve voltage, so that the voltage Vy of the floating Y electrode is increased by a predetermined voltage as shown in FIG. 3.

Referring to FIG. 3 again, if the Y electrode floats when the discharge occurs due to the drop of the Y electrode voltage, the discharge disappears while the wall charges formed on the Y and X electrodes are slightly lost by the discharge dissipation mechanism described above. By repeating this operation, it is possible to control the wall charges to a desired state while gradually erasing the wall charges formed on the Y and X electrodes. That is, it is possible to accurately control the desired wall charge state in the falling ramp period Pr3 of the reset period Pr.

Although the embodiment of the present invention has been described only in the falling ramp period Pr3 of the reset period Pr, the present invention is not limited to this and can be applied to all cases of controlling the wall charge using the falling ramp.

In addition, the embodiment of the present invention has been described with respect to the waveform in which the voltage of the electrode drops and floats, but the abrupt disappearance mechanism of the discharge described above may also be applied to the waveform in which the voltage of the electrode rises and floats. That is, instead of applying the rising ramp voltage to the electrode, the floating operation may be repeated after raising the voltage of the electrode.

Hereinafter, a driving circuit capable of repeating the operation of lowering the voltage applied to the electrode and then floating it will be described with reference to FIGS. 5 to 8. The driving circuit may be formed in the Y electrode driver 500 connected to the Y electrode in the driving waveform of FIG. 2.

FIG. 5 is a schematic circuit diagram of a driving circuit according to a first embodiment of the present invention, and FIG. 6 is a driving waveform diagram of the driving circuit of FIG. 7 and 8 are schematic circuit diagrams of a driving circuit according to the second and third embodiments of the present invention. The panel capacitor Cp of FIG. 5 is a capacitive load formed between the Y electrode and the X electrode as described with reference to FIG. 4A, and a ground voltage is applied to the second end of the panel capacitor Cp. Assume that (Cp) is charged with a certain amount of charge.

As shown in FIG. 5, the driving circuit according to the first embodiment of the present invention includes a transistor SW, a capacitor Cd, a resistor R, diodes D1 and D2 and a control signal voltage source Vg. . The drain of the transistor SW is connected to the first end of the panel capacitor Cp and the source is connected to the first end of the capacitor Cd. The second end of the capacitor Cd is connected to the ground terminal 0. The control signal voltage source Vg is connected between the gate of the transistor SW and the ground terminal 0 to supply the control signal Sg to the transistor SW.

The diode D1 and the resistor R1 are connected between the first end of the capacitor Cd and the control signal voltage source Vg to form a discharge path through which the capacitor Cd can be discharged. The diode D2 is connected between the ground terminal 0 and the gate of the transistor SW to clamp the gate voltage of the transistor SW. Although not shown, a resistor may be further included between the control signal voltage source Vg and the transistor SW, and a resistor may be further included between the gate and the ground terminal 0 of the transistor SW.

Next, the operation of the driving circuit of FIG. 5 will be described in detail with reference to FIG. 6. For convenience of explanation, the waveform of FIG. 6 assumes that no discharge occurs. If discharge occurs, the waveform of FIG. 6 will be given in the form of increasing V _p voltage in the floating period as shown in FIG. 3.

As shown in FIG. 6, the control signal Sg supplied from the gate voltage source Vg alternates between a high level voltage for turning on the transistor SW and a low level voltage for turning off the transistor SW.

First, when the transistor SW is turned on by the high level control signal Sg, the charge accumulated in the panel capacitor Cp is transferred to the capacitor Cd. When charge is accumulated in the capacitor Cd, the voltage at the first stage of the capacitor Cd is increased to increase the source voltage of the transistor SW. However, when referring to the second end of the capacitor Cd, the gate voltage of the transistor SW is maintained at the voltage when the transistor SW is turned on, whereas the voltage at the first end of the capacitor Cd increases. The source voltage of the transistor SW is relatively increased. At this time, when the source voltage of the transistor SW rises to a predetermined voltage, the gate-source voltage of the transistor SW becomes smaller than the threshold voltage V _{t of} the transistor SW, so that the transistor SW is turned off.

That is, the transistor SW is turned off when the difference between the high level voltage of the control signal and the source voltage of the transistor SW is smaller than the threshold voltage V _{t of} the transistor SW. As such, when the transistor SW is turned off, the voltage supplied to the panel capacitor Cp is cut off, and thus the panel capacitor Cp is in a floating state. When the transistor M1 is turned off, the amount of charge ΔQ _i accumulated in the capacitor Cd is expressed by Equation 14. At this time, if the capacitance C _d of the capacitor Cd is appropriately set, the period T _{ri at} which the voltage of the panel capacitor Cp falls is shorter than the period T _on at which the control signal Sg is at the high level. Can be. That is, the level control of the control signal Sg may cause the floating of the panel capacitor Cp faster than the floating of the panel capacitor Cp. In addition, even when the control signal Sg is at the low level, since the transistor SW is continuously turned off, the floating period T _fi may be longer than the falling voltage application period T _ri .

Here, V _cc is the high level voltage of the control signal, V _t is the threshold voltage of the transistor SW and C _d is the capacitance of the capacitor Cd.

Since the charge equal to the charge amount ΔQ _i stored in the capacitor Cd is supplied from the panel capacitor Cp, the voltage decrease amount ΔV _pi of the panel capacitor Cp is expressed by Equation 15.

Here, C _p is the capacitance of the panel capacitor C _p .

Next, when the control signal goes low, the voltage at the first stage of the capacitor Cd is higher than the voltage of the gate voltage source Vg, so that the voltage of the capacitor Cd, the diode D1, the resistor R1, and the gate voltage source Vg is increased. Through the path, the capacitor Cd is discharged. At this time, since the capacitor Cd discharges while the voltage of (V _cc −V _t ) is charged, the amount ΔV _{d at} which the voltage of the capacitor Cd decreases due to discharge is given by Equation 16 below.

Here, R ₁ is the resistance value of the resistor R1.

The amount of charge ΔQ _d discharged from the capacitor Cd is represented by Equation 17 according to the time T _off when the control signal is maintained at the low level, and the amount of charge Q _d remaining in the capacitor Cd is (18)

Next, when the control signal becomes high again, the transistor SW is turned on to transfer charge from the panel capacitor Cp to the capacitor Cd. As described above, when the charge of ΔQ _i is accumulated in the capacitor Cd, the transistor SW is turned off. Therefore, when the charge of ΔQ _d is moved from the panel capacitor Cp to the capacitor Cd, the transistor SW is turned off. Is turned off. Therefore, the voltage ΔV _p decreasing in the panel capacitor Cp is expressed by Equation 19.

As described above, when the voltage of ΔV _p decreases in the panel capacitor Cp, the voltage of the capacitor Cd increases and the transistor SW is turned off. When the control signal Sg becomes low, the capacitor Cd is discharged while the transistor SW is turned off. That is, the control signal (Sg) period the voltage drops in response to the high level of the panel capacitor (Cp) (T _r) and the capacitor (Cd) is that the floating period (T _f panel capacitor (Cp) in response to the voltage rise of the ) Will continue to repeat. Therefore, it is possible to apply the falling ramp voltage to the electrode which is repeated voltage drop and floating.

In the first embodiment of the present invention, although the discharge path is formed to repeat the voltage drop and the floating, the discharge path may not be necessary when the voltage drop and the float are performed only once. In addition, the discharge path may be formed in another path without being connected to the control signal voltage source Vg. For example, a switch may be connected between the first end of the capacitor Cp and the ground to be used as a discharge path. In this case, the switch may be turned on in the period T _off for discharging the capacitor Cp.

In Equation 19, since the voltage decreasing in the panel capacitor Cp is determined by the low level period T _off of the resistor R1 and the control signal Sg, the panel is controlled by adjusting the duty of the control signal Sg. The voltage reduction amount of the capacitor Cp can be adjusted. In addition, as shown in FIG. 7, the amount of voltage reduction of the panel capacitor Cp may be adjusted by connecting the variable resistor R2 to the resistor R1 in parallel to adjust the size of the variable resistor R2. Of course, instead of connecting the variable resistor R2 to the resistor R1 in parallel, the variable resistor R2 may be connected instead of the resistor R1.

In addition, as shown in FIG. 8, a resistor R3 may be connected between the panel capacitor Cp and the transistor SW to limit the amount of current discharged from the panel capacitor Cp. Instead of the resistor R3, another element that can limit the magnitude of the current, for example, an inductor (not shown) may be used.

In the driving circuit described with reference to FIGS. 5 to 8, when the transistor SW is turned off when charged to a predetermined voltage of the capacitor Cd, the current flowing in the direction from the first end to the second end of the capacitor Cd is a transistor. It is controlled by the gate-source voltage of (SW). However, since the transistor SW has a body diode generally formed from a source to a drain direction, the capacitor (when the voltage of the panel capacitor Cp is lower than the voltage of the power source to which the capacitor Cd is connected (ground voltage in FIG. 5) is used. A current may flow in the direction of the first end from the second end of Cd). In the driving circuit of FIGS. 5 to 8, since there is no means for controlling the current flowing in this direction, the voltage may be continuously charged to the capacitor Cd. Then, the voltage of the second stage of the capacitor Cd is relatively higher than the voltage of the first stage voltage by the voltage charged in the capacitor Cd, so that the gate voltage of the transistor SW is increased by the voltage of the first stage of the capacitor Cd, that is, The source voltage of the transistor SW is relatively higher than the voltage charged in the capacitor Cd. Therefore, the gate-source voltage of the transistor SW is increased by the voltage charged in the capacitor Cd. If the voltage is greater than the breakdown voltage between the gate and the source of the transistor SW, the transistor SW may be destroyed.

Hereinafter, an embodiment for preventing the transistor SW from being destroyed by the current flowing in the second end direction of the capacitor Cd in this manner will be described in detail with reference to FIGS. 9 and 10. Explain.

9 and 10 are schematic circuit diagrams of driving circuits according to fourth and fifth embodiments of the present invention, respectively. 9 and 10 illustrate the body diode of the transistor SW for convenience of description.

9, the driving circuit according to the fourth embodiment of the present invention has the same structure as the driving circuit of FIG. 5 except that the diode D3 is connected in parallel to the capacitor Cd. That is, an anode of the diode D3 is connected to the second end of the capacitor Cd and a cathode of the diode D3 is connected to the first end of the capacitor Cd. In this case, when the second stage voltage of the capacitor Cd is higher than the voltage of the panel capacitor Cp, the current generated by the body diode of the transistor SW flows through the diode D3, so that the capacitor Cd ) Is not charged. Since the voltage is not charged in the capacitor Cd, the voltage between the source and the source of the transistor SW does not increase withstand voltage abnormally.

Referring to FIG. 10, the driving circuit according to the fifth embodiment of the present invention is connected to the driving circuit of FIG. 5 except that the diode D4 is connected in series between the panel capacitor Cp and the transistor SW. Have the same structure. That is, an anode of the diode D4 is connected to the first end of the panel capacitor Cp and a cathode of the diode D4 is connected to the drain of the transistor SW. In this way, since the diode D4 is connected to the body diode of the transistor SW in the opposite direction, the current flow generated by the body diode of the transistor SW is blocked. In FIG. 10, the diode D4 is connected between the panel capacitor Cp and the transistor SW. However, the diode D4 is connected to the panel capacitor Cp, the transistor SW, and the capacitor Cd. It can form in any of the path | route formed.

In the above, the method of discharging the voltage charged in the panel capacitor Cp in order to generate the falling waveform has been described above. However, the present invention is not limited thereto, and the voltage is increased in the panel capacitor Cp. The same may be applied to a method for generating a waveform. Hereinafter, such an embodiment will be described with reference to FIGS. 11 to 13.

11 to 13 are schematic circuit diagrams of driving circuits according to sixth to eighth embodiments of the present invention, respectively. 12 and 13 also illustrate a body diode of the transistor SW for convenience of description.

As shown in FIG. 11, in the driving circuit according to the sixth embodiment of the present invention, unlike FIG. 5, the drain of the transistor M1 is connected to a power supply for supplying a high voltage Vset, and the source of the transistor M1 The capacitor Cd is connected between the first terminal Y electrode of the panel capacitor Cp. In FIG. 11, when the transistor SW is turned on, the capacitor Cd and the panel capacitor Cp are charged by the Vset voltage, and when the voltage of the capacitor Cd increases to a predetermined voltage, the transistor SW is turned off. Since the rest of the operation can be easily understood by those skilled in the art from the above-described embodiment, a detailed description thereof will be omitted.

In the driving circuit of FIG. 11, current may flow from the second end of the capacitor Cd to the first end due to the body diode of the transistor SW, and thus the transistor SW may be destroyed. Therefore, as described with reference to FIGS. 9 and 10, the diode may be connected to the driving circuit of FIG. 11.

That is, referring to FIG. 12, the anode of the diode D3 may be connected to the second end of the capacitor Cd and the cathode of the diode D3 may be connected to the first end of the capacitor Cd as described with reference to FIG. 9. Then, since the current formed by the body diode of the transistor SW flows through the diode D3, the voltage of the capacitor Cd can be blocked.

13, the anode of the diode D4 is connected to the second end of the capacitor Cd and the cathode of the diode D4 is connected to the first end of the panel capacitor Cp as described with reference to FIG. 10. Then, since the current formed by the body diode of the transistor SW is blocked by the diode D4, the voltage of the capacitor Cd can be blocked. As described with reference to FIG. 10, the diode D4 may be formed anywhere in the path formed by the Vset voltage, the transistor SW, the capacitor Cd, and the panel capacitor Cp.

As mentioned above, although the method of floating a scan electrode was mainly demonstrated in the Example of this invention, this invention can be applied to all the methods of floating any one electrode in the discharge cell which consists of a scan electrode, a sustain electrode, and an address electrode.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

According to the present invention, it is possible to provide a driving circuit capable of repeating the operation of floating the electrode after decreasing or raising the voltage applied to the electrode forming the discharge cell. By this operation, the wall charges formed in the discharge cells can be finely controlled. In addition, it is possible to prevent destruction of the transistor SW, which may be generated by the current formed by the body diode of the transistor SW.

1 is a schematic diagram of a plasma display panel according to an embodiment of the present invention.

2 is a driving waveform diagram of a plasma display panel according to an exemplary embodiment of the present invention.

3 is a view showing a driving waveform and a discharge current according to an embodiment of the present invention.

4A is a diagram illustrating a discharge cell formed by a sustain electrode and a scan electrode.

4B is an equivalent circuit diagram of FIG. 4A.

4C is a diagram illustrating a case where no discharge occurs in the discharge cell of FIG. 4A.

4D is a diagram illustrating a state in which a voltage is applied when a discharge occurs in the discharge cell of FIG. 4A.

FIG. 4E is a diagram illustrating a floating state when discharge occurs in the discharge cell of FIG. 4A.

5 is a schematic circuit diagram of a driving circuit according to a first embodiment of the present invention.

6 is a driving waveform diagram of the driving circuit of FIG. 5.

7 to 13 are schematic circuit diagrams of a driving circuit according to another embodiment of the present invention, respectively.

Claims (20)

An apparatus for driving a plasma display panel in which a capacitive load is formed between at least two electrodes, A first main terminal electrically connected to the capacitive load, a second main terminal electrically connected to a power supply for supplying a first voltage, and a transistor turned on in response to a first level of a control signal applied to a control terminal; A capacitor formed in a path formed by the capacitive load, the transistor, and the power source, A discharge path for discharging at least a portion of the voltage stored in the capacitor in response to the second level of the control signal, and A first diode that blocks current in the body diode direction of the transistor from flowing to the capacitor Including; The control signal alternately has the first level and the second level, The transistor is turned on in response to a first level of a control signal applied to a control terminal of the transistor to change the voltage of the capacitive load, And the transistor is turned off when the second voltage is charged in the capacitor while the voltage of the capacitive load is changed. The method of claim 1, And the first diode is electrically connected in parallel to the capacitor and is formed in the same direction as the body diode of the transistor. The method of claim 1, And the first diode is formed in a path formed by the capacitive load, the transistor, and the power source, and is formed in a direction opposite to the body diode of the transistor. The method according to any one of claims 1 to 3, And the transistor is turned off due to a difference between the second voltage charged in the capacitor and a control terminal voltage of the transistor due to the control signal of the first level. The method according to any one of claims 1 to 3, And the transistor is turned on after the capacitor is discharged so that the voltage of the capacitive load is changed. The method of claim 5, And the transistor is turned off while the control signal is maintained at the first level. The method according to any one of claims 1 to 3, And a second level of the control signal is a level at which the transistor can be turned off. The method according to any one of claims 1 to 3, And the discharge path includes a second diode electrically connected to an anode of the capacitor. The method of claim 8, The discharge path further comprises a resistor, And a capacitor discharged through a path formed by the capacitor and the resistor. The method according to any one of claims 1 to 3, The voltage of the capacitive load is reduced by turning on the transistor, And the capacitor is electrically connected between the second main terminal of the transistor and the power supply. The method according to any one of claims 1 to 3, The voltage of the capacitive load is increased by turning on the transistor, And the capacitor is electrically connected between the first main terminal of the transistor and the capacitive load. An apparatus for driving a plasma display panel in which a capacitive load is formed between at least two electrodes, A transistor having a first main terminal electrically connected to the capacitive load; A capacitor electrically connected between the second main terminal of the transistor and a power supply for supplying a first voltage, A discharge path having a first end electrically connected to the capacitor, A first diode which blocks current flowing in the body diode of the transistor from flowing to the capacitor, and A control voltage supply source for supplying a control voltage to the control terminal of the transistor, And a state of the transistor is determined by a voltage charged in the capacitor. An apparatus for driving a plasma display panel in which a capacitive load is formed between at least two electrodes, A transistor having a first main terminal electrically connected to a power supply for supplying a first voltage, A capacitor electrically connected between the second main terminal of the transistor and the capacitive load, A discharge path having a first end electrically connected to the capacitor, A first diode which blocks current flowing in the body diode of the transistor from flowing to the capacitor, and A control voltage supply source for supplying a control voltage to the control terminal of the transistor, And a state of the transistor is determined by a voltage charged in the capacitor. The method according to claim 12 or 13, The control voltage alternately has a first level and a second level, The first level is a level at which the transistor can be turned on when the capacitor is discharged by a predetermined amount in the discharge path. And the second level is a level at which the transistor can be turned off. The method of claim 14, And a discharge period in which the second voltage of the discharge path is lower than the voltage of the capacitor. The method of claim 15, The discharge path further includes a second diode having an anode electrically connected to the capacitor and a cathode electrically connected to a second end of the discharge path. The method of claim 16, And a second end of the discharge path is electrically connected to the control voltage supply source. The method according to claim 12 or 13, And the first diode is electrically connected in parallel to the capacitor and is formed in the same direction as the body diode of the transistor. The method of claim 12, And the first diode is electrically connected in the opposite direction to the body diode of the transistor between the capacitive load and the transistor, or between the transistor and the capacitor, or between the capacitor and the power supply. The method of claim 13, And the first diode is electrically connected in the opposite direction to the body diode of the transistor between the power supply and the transistor, or between the transistor and the capacitor, or between the capacitor and the capacitive load.