KR100497163B1 - Test device for a semiconductor memory device - Google Patents

Abstract

A special test mode circuit configured to generate a special test mode entry signal in response to the special test mode control signal; A refresh buffer generating a control signal in response to an external refresh signal and a special test entry signal; A controller configured to generate an external refresh control signal and a forced refresh signal in response to the control signal, or generate a forced rate write signal; A refresh controller configured to generate a self refresh request signal in response to an external refresh control signal; A precharge controller configured to generate a precharge signal in response to one of the forced refresh signal and the forced late write signal; And a special refresh controller configured to generate a refresh start signal in response to a self refresh request signal and a forced refresh signal, or to generate a rate write start signal in response to a forced rate write signal. .

Description

Test device for a semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to test apparatus for semiconductor memory devices, and more particularly, to test apparatus useful for failure analysis of pseudo SRAM.

Pseudo-SRAM, which has a DRAM cell and an SRAM interface, looks like SRAM from the outside, but because it uses a DRAM cell, the internal refresh operation is performed to maintain the written cell data. However, the refresh operation of the DRAM cell is hidden from the outside, so that the pseudo SRAM seems to be performing only a normal write or read operation. That is, the pseudo SRAM actually performs the refresh operation without affecting the normal operation inside. Also, in the case of a long write operation, tCW (the time from the time of chip selection to the end of the write operation) is maximized. In such a case, refreshing is required during writing. At this time, the write operation is interrupted and the refresh operation is started. In addition, a write operation may be disabled by a refresh operation. At this time, a write operation must be performed. Like this, in addition to normal operation, a special operation such as refresh or late write operation is performed internally.

However, in the prior art, it was not possible to confirm by external control whether such a special operation was normally performed.

Accordingly, an object of the present invention is to provide a test apparatus for a semiconductor memory device capable of testing whether a refresh or late write operation other than the above-described normal operation is normally performed.

According to another aspect of the present invention, a test apparatus for a semiconductor memory device may include: a special test mode circuit configured to generate a special test mode entry signal in response to a special test mode control signal; A refresh buffer generating a control signal in response to an external refresh signal and a special test entry signal; A controller configured to generate an external refresh control signal and a forced refresh signal in response to the control signal, or generate a forced rate write signal; A refresh controller configured to generate a self refresh request signal in response to an external refresh control signal; A precharge controller configured to generate a precharge signal in response to one of the forced refresh signal and the forced late write signal; And a special refresh controller configured to generate a refresh start signal in response to the self refresh request signal and the forced refresh signal, or to generate a rate write start signal in response to the forced rate write signal.

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Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a test apparatus for a semiconductor memory device according to an exemplary embodiment of the present invention with reference to FIGS. 2 to 4.

Referring to FIG. 1, the test apparatus includes a test pad 10, a refresh buffer 20, a special test mode circuit 30, a controller 40, a refresh controller 50, a special refresh controller 60, and a precharge. The control unit 70 is included. The external refresh signal Ref.force is input to the test pad 10. The special test mode circuit 30 generates a special test mode entry signal st_extref_bufen in response to the special test mode control signal x. The refresh buffer 20 generates a control signal ext_ref in response to the external refresh signal Ref.force and the special test entry signal st_extref_bufen. More specifically, when the special test entry signal st_extref_bufen is in a logic high state, the refresh buffer 20 generates the control signal ext_ref in response to the external refresh signal Ref.force. The controller 40 generates an external refresh control signal extref_en and a forced refresh signal ref_force in response to the control signal ext_ref, or generates a forced rate write signal ltwr_force. The refresh control unit 50 generates a self refresh request signal srefreq in response to the external refresh control signal extref_en. The special refresh control unit 60 generates a refresh start signal ref_start in response to the self refresh request signal srefreq and the forced refresh signal ref_force, or generates a rate in response to the forced rate write signal ltwr_force. The write start signal ltwr_start is generated. A refresh operation of the DRAM cells of the pseudo SRAM is started according to the refresh start signal ref_start, and a late write operation of the DRAM cells of the pseudo SRAM is started according to the late write start signal ltwr_start. The precharge control unit 70 generates a precharge signal in response to one of the forced refresh signal ref_force and the forced rate write signal ltwr_force, and generates a precharge signal according to the precharge signal. The word line is closed (ie, the word line is disabled).

More specifically, when the control signal ext_ref transitions from the high level to the low level, the controller 40 activates the forced refresh signal ref_force (ie, generates a high pulse signal). In addition, when the control signal ext_ref transitions from a low level to a high level, the controller 40 activates the forced rate write signal ltwr_force (that is, generates a high pulse signal). The controller 40 may be implemented with logic elements.

The refresh start signal ref_start is a signal for controlling the start of the refresh operation. When the refresh start signal ref_start is activated, the refresh operation is executed. When the forced refresh signal ref_force is activated and the self refresh request signal srefreq is activated in the middle of the write operation, the refresh start signal ref_start is activated to start the refresh. The late write start signal ltwr_start is a signal for controlling the start of a late write operation.

If a forced refresh signal ref_force is generated during a read operation, the special refresh control unit 60 waits until the read operation is finished, and then when the precharge signal is generated, the refresh start signal ref_start is generated. )

When the forced rate write signal ltwr_force is generated while the write operation is executed, an interrupt is interrupted in the middle of the write operation, and the precharge control unit 70 generates the precharge signal Precharge to perform the rate write operation. . However, the rate write operation is not executed unconditionally, but the refresh operation is forcibly executed during the write operation, and the write operation is terminated during the forcibly executed refresh operation, so that the condition to execute the rate write operation must be preceded first. The action is made.

The precharge control unit 70 generates a precharge signal Precharge to interrupt the write operation in response to one of the forced refresh signal ref_force and the forced rate write signal ltwr_force.

Each of the refresh buffer 20, the special test mode circuit 30, the control unit 40, the refresh control unit 50, the special refresh control unit 60, and the precharge control unit 70 may be implemented as logic elements. .

2 is a timing diagram for explaining a forced refresh operation and a late write operation.

The forced refresh operation and the rate write operation are performed only in a section in which the special test mode entry signal st_extref_bufen is high. When the external refresh signal Ref_force is input to the test pad 10, if the special test mode entry signal st_extref_bufen is high, the refresh buffer 20 generates a control signal ext_ref. More specifically, while the special test mode entry signal st_extref_bufen is high, the refresh buffer 20 generates the control signal ext_ref substantially equal to the phase of the external refresh signal Ref_force. . When the control signal ext_ref transitions from the high level to the low level, the controller 40 generates an external refresh control signal extref_en and a forced refresh signal ref_force in the form of a high pulse signal. In addition, the control unit 40 generates a forced rate write signal ltwr_force in the form of a high pulse signal when the control signal ext_ref transitions from a low level to a high level. When the external refresh control signal extref_en is generated in the form of a high pulse signal, the refresh control unit 50 activates the self refresh request signal srefreq. The precharge control unit 70 generates a precharge signal in the form of a high pulse signal whenever the forced refresh signal ref_force or the forced rate write signal ltwr_force is generated in the form of a high pulse signal. When the self refresh request signal srefreq is activated and the forced refresh signal ref_force is generated in the form of a high pulse signal, the special refresh control unit 60 generates a refresh start signal ref_start in the form of a high pulse signal. . As a result, the refresh start signal ref_start is generated when the external refresh control signal extref_en and the forced refresh signal ref_force are at a high level. On the other hand, when the forced late write signal ltwr_force is at a high level, the special refresh control unit 60 generates the late write start signal ltwr_start in the form of a high pulse signal.

3 is a timing diagram illustrating a write interrupt operation for a forced refresh operation.

The write interrupt operation for the forced refresh operation is also performed only while the special test mode entry signal st_extref_bufen maintains the high level. When the external refresh signal Ref.force falls from the high level to the low level during the normal write operation, the refresh buffer 20 causes the control signal ext_ref to transition from the high level to the low level. The controller 40 generates a forced refresh signal ref_force in the form of a high pulse signal in response to the control signal ext_ref. The precharge control unit 70 generates a precharge signal in the form of a high pulse signal in response to the forced refresh signal ref_force. Accordingly, the precharge signal causes the word line to be closed (that is, disabled) and the write operation is interrupted. Meanwhile, the special refresh control unit 60 generates a refresh start signal ref_start in the form of a high pulse signal in response to the forced refresh signal ref_force. As a result, the refresh operation of the pseudo SRAM is started by the refresh start signal ref_start.

4 is a timing diagram for describing a write interrupt operation for a forced rate write operation.

The write interrupt operation for the forced rate write operation is also performed only while the special test mode entry signal st_extref_bufen maintains the high level. During the normal write operation, when the external refresh signal Ref.force transitions from the low level to the high level, the refresh buffer 20 causes the control signal ext_ref to transition from the low level to the high level. The controller 40 generates a forced rate write signal ltwr_force in the form of a high pulse signal in response to the control signal ext_ref. The precharge controller 70 generates a precharge signal in the form of a high pulse signal in response to the forced rate write signal ltwr_force. Accordingly, the precharge signal causes the word line to be closed (ie, disabled) and the write operation is interrupted. Meanwhile, the special refresh control unit 60 generates a late write start signal ltwr_start in the form of a high pulse signal in response to the forced late write signal ltwr_force. As a result, the late write operation of the pseudo SRAM is started by the late write start signal ltwr_start.

After the interrupt operation of FIGS. 3 and 4, the normal write operation is started again.

As described above, in the present invention, the refresh and rate write operations can be freely controlled using an external signal. That is, by reading the data storage state of the cell through the read operation after the forced refresh and late write operation, it is possible to quickly determine whether the semiconductor memory device is defective.

According to the present invention, there is an excellent effect that can effectively analyze the failure of a semiconductor memory device.

Although the present invention has been described with reference to the embodiments, one of ordinary skill in the art can modify and change various forms using such embodiments, and thus the present invention is not limited to these embodiments. It is limited by the claims.

1 is a block diagram of an apparatus for testing a semiconductor memory device according to the present invention.

2 to 4 are timing diagrams for describing the operation of FIG. 1.

* Explanation of symbols for the main parts of the drawings

10: test pad 20: refresh buffer

30: special test mode circuit

40: control unit 50: refresh control unit

60: special refresh control unit

70: precharge control unit

Claims (5)

A special test mode circuit configured to generate a special test mode entry signal in response to the special test mode control signal; A refresh buffer configured to generate a control signal in response to an external refresh signal and the special test entry signal; A controller configured to generate an external refresh control signal and a forced refresh signal in response to the control signal, or generate a forced rate write signal; A refresh controller configured to generate a self refresh request signal in response to the external refresh control signal; A precharge controller configured to generate a precharge signal in response to one of the forced refresh signal and the forced late write signal; And And a special refresh controller configured to generate a refresh start signal in response to the self refresh request signal and the forced refresh signal, or to generate a rate write start signal in response to the forced rate write signal. Testing device. The method of claim 1, And the refresh buffer generates the control signal equal to the phase of the external refresh signal when the special test mode entry signal is in a high state. The method of claim 1, The controller generates the external refresh control signal and the forced refresh signal in the form of a high pulse signal when the control signal transitions from a high level to a low level, and when the control signal transitions from a low level to a high level, And generating the forced late write signal in the form of a high pulse signal. The method of claim 1, The special refresh control unit generates the refresh start signal when the self refresh request signal is activated and the forced refresh signal is at a high level, and generates the rate write start signal when the forced rate write signal is at a high level. Test device for a semiconductor memory device, characterized in that. The method of claim 1, And the precharge control unit generates the precharge signal when one of the forced refresh signal and the forced rate write signal is at a high level.