KR100495090B1 - Method of shrinking tunnelling range of EEPROM - Google Patents
Method of shrinking tunnelling range of EEPROM Download PDFInfo
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- KR100495090B1 KR100495090B1 KR10-1998-0041693A KR19980041693A KR100495090B1 KR 100495090 B1 KR100495090 B1 KR 100495090B1 KR 19980041693 A KR19980041693 A KR 19980041693A KR 100495090 B1 KR100495090 B1 KR 100495090B1
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 238000005468 ion implantation Methods 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 6
- 230000003647 oxidation Effects 0.000 claims abstract description 3
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 230000008569 process Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 239000002904 solvent Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000010884 ion-beam technique Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
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Abstract
본 발명은 EEPROM(electrically erasable programmable ROM)의 터널영역에 대한 것이다. 보다 구체적으로 본 발명은 EEPROM의 터널영역의 크기를 이온주입법을 써서 축소하는 방법에 대한 것이다. 본 발명은 드레인영역 위에 터널산화막과 부유게이트(floating gate) 전극이 형성된 EEPROM의 터널산화막 영역(터널영역)을 축소하는 방법에 대한 것이다. 본 발명에 따른 방법은 반도체기판 위에 드레인영역을 형성하고 이 드레인영역 위에 산화막을 성장한 후, 산화막이 형성된 반도체기판에 감광막을 덮고 에칭하여 터널영역을 형성하는 단계와, 터널영역이 형성된 감광막을 마스크로 하여 이온주입을 실시하되, 터널영역이 형성된 감광막 측벽의 바깥 방향에서 안쪽으로 비스듬히 360°돌아가면서 이온주입을 하여 이온주입에 의한 드레인영역 손상부가 고리형상으로 형성되도록 하는 단계와, 터널영역의 산화막을 제거하여 드레인영역을 노출시키는 단계와, 이온주입에 의해 손상을 받은 부분이 손상받지 않은 부분보다 산화 속도가 빠른 성질을 이용하여 터널영역의 드레인영역에 이차로 산화막을 성장하는 단계와, 터널영역의 이차 산화막 위에 부유게이트 전극을 형성하는 단계를 포함한다.The present invention relates to a tunnel region of an electrically erasable programmable ROM (EEPROM). More specifically, the present invention relates to a method of reducing the size of a tunnel region of an EEPROM by using an ion implantation method. The present invention relates to a method for reducing a tunnel oxide layer region (tunnel region) of an EEPROM in which a tunnel oxide layer and a floating gate electrode are formed on a drain region. The method according to the present invention comprises forming a drain region on a semiconductor substrate and growing an oxide film on the drain region, then covering and etching the photosensitive film on the semiconductor substrate on which the oxide film is formed to form a tunnel region, and using the photosensitive film having the tunnel region as a mask. Ion implantation, and the ion implantation is performed while turning 360 degrees obliquely inward from the outer side of the sidewall of the photosensitive film where the tunnel region is formed so that the drain region damaged portion by the ion implantation is formed in a ring shape, and the oxide film of the tunnel region is formed. Removing the oxide to expose the drain region, and growing the oxide film in the drain region of the tunnel region using the property of faster oxidation rate than the portion damaged by the ion implantation; Forming a floating gate electrode on the secondary oxide layer.
Description
본 발명은 EEPROM(electrically erasable programmable ROM)의 터널영역에 대한 것이다. 보다 구체적으로 본 발명은 EEPROM의 터널영역의 크기를 이온주입법을 써서 축소하는 방법에 대한 것이다.The present invention relates to a tunnel region of an electrically erasable programmable ROM (EEPROM). More specifically, the present invention relates to a method of reducing the size of a tunnel region of an EEPROM by using an ion implantation method.
EEPROM은 자외선을 쓰지 않고 전기적으로 저장데이터를 지웠다 썼다 할 수 있는 메모리소자인데, EEPROM은 기능측면에서의 소자명이고 구조측면에서는 FLOTOX(floating-gate tunnel-oxide MOS transistor)라 부르고 있다. 이름 그대로 얇은 터널산화막을 부유게이트(floating gate)와 드레인 사이에 끼워서 캐리어가 이 산화막을 터널링하도록 하는 구조를 갖는다. EEPROM is a memory device that can be erased and written electrically without using ultraviolet light. EEPROM is a device name in terms of function and is called FLOTOX (floating-gate tunnel-oxide MOS transistor) in terms of structure. As the name implies, a thin tunnel oxide is sandwiched between a floating gate and a drain so that the carrier tunnels the oxide.
도6에 개략적인 구조가 나타나 있다. 일반적인 MOS구조와 같이, 반도체기판(101)에 드레인영역(103)과 소스영역(105)을 만들고 게이트산화막(107)을 형성한 후 다결정실리콘(poly-Si)으로 게이트전극(113)을 형성한다. 일반 MOS구조와 다른 점은, 게이트전극(113)과 드레인영역(103) 사이에 아주 얇은(보통 10nm 내외) 터널산화막(109)과 다결정실리콘으로 부유게이트(floating gate)전극(111)이 형성된다는 점이다. 이 부유게이트 전극(111)은 아무데도 연결되지 않기 때문에 부유(floating)전극이라 부르는 것이다. 위와 같은 구조에서 터널산화막(109)이 있는 영역을 본 명세서에서 "터널영역"이라 부르기로 한다. A schematic structure is shown in FIG. As in the general MOS structure, the drain region 103 and the source region 105 are formed in the semiconductor substrate 101, the gate oxide film 107 is formed, and the gate electrode 113 is formed of poly-silicon (poly-Si). . The difference from the general MOS structure is that a very thin (usually around 10 nm) tunnel oxide film 109 and a floating gate electrode 111 are formed of polycrystalline silicon between the gate electrode 113 and the drain region 103. Is the point. The floating gate electrode 111 is called a floating electrode because it is not connected anywhere. In the above structure, the region in which the tunnel oxide film 109 is located is referred to herein as a "tunnel region".
최근, 메모리용량이 증가하고 소자크기가 줄어들고 있는 추세에 따라 메모리소자의 단위구조(cell)의 축소기술(scaling)이 중요해 지고 있다. 따라서 터널영역의 축소 또한 불가결한데, 종래의 석판기술로서 터널영역을 축소하는 것은 이미 한계에 도달해 있다. Recently, as the memory capacity increases and the device size decreases, scaling technology of a cell structure of a memory device has become important. Therefore, the reduction of the tunnel area is also indispensable. As the conventional slab technology, the reduction of the tunnel area has already reached its limit.
석판기술(lithography)이란 마스크에 형성된 원하는 패턴을 반도체기판에 덮은 감광막(photoresist)에 옮기는 공정을 일컫는다. 기본적으로 반도체소자 제조공정은 웨이퍼 위에 층층이 막을 형성해 가는 공정이라고 할 수 있다. 이 때 필요한 영역들, 즉 이온주입 영역, 전극 영역, 배선패턴, 각종 패드 등이 필요한데 이들 영역을 형성하기 위하여 석판기술이 이용된다. 석판기술은 근본적으로 감광막에 마스크를 통해 빛을 쬐어 감광막의 성질을 변화시키는 것을 원리로 한다. 빛을 받은 부분이 용제에 녹는 감광막을 양성(positive)감광막이라 하고 빛을 받지 않은 부분이 용제에 녹는 감광막을 음성(negative)감광막이라 한다. 어떠한 종류의 감광막을 쓰든지 마스크에 형성된 패턴에 따라 빛에 노출된 부위와 노출되지 않은 부위가 생기기 때문에 감광막을 용제로 녹여 내면 마스크의 패턴이 그대로 반도체기판에 전사된다. 이 감광막의 패턴을 마스크로 하여 반도체기판에 에칭을 행하면 원하는 패턴이 반도체기판에 형성되는 것이다. Lithography refers to a process of transferring a desired pattern formed on a mask to a photoresist covered by a semiconductor substrate. Basically, the semiconductor device manufacturing process is a process in which a layer layer forms a film on a wafer. At this time, necessary regions, i.e., an ion implantation region, an electrode region, a wiring pattern, various pads, and the like are required, and a slab technique is used to form these regions. Lithography is basically based on the principle that the photoresist is exposed to light through a mask to change its properties. The photoresist film in which the light is melted in the solvent is called a positive photoresist film, and the photoresist film in which the light is not dissolved in the solvent is called a negative photoresist film. Whatever type of photoresist film is used, the exposed and unexposed portions of the light are generated depending on the pattern formed on the mask. When the photoresist film is melted with a solvent, the pattern of the mask is transferred to the semiconductor substrate. When the semiconductor substrate is etched using the pattern of the photosensitive film as a mask, a desired pattern is formed on the semiconductor substrate.
한편, 근래에 반도체 제조공정에 이온주입(ion implantation)기술이 널리 사용되고 있다. 이온주입이란 에너지를 갖는 하전입자를 반도체기판 내에 강제로 주입하여 침투시키는 공정을 말한다. 이온주입은 주로 기판의 전기적 성질을 변화시키는데 이용되고 있는데, 종래의 확산공정 대신에 또는 함께 이용되고 있다. 이온을 주입시키는 에너지는 보통 30~300keV 정도이고 이온주입량(dose)은 1011~1016개/cm2 정도이다. 이온주입의 주요 장점은 확산에 의한 불순물도핑보다 도핑량의 제어를 정밀하게 할 수 있고 재현성이 우수하며 확산공정보다 낮은 온도에서 실시할 수 있다는 점이다. 그러나, 이온주입은 근본적으로 기계적으로 도펀트(dopant)를 반도체기판에 침투시키는 것이기 때문에 반도체의 고유 격자구조를 파괴하여 손상(lattice defect)을 일으키는 문제가 있다.On the other hand, ion implantation technology has been widely used in semiconductor manufacturing processes in recent years. Ion implantation refers to a process of forcibly injecting charged particles with energy into a semiconductor substrate. Ion implantation is mainly used to change the electrical properties of the substrate, and is used instead of or in conjunction with conventional diffusion processes. The energy for implanting ions is usually about 30 to 300 keV and the dose is about 10 11 to 10 16 / cm 2 . The main advantage of ion implantation is that the doping amount can be controlled more precisely than the doping of impurities by diffusion, and it is excellent in reproducibility and can be carried out at a lower temperature than the diffusion process. However, since ion implantation is essentially mechanically infiltrating dopant into the semiconductor substrate, there is a problem in that it destroys the intrinsic lattice structure of the semiconductor and causes damage.
본 발명의 목적은 이온주입에 의해 발생하는 반도체기판의 손상을 적극적으로 이용하여 EEPROM의 터널영역의 크기를 축소하는 방법을 제공하는 것이다.An object of the present invention is to provide a method for reducing the size of a tunnel region of an EEPROM by actively utilizing damage of a semiconductor substrate caused by ion implantation.
위 목적을 달성하기 위하여, 본 발명은 드레인영역 위에 터널산화막과 부유게이트(floating gate) 전극이 형성된 EEPROM의 터널산화막 영역(터널영역)을 축소하는 방법에 대한 것이다. 본 발명에 따른 방법은 반도체기판 위에 드레인영역을 형성하고 이 드레인영역 위에 산화막을 성장한 후, 산화막이 형성된 반도체기판에 감광막을 덮고 에칭하여 터널영역을 형성하는 단계와, 터널영역이 형성된 감광막을 마스크로 하여 이온주입을 실시하되, 터널영역이 형성된 감광막 측벽의 바깥 방향에서 안쪽으로 비스듬히 360°돌아가면서 이온주입을 하여 이온주입에 의한 드레인영역 손상부가 고리형상으로 형성되도록 하는 단계와, 터널영역의 산화막을 제거하여 드레인영역을 노출시키는 단계와, 이온주입에 의해 손상을 받은 부분이 손상받지 않은 부분보다 산화 속도가 빠른 성질을 이용하여 터널영역의 드레인영역에 이차로 산화막을 성장하는 단계와, 터널영역의 이차 산화막 위에 부유게이트 전극을 형성하는 단계를 포함한다. 상기 터널영역은 평면에서 보아 원형인 것을 특징으로 하고, 부유게이트는 다결정실리콘(poly-Si)인 것을 특징으로 한다.In order to achieve the above object, the present invention relates to a method for reducing the tunnel oxide region (tunnel region) of the EEPROM in which the tunnel oxide layer and the floating gate electrode are formed on the drain region. The method according to the present invention comprises forming a drain region on a semiconductor substrate and growing an oxide film on the drain region, then covering and etching the photosensitive film on the semiconductor substrate on which the oxide film is formed to form a tunnel region, and using the photosensitive film having the tunnel region as a mask. Ion implantation, and the ion implantation is performed while turning 360 degrees obliquely inward from the outer side of the sidewall of the photosensitive film where the tunnel region is formed so that the drain region damaged portion by the ion implantation is formed in a ring shape, and the oxide film of the tunnel region is formed. Removing the oxide to expose the drain region, and growing the oxide film in the drain region of the tunnel region using the property of faster oxidation rate than the portion damaged by the ion implantation; Forming a floating gate electrode on the secondary oxide layer. The tunnel region may be circular in plan view, and the floating gate may be polycrystalline silicon (poly-Si).
이하, 도1~5를 참조하여 본 발명에 대해 설명한다. 각 도면의 (a)는 종단면도를 나타내고 (b)는 평면도를 나타낸다.Hereinafter, the present invention will be described with reference to FIGS. 1 to 5. (A) of each figure shows a longitudinal cross-sectional view, and (b) shows a top view.
(I) 원하는 터널패턴으로 감광막(photoresist)을 형성하기 위한 공정으로서, 반도체기판 위에 드레인영역(1)을 형성하고 이 드레인영역(1)에 산화막(3)을 성장한 후, 일반적인 석판기술에 따라 산화막(3) 위에 감광막(5)을 덮고 터널패턴이 그려진 마스크(미도시)를 통해 감광막에 자외선을 쬔다. 그러면 감광막(5)에는 자외선에 반응한 부분과 그렇지 않은 부분이 생기는데 자외선에 반응한 부분(포지티브형 감광막일 경우)을 에칭으로 제거하면 도1에서와 같이 원형의 패턴이 형성된다. 이 원형패턴(참조번호 7)이 바로 터널이 될 곳이다. 종래에는 이렇게 원형패턴을 갖는 감광막(5)을 마스크로 하여 다시 드레인영역에 대해서 에칭하여 터널을 형성하였지만, 본 발명에서는 이후의 공정과 같이 이온주입법을 이용한다.(I) A process for forming a photoresist in a desired tunnel pattern, wherein a drain region 1 is formed on a semiconductor substrate and an oxide film 3 is grown in the drain region 1, followed by an oxide film according to a general slab technique. (3) The photosensitive film was covered with ultraviolet rays through a mask (not shown) covering the photosensitive film 5 and a tunnel pattern. Then, the photoresist film 5 has a portion that reacts with ultraviolet rays and a portion that does not. When the portion that reacts with ultraviolet rays (for a positive photoresist film) is removed by etching, a circular pattern is formed as shown in FIG. This circular pattern (reference number 7) is where the tunnel will be. Conventionally, the tunnel is formed by etching the drain region again using the photosensitive film 5 having the circular pattern as a mask, but the ion implantation method is used in the present invention as in the following steps.
(II) 감광막(5) 위에 이온주입(ion implantation)을 실시한다. 이온주입을 하되 수직에서 이온빔을 쏘지 않고 도2에서와 같이 감광막(5)의 원형패턴의 원주 바깥 방향에서 안쪽으로 비스듬히 360°돌아가면서 이온빔을 쏜다. 이렇게 이온주입을 하면 감광막의 패턴 측벽에서 그림자효과가 일어나 원형 터널패턴의 원주쪽은 깊게, 중심쪽으로 갈수로 얕게 이온빔이 침투하여 참조번호 9와 같이 드레인영역(1) 표면에 이온주입 손상부가 고리형상으로 그 침투깊이가 다르게 형성된다. 이를 손상환(9)이라 부르기로 한다. (II) Ion implantation is performed on the photosensitive film 5. While ion implantation is performed, the ion beam is shot while turning 360 degrees obliquely inward from the circumferential direction of the circular pattern of the photosensitive film 5 without shooting the ion beam vertically. The ion implantation causes shadow effect on the pattern sidewall of the photoresist film, and the ion beam penetrates the circumferential side of the circular tunnel pattern deeply and shallowly toward the center. The penetration depth is formed differently. This will be called damaged ring (9).
이 공정에서는 침투깊이를 도2에서와 같이 제어하기 위하여 이온주입의 경사각도를 적절히 설정하는 것이 중요한데, 최종적으로 원하는 터널영역의 크기에 따라 이온주입하는 경사각을 적절히 설정하여야 한다. 예를 들면, 이온주입 경사각을 작게 하면 손상환(9)의 환폭이 작아지기 때문에 터널영역의 축소율이 작아지고, 이온주입 경사각을 크게 하면 손상환(9)의 환폭이 커지기 때문에 보다 작은 터널영역을 얻을 수 있다[이하 (IV)단계 참조]. 이는 당업자라면 용이하게 실시할 수 있는 사항이다. 또한, 이온주입하는 도펀트(dopant)는 실리콘기판에 손상을 크게 주는 물질인 것이 바람직하다. 본 발명을 구현하려면 상기 손상환(9)이 뚜렷하게 형성되어야 하기 때문이다.In this process, it is important to appropriately set the inclination angle of ion implantation in order to control the penetration depth as shown in FIG. 2, and finally, the inclination angle of ion implantation must be appropriately set according to the desired tunnel area size. For example, the smaller the ion implantation inclination angle, the smaller the ring width of the damaged ring 9, and the smaller the tunnel area shrinkage, and the larger the ion implantation inclination angle, the larger the ring width of the damaged ring 9, the smaller the tunnel area can be obtained. (See step (IV) below). This is a matter that can be easily carried out by those skilled in the art. In addition, the dopant implanted with ions is preferably a material that greatly damages the silicon substrate. This is because the damaged ring 9 must be clearly formed to implement the present invention.
(III) 감광막(5)을 마스크로 하여 터널영역(7)의 산화막(3)을 제거한 후 감광막(5) 전체를 벗겨낸다. 산화막(3)의 제거는 일반적인 에칭법을 사용하고 감광막(5)의 제거는 일반적인 용제를 사용해서 한다. (III) After removing the oxide film 3 of the tunnel region 7 using the photosensitive film 5 as a mask, the entire photosensitive film 5 is peeled off. The oxide film 3 is removed using a general etching method and the photosensitive film 5 is removed using a general solvent.
(IV) 터널영역(7)에 다시 산화막을 성장한다. 이 때 이온주입에 의해 손상을 받은 손상환(9) 부분이 손상받지 않은 부분보다 산화 속도가 두 배 이상 빠르기 때문에(격자결함이 많기 때문에 O2와 결합될 수 있는 기회가 많아지기 때문이다), 도4의 (a)에서와 같이 9a 부분이 9b 부분보다 산화막이 두껍게 성장된다. 따라서, 결과적으로 원래의 터널영역(7)보다 축소된 터널영역(9b)이 형성된다. 이 축소된 터널영역(9b)의 크기는 손상환(9)의 환폭에 의해 조절될 수 있는데, 궁극적으로 이온주입에 의해 드레인영역(1)에 손상을 입히는 정도에 의해 제어할 수 있다.(IV) An oxide film is grown in the tunnel region 7 again. At this time, since the damaged ring (9) portion damaged by ion implantation is more than twice as fast as the undamaged portion (because there are many lattice defects, there is more opportunity to combine with O 2 ). As shown in (a) of FIG. 4, the oxide film is grown thicker in the 9a portion than in the 9b portion. As a result, the tunnel area 9b which is smaller than the original tunnel area 7 is formed. The size of the reduced tunnel region 9b can be controlled by the ring width of the damaged ring 9, which can ultimately be controlled by the extent of damaging the drain region 1 by ion implantation.
(V) 터널영역(9b)에 다결정실리콘(poly-Si)을 증착하여 최종적으로 부유게이트전극(11)을 형성한다. (V) Poly-Si is deposited in the tunnel region 9b to finally form the floating gate electrode 11.
이상에서와 같이, 본 발명에 따르면 종래의 석판기술에 의한 터널영역 축소의 한계를 극복하여 이온주입으로써 보다 더 축소된 터널영역을 얻을 수 있기 때문에 메모리소자의 크기를 줄이면서 저장용량을 극대화할 수 있다.As described above, according to the present invention, it is possible to maximize the storage capacity while reducing the size of the memory device because the tunnel area can be obtained by ion implantation by overcoming the limitation of the tunnel area reduction by the conventional slab technology. have.
도1은 감광막에 패턴을 형성하는 공정을 나타내는 그림으로서, (a)는 단면도 (b)는 평면도이다.1 is a diagram showing a step of forming a pattern on a photosensitive film, where (a) is a sectional view and (b) is a plan view.
도2는 이온주입을 하는 공정을 나타내는 그림으로서, (a)는 단면도 (b)는 평면도이다.2 is a diagram showing a step of ion implantation, in which (a) is a cross sectional view (b) is a plan view.
도3은 감광막을 제거한 후의 모습을 나타내는 그림으로서, (a)는 단면도 (b)는 평면도이다.3 is a view showing the state after removing the photosensitive film, (a) is a cross-sectional view (b) is a plan view.
도4는 터널 영역에 다시 산화막을 성장하는 공정을 나타내는 그림으로서, (a)는 단면도 (b)는 평면도이다.4 is a diagram showing a process of growing an oxide film in the tunnel region again, (a) is a sectional view (b) is a plan view.
도5는 축소된 터널 영역에 다결정실리콘을 증착한 것을 나타내는 단면도이다.5 is a cross-sectional view showing deposition of polysilicon in a reduced tunnel region.
도6은 EEPROM의 개략적 구조를 나타내는 단면도이다. Fig. 6 is a sectional view showing the schematic structure of the EEPROM.
<도면의 주요 부호에 대한 설명><Description of Major Symbols in Drawing>
드레인영역(1) 산화막(3)Drain region (1) Oxide film (3)
감광막패턴(5) 터널영역(7)Photoresist pattern (5) Tunnel area (7)
손상환(9) 손상환의 환폭(9a)Damaged ring (9) Damaged ring width (9a)
축소된 터널영역(9b) 부유게이트(floating gate) 전극(11)Reduced tunnel region 9b floating gate electrode 11
반도체기판(101) 드레인영역(103)Semiconductor Substrate 101 Drain Region 103
소스영역(105) 게이트산화막(107)Source region 105 Gate oxide film 107
터널산화막(109) 부유게이트전극(111)Tunnel oxide film 109, floating gate electrode 111
게이트전극(113)Gate electrode 113
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5393684A (en) * | 1991-12-13 | 1995-02-28 | Sgs-Thomson Microelectronics S.R.L. | Method of making thin oxide portions particularly in electrically erasable and programmable read-only memory cells |
| US5750428A (en) * | 1996-09-27 | 1998-05-12 | United Microelectronics Corp. | Self-aligned non-volatile process with differentially grown gate oxide thickness |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5393684A (en) * | 1991-12-13 | 1995-02-28 | Sgs-Thomson Microelectronics S.R.L. | Method of making thin oxide portions particularly in electrically erasable and programmable read-only memory cells |
| US5527728A (en) * | 1991-12-13 | 1996-06-18 | Sgs-Thomson Microelectronics S.R.L. | Method of making thin oxide portions consisting of gate and tunnel oxides particularly in electrically erasable and programmable read-only memory cells |
| US5750428A (en) * | 1996-09-27 | 1998-05-12 | United Microelectronics Corp. | Self-aligned non-volatile process with differentially grown gate oxide thickness |
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