KR100494694B1 - Apparatus for thin film transistor liquid crystal display - Google Patents

Abstract

The present invention relates to a thin film transistor liquid crystal display device, comprising a front gate line and a rear gate line; A data line defining the front gate line and the rear gate line and two unit pixel units; A common line which distinguishes the two unit pixel units up and down; A first pixel electrode and a second pixel electrode of each of the two unit pixel units; And a first thin film transistor and a second thin film transistor, wherein the afterimage is reduced by the parasitic capacitance Cgs' formed between the rear gate and the pixel electrode in the common common electrode structure to reduce the afterimage, and use the common common electrode. The electrode has an effect of improving the image quality by reducing the flicker with the parasitic capacitance Cgs "overlapping between the front gate and the pixel electrode. In addition, by adopting a driving method to change the direction of the scanning signal in the forward / reverse direction. Cgs' and Cgs "function, and the pixel electrode is a multi-level driving method to compensate for falling by ΔVp at the front gate to reduce flicker and to discharge afterimage to discharge at the rear gate. It works.

Description

Thin Film Transistor Liquid Crystal Display {APPARATUS FOR THIN FILM TRANSISTOR LIQUID CRYSTAL DISPLAY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor liquid crystal display device, and more particularly, to a thin film transistor liquid crystal display device having improved image quality by reducing flicker and afterimage with an improved electrode structure.

In general, a thin film transistor liquid crystal display device (hereinafter, TFT-LCD) is a device that uses a thin film transistor as a switching element and implements an image by changing an arrangement of liquid crystals according to an electric field formed between electrodes, and replaces a conventional cathode ray tube. It is used in various imaging devices.

A nematic mode TFT-LCD using a vertical electric field has been developed and used. In order to improve a narrow viewing angle, which is a disadvantage, an in-plane switching (IPS) mode and a fringe field switching (hereinafter referred to as FFS) using a lateral electric field method are used. Mode thin film transistor liquid crystal display device has been developed.

Such a transverse electric field type IPS or FFS TFT-LCD has the advantage of enabling high-speed response of the liquid crystal as well as the wide viewing angle. In particular, the FFS TFT-LCD has the advantage of high light transmittance and aperture ratio by using a transparent electrode.

However, the liquid crystal display device according to the related art has the following problems.

In the thin film transistor liquid crystal display device according to the prior art, IPS or FFS TFT-LCD using a transverse electric field flickers and image sticking due to flicker due to horizontal and vertical electric fields present on the same plane. ) There is a problem that the phenomenon is severe.

In order to solve this problem, as illustrated in FIG. 1, the pixel electrode 9 on the lower substrate 1 is disposed to overlap the common electrode 7 and the rear gate 3b. Here, the front gate 3a and the data line 7 vertically intersect, and a thin film transistor 11 is disposed at the vertical intersection thereof and is in contact with the pixel electrode 9.

As described above, the parasitic capacitance (hereinafter, Cgs) formed by overlapping the pixel electrode 9 and the rear gate line 3b is the rear end of the charge and ions charged to the pixel electrode 9 due to stress. The current flows when the gate 3b is turned on / off, that is, serves to discharge, thereby reducing afterimages.

However, the electrode structure as described above discharges the pixel voltage charged in the capacitance capacitance (hereinafter, Cst) when the rear gate is turned on, thereby causing a feedthrough voltage difference (ΔVp), which worsens the flicker phenomenon. There is a problem.

In addition, since Cst and Cgs are adjacent to each other in parallel, the common electrode and the rear gate line are adjacent to each other, so that a leakage current is generated under the influence of an electric field therebetween, thereby preventing the afterimage reduction effect of Cgs.

Accordingly, the present invention has been made to solve the problems of the prior art, an object of the present invention is to have a common common electrode structure to reduce the afterimage and flicker phenomenon in each parasitic capacitance to improve the image quality The present invention provides a transistor liquid crystal display device.

According to an aspect of the present invention, a thin film transistor liquid crystal display device includes: a substrate; A front gate line and a rear gate line which are laterally spaced apart on the substrate, each of which comprises a pair of gate lines; A data line arranged in a longitudinal direction to be substantially perpendicular to the front gate line and the rear gate line to be spaced apart to define two unit pixel units; A common line arranged transversely on the substrate so as to distinguish the two unit pixel units into a first unit pixel unit and a second unit pixel unit; A first pixel electrode disposed in the first unit pixel portion to partially overlap the common line to form a storage capacitance, and partially overlapping the front gate line to form a first parasitic capacitance; A second pixel electrode disposed in the second unit pixel and partially overlapping the common line to form a storage capacitance, and partially overlapping the rear gate line to form a second parasitic capacitance; And a first thin film transistor formed in the first unit pixel portion, and a second thin film transistor formed in the second unit pixel portion.

In addition, the thin film transistor liquid crystal display device according to the present invention includes a gate integrated circuit for emitting a scan signal; A gate line through which the scan signal is transmitted; And a panel made up of frames defined as data lines that transmit display signals perpendicular to the gate lines, wherein the scan signals are arranged in any one column frame of the panel by a gate integrated circuit having a forward scan method. In the forward direction, in the arbitrary one-row array frame, or in the reverse direction, or in any one-row frame of the panel by the gate integrated circuit having a reverse scanning method, in the reverse direction, and in the arbitrary one-row array frame Is characterized in that it faces in the forward direction. In addition, the thin film transistor liquid crystal display device according to the present invention includes a gate integrated circuit for emitting a scan signal; A gate line through which the scan signal is transmitted; And a panel made up of frames defined as data lines that transfer display signals perpendicular to the gate line, wherein the scan signal is a forward scan disposed at the left end of the panel in the leftmost column of the panel. The gate integrated circuit has a positive direction, and in the frame of the uppermost column of the panel, the gate integrated circuit has a reverse direction scanning gate disposed at the right end of the panel.

Hereinafter, a thin film transistor liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings.

In the thin film transistor liquid crystal display device according to the present invention, as shown in FIG. 2, several gate lines 103a and 103b are formed on a substrate 101 composed of a transparent insulator such as glass ( 103c, 103d, data line 105, common line 107, pixel electrodes 109a and 109b, and thin film transistors 111a and 111b. Each detailed description is as follows.

First, several gate lines 103a, 103b, 103c and 103d are arranged on the substrate 101 in the lateral direction. The several gate lines 103a, 103b, 103c, and 103d are shear gate lines 103a and 103b arranged horizontally on the substrate 101 according to their positions, and the shear gate lines 103a. The rear gate lines 103c and 104d may be spaced apart from the bottom 103b to be spaced apart from the bottom 103b.

Herein, when the common electrode 107 is arbitrarily assumed to be an N column electrode, the upper gate line 103a of the front gate lines 103a and 103b is replaced by the N-1 column gate line and the lower gate line 103b. It can be defined as an N column gate line. Similarly, the upper gate line 103c of the lower gate lines 103c and 103d may be defined as an N + 1 column gate line and the lower gate line 103d as an N + 2 column gate line.

Secondly, data lines 105 are arranged in the longitudinal direction on the substrate 101. The data line 105 defines the complex pixel unit 110 having a predetermined space with the front gate lines 103a and 103b and the rear gate lines 103c and 103d spaced apart from each other.

Third, the common electrode 107 is formed in the complex pixel unit 110 defined above. Here, the common electrode 107 includes a body portion 107a which is arranged in the horizontal direction, and several branch portions 107b extending in the longitudinal direction extend from the body portion 107a. Here, the body portion 107a of the common electrode 107 may be divided into two unit pixel units, that is, the first unit pixel unit 110a and the second unit pixel unit 110b by dividing the complex pixel unit 110 up and down. Define. Therefore, the first unit pixel unit 110a and the second unit pixel unit 110b share the common line 107.

Fourth, a first pixel electrode 109a is formed in the first unit pixel portion 110a, and a second pixel electrode 109b is formed in the second unit pixel portion 110b. The first pixel electrode 109a partially overlaps the body portion 107a of the common line to form a storage capacitance Cst (C), and partially overlaps the shear gate lines 103a and 103b to form a first parasitic. The capacitance capacitance Cgs' (A) is formed. In addition, the second pixel electrode 109b partially overlaps the body portion 107a of the common line to form a storage capacitance Cst (C), and partially overlaps the rear gate lines 103c and 103d. The parasitic capacitance Cgs "(B) is formed.

Fifth, a first thin film transistor 111a is formed in the first unit pixel portion 110a, and a second thin film transistor 111b is formed in the second unit pixel portion 110b.

In the thin film transistor liquid crystal display device having the above structure, the upper and lower pixel electrodes 109a and 109b share one common electrode 107 to form a storage capacitance Cst.

On the other hand, when the scanning direction is downward (forward direction) from top to bottom, the order of the gate line and the common electrode is as follows: N-1 column gate line 103a, N column gate line 103b, N column common electrode. (107), N + 1 column gate line 103c, N + 1 column gate line 103d, ... in order.

Here, the first parasitic capacitance Cgs' is formed between the first pixel electrode 109a and the front end gate lines 103a and 103b as described above. As shown in FIG. When the signal falls from the on line to the off line, a signal such as (a) of FIG. 3 is applied to the N-1 column gate line. As a result, a charging effect occurs in the first pixel electrode 109a through the first parasitic capacitance Cgs', thereby compensating for a drop in feedthrough voltage ΔVp to reduce flicker.

Meanwhile, as described above, the second parasitic capacitance Cgs ″ is formed between the second pixel electrode 109b and the rear gate lines 103c and 103d. As illustrated in FIG. 3, the N + When the one-column gate line falls from on to off, a signal such as (c) of FIG. 3 is applied to the N + 2-column gate line, as a result of the second parasitic capacitance. Through the Cgs ″, the charge in the second pixel electrode 109b is bypassed to the N + 2 column gate line. Therefore, in the presence of direct current (DC) stress, the residual image is reduced by discharging the residual charges present at the interface of the protective film (not shown), the liquid crystal layer (not shown), the alignment film (not shown), and the like.

The above structure can reduce the afterimage and the flicker at the same time because one pixel simultaneously has the first parasitic capacitance Cgs' and the second parasitic capacitance Cgs "

If the scanning direction is in the reverse direction from bottom to top, it is necessary to drive the panel at a higher frequency since the magnitude of the panel frequency is 1/2 of the magnitude of the forward frequency.

Accordingly, the thin film transistor liquid crystal display according to the present invention is a panel including frames defined by a gate line through which a scan signal from a gate integrated circuit is transmitted and a data line through which a display signal is transmitted. The scan signal is transmitted together.

First, as shown in FIG. 4, by means of a gate integrated circuit (not shown) having a scanning method in a forward direction (downward), any frame 50 of the panel is in the forward direction, that is, the order 50a, 50b, 50c, 50d. The scan signal is transmitted. Then, the arbitrary one-order row frame 51 allows scanning signals to be transmitted in the reverse direction (upward), that is, in the order of 51a, 51b, 51c, and 51d.

Although not shown in the drawing, if the scanning method of the gate integrated circuit (not shown) is reverse (upward), the scan signal is reversed (upward) in an arbitrary frame 50, that is, reference numerals 50d, 50c, 50b, The scanning signals are transmitted in the order of 50a. The arbitrary blocking frame 51 causes the scanning signals to be transmitted in the forward direction (downward), that is, in the order of 51d, 51c, 51b, and 51a.

Alternatively, as shown in FIG. 5, for example, the leftmost column frame 50 of the panel may be in a forward direction by a gate integrated circuit (not shown) having a forward (downward) scanning method disposed at the left end of the panel. That is, scan signals are transmitted in the order of 50a, 50b, 50c, and 50d, and the transfer method is directed to the right side of the panel. The uppermost column frame 51 of the panel is reversed by gate integrated circuits (not shown) having a reverse (upward) scanning method disposed at the right end of the panel, that is, the order 51a, 51b, 51c, and 51d. The scan signal is transmitted to the left side of the panel.

As a result, even if the panel is driven at the same frequency by the forward and backward scanning method or the dual gate scanning method, the flicker phenomenon that the screen flickers does not occur.

Various embodiments can be easily implemented as well as self-explanatory to those skilled in the art without departing from the principles and spirit of the present invention. Accordingly, the claims appended hereto are not limited to those already described above, and the following claims are intended to cover all of the novel and patented matters inherent in the invention, and are also common in the art to which the invention pertains. Includes all features that are processed evenly by the knowledgeable.

As described above, the thin film transistor liquid crystal display according to the present invention has the following effects.

In the present invention, the afterimage is reduced by the parasitic capacitance Cgs " formed overlapping between the rear gate and the pixel electrode in the common common electrode structure, and overlapped between the front gate and the pixel electrode in other pixel electrodes using the common common electrode. With the parasitic capacitance Cgs', the flicker is reduced to improve the image quality.

In addition, in the present invention, the driving method of changing the direction of the scanning signal in the forward / reverse direction is adopted to simultaneously have the functions of Cgs' and Cgs ", and the pixel electrode is multi-level driving type in the front gate. Compensation for falling by ΔVp reduces the flicker, and gives the discharge (Discharging) at the rear gate to reduce the afterimage.

1 is a plan view of a thin film transistor liquid crystal display device according to the prior art.

2 is a plan view of a thin film transistor liquid crystal display device according to the present invention;

3 is a signal waveform of a front gate and a rear gate in a thin film transistor liquid crystal display according to the present invention.

4 is a plan view showing a forward and backward scanning method in the thin film transistor liquid crystal display device according to the present invention.

5 is a plan view illustrating a dual gate scanning method in a thin film transistor liquid crystal display device according to an exemplary embodiment of the present invention.

Explanation of symbols on main parts of drawing

101: substrate 103a, 103b, 103c, 103d: gate line

105: data line 107: common electrode

109a and 109b: pixel electrode 110: unit pixel

111a, 111b: thin film transistor

Claims (4)

Board; A front gate line and a rear gate line which are laterally spaced apart on the substrate, each of which comprises a pair of gate lines; A data line arranged vertically on the substrate to be substantially perpendicular to the spaced apart front and rear gate lines and the rear gate line; A common line arranged transversely on the substrate so as to distinguish the two unit pixel units into a first unit pixel unit and a second unit pixel unit; A first pixel electrode disposed in the first unit pixel portion to partially overlap the common line to form a storage capacitance, and partially overlapping the front gate line to form a first parasitic capacitance; A second pixel electrode disposed in the second unit pixel and partially overlapping the common line to form a storage capacitance, and partially overlapping the rear gate line to form a second parasitic capacitance; And And a second thin film transistor formed in the first unit pixel portion, and a second thin film transistor formed in the second unit pixel portion. A gate integrated circuit for emitting a scan signal; A gate line through which the scan signal is transmitted; And a panel made up of frames defined as data lines that transfer display signals perpendicular to the gate lines. The scanning signal is directed in the forward direction in any one-column frame of the panel by the gate integrated circuit having the forward-scanning method, and in the opposite direction in the arbitrary one-column blocking frame, Or a gate integrated circuit having a reverse scanning method in a reverse direction in any one-row frame of the panel and in a forward direction in the arbitrary one-row array frame. A gate integrated circuit for emitting a scan signal; A gate line through which the scan signal is transmitted; And a panel made up of frames defined as data lines that transfer display signals perpendicular to the gate lines. The scan signal is directed in a forward direction by a gate integrated circuit having a forward scanning method disposed in the leftmost frame of the panel in a leftmost frame of the panel, and disposed in the right end of the panel in a frame of the rightmost column of the panel. A thin film transistor liquid crystal display device, which faces in a reverse direction by a gate integrated circuit having a reverse scanning method. The method of claim 3, And the scan signal directed to the forward direction is transmitted to the right direction of the panel, and the scan signal directed to the reverse direction is transmitted to the right direction of the panel.