KR100493103B1 - Apparatus for synchronization acquisition in asynchronous imt-2000 mobile communication system and method thereof - Google Patents

Abstract

According to the present invention, in a next-generation mobile communication system having a first transmitting antenna and a second transmitting antenna and transmitting a reference channel signal by applying transmit diversity, the reference channel signal is received to acquire synchronization of the base station. An apparatus comprising: a first correlation bank for correlating a reference channel signal transmitted through the first transmit antenna with scrambling codes generated at an input controller, and a transmit diversity controller for transmitting a reference channel signal transmitted through the second transmit antenna A second correlation bank that correlates with the scrambling codes generated in the second generation, and each of the scrambling codes in the code group of the base station to which the base station belongs, is generated when the synchronization acquisition device performs a three-step cell search operation. When performing the multipath search, the search in the step 3 cell search The transmit diversity which inputs the scrambling codes generated by the phase shifting of the scrambling code and the scrambling codes generated by the input controller, and multiplies the modulation pattern applied to the second transmitting antenna to output to the second correlator. And a controller.

Description

Synchronization Acquisition Apparatus and Method in Next Generation Mobile Communication System of Asynchronous Method {APPARATUS FOR SYNCHRONIZATION ACQUISITION IN ASYNCHRONOUS IMT-2000 MOBILE COMMUNICATION SYSTEM AND METHOD THEREOF}

TECHNICAL FIELD The present invention relates to a next generation (IMT-2000) mobile communication system, and more particularly, to an apparatus and method for collectively acquiring synchronization for an asynchronous mobile communication system.

As the Mobile Communication System develops, Code Division Multiple Access (CDMA) is referred to as International Mobile Telecommunication- IMT-2000, a next-generation communication system. 2000). The IMT-2000 refers to a wired / wireless integrated next-generation communication service providing global roaming and multimedia services such as voice, high-speed data, and video in land and satellite environments. The international standard for IMT-2000 is the wideband code division multiple access (W-CDMA: W-CDMA), which is mainly the synchronous CDMA 2000 scheme led by North America, and the asynchronous scheme led by Europe (W-CDMA). Can be distinguished in a manner. On the other hand, UMTS (Universal Mobile Telecommunication System) is a European next-generation mobile communication system, a mobile communication system using the W-CDMA method, which is an asynchronous method based on the Global System for Mobile communication (GSM) method. The UMTS (Universal Mobile Telecommunication System) basically uses a CDMA scheme, but is an asynchronous base station system. Each base station performs an asynchronous operation. On the other hand, the CDMA 2000 mobile communication system is a synchronous base station system based on the IS-95 mobile communication system, and each base station performs synchronization with each other. User equipment (UE) operating in the UMTS mobile communication system and the CDMA 2000 mobile communication system includes an initial cell search, a multipath search, a neighbor cell search, and a neighbor cell search. You must perform a re-acquisition operation.

However, the UMTS system is an asynchronous system, and the IS-95 and CDMA 2000 systems are synchronous systems, and there is a difference between the initial cell search, the multipath search, and the neighbor cell search and reacquisition operation. Next, the synchronization process of the UMTS communication system, that is, initial cell search, multipath search, neighbor cell search and recapture operation will be described.

In order to distinguish each of the base stations in a UMTS communication system, a method of allocating different scrambling codes corresponding to each of the base stations is used. For example, when the cells constituting the asynchronous base station system, that is, 512 base stations exist, each of the 512 base stations is assigned with a different scrambling code among 512 scrambling codes to identify itself. Will be used as the code Since the base station transmits a signal using a scrambling code for identifying the base station itself, user equipment (UE) which is to be serviced by the base station may also identify a scrambling code of the base station. Only when it is possible to receive the signal provided by the base station normally.

First, in the UMTS system, different scrambling codes, that is, cell specific codes, are allocated to each of the base stations in order to distinguish each of the base stations. For example, if there are 512 cells constituting the UMTS, and each base station has one base station, each of the 512 base stations allocates a different one of the 512 cell identification codes. The code is used to identify the base station itself. Since the base station transmits a signal using a cell identification code for identifying the base station itself, the mobile stations to be serviced by the base station must also be able to identify the cell identification code of the base station to receive the signal provided by the base station normally. It is possible.

As described above, in order to normally receive the signal provided by the base station, the mobile station should check the scrambling code of the received signal with the strongest energy among the signals received from the adjacent base stations. The confirmation process becomes the cell search process. Meanwhile, the cell search is performed in various forms according to the situation. The mobile station continuously searches for the initial cell search for finding the scrambling code being used by the base station of the serving cell when the mobile station is powered on and the obtained scrambling code continuously. Multipath search for detecting a multipath signal component of a received signal for Rake demodulation in the held state, and the mobile station itself must handover when the mobile station is in a handover region. Search for neighbor cells to search for neighbor cells, and finally, pseudo-noise lost in the sleep state when selecting and using "slotted mode" in the idle state or waking from the sleep state. There is a reacquisition of reacquiring code timing.

However, since the mobile station needs to search for each of the base stations constituting the UMTS in order to search for the base station to which the mobile station belongs, the mobile station eventually needs to search for each of the 512 base stations constituting the UMTS. will be. Since the mobile station searches for each of the 512 base stations constituting the UMTS, the mobile station checks the cell identification code of each of the 512 base stations. Therefore, it takes a long time to search the cell to which the mobile station belongs. Therefore, since it is inefficient to apply the general cell search algorithm for each base station constituting the UMTS, the mobile station implements a multi-stage cell search algorithm. In order to implement the multi-level cell search algorithm, a plurality of base stations belonging to the UMTS, for example, 512 base stations are classified into a predetermined number of groups, for example, 64 groups (Group 0 to Group 63). A different group identification code is assigned to each of the classified 64 groups to distinguish a base station group, and each base station group is composed of eight base stations. In addition, since each of the eight base stations is assigned a cell specific code, it is possible to finally search for the base station to which the mobile station itself belongs.

The multi-step cell search process described above is composed of the following three-step cell search process. First, the first step cell search process is a process in which a mobile station receives a primary synchronization channel (P-SCH) signal transmitted from a base station and finds and synchronizes slot timing received at maximum power. In the two-stage cell search process, frame synchronization and mobile station itself belong to a second synchronization channel (S-SCH: Secondary Synchronization CHannel) received by the mobile station from the base station after receiving the slot timing information found in the first-stage cell search process. This is a process of detecting a group of base stations. In the step 3 cell search, the mobile station finally searches for the base station to which the mobile station belongs with a common pilot channel (CPICH) signal transmitted from the base station based on the frame synchronization and base station group information found in the step 2 cell search. It's a process.

In the above description, the synchronization acquisition process of the UMTS communication system performing the asynchronous base station operation has been described. Next, the three-step cell search process will be described in detail.

1 is a diagram illustrating a correlator structure inside a general CDMA mobile communication system synchronization acquisition device.

Referring to FIG. 1, when a channel signal is received from a base station, the received channel signal, that is, the I-channel signal and the Q-channel signal in the form of an analog, are analog to digital converters (ADCs). The analog-to-digital converter digitally converts the analog I-channel signal and the Q-channel signal, and outputs the de-scrambler 110 and the descrambler 111. Here, the digitally converted I channel signal and Q channel signal will be referred to as an ADC_I signal and an ADC_Q signal, respectively. The descrambler 110 receives the ADC_I signal, and a scrambling code generator 105 generates the same scrambling code sc_i as the scrambling code used when the base station transmits a channel signal. Will output The descrambler 110 performs descrambling with the scrambling code output from the scrambling code generator 105 and then outputs the ADC_I signal to the first offset compensator 115. Meanwhile, the descrambler 111 inputs an ADC_Q signal to perform a descrambling with the same scrambling code sc_q generated by the scrambling code generator 105 when the base station transmits the channel signal, and then performs a second offset. Output to compensator 116.

The offset compensator 115 receives the I-channel signal output from the descrambler 110, removes the offset component shifted toward the negative (−) side, and outputs the offset component to the gain multiplier 120. That is, the offset compensator 115 has a value of -32 to +31 when 6-bit complementary format data of 2 ⁿ is input, and the offset compensator has offset offset toward negative (-). Therefore, the negative offset component is removed so that the maximum value can be detected by changing the value from -63 to +63 through the "2x () + 1" type offset compensation by multiplying the input signal by 2 and adding 1 to it. . The offset compensator 116 also performs the same operation as the offset compensator 115, and the offset compensator 116 inputs a Q channel signal output from the descrambler 111 and biases the negative component toward the negative (−) side. After eliminating the output to the gain multiplier 121. Since the gain multiplier 120 changes the number of data bits for detecting correlation energy according to the change in the synchronous cumulative and asynchronous cumulative times, the gain multiplier 120 receives the signal output from the offset compensator 115 and multiplies the gain G. The output is then output to the sync accumulator 125. The synchronous accumulator 125 performs synchronous accumulation during the period in which the influence of the frequency offset is minimized and outputs the signal output from the gain multiplier 120 to the squarer 135. Here, the synchronous accumulation period is loaded through a register of the CPU. Similarly, the gain multiplier 121 inputs the signal output from the offset compensator 115, multiplies the gain G, and outputs the multiplied gain G to the sync accumulator 126. The synchronous accumulator 126 synchronously accumulates the signal output from the gain multiplier 121 and outputs the result to the squarer 136.

The squarer 135 receives the synchronous accumulated I-channel data output from the accumulator 125 and performs a square operation and outputs the sum to the summer 140. In addition, the squarer 136 receives the synchronous accumulated Q channel data output from the accumulator 126 and performs a square operation and outputs the squared result to the summer 140. The summer 140 calculates energy by summing the synchronous accumulated I / Q channel data output from the squarer 135 and the squarer 136 and outputs the result to the asynchronous accumulator 145. . The asynchronous accumulator 145 accumulates the energy value output from the summer 140 as an asynchronous cumulative number of times and outputs the correlation energy. Here, the asynchronous accumulation section of the asynchronous accumulator 145 is loaded through a register of the CPU. Also, find the maximum value of the correlation energies and the index at that time. At this time, the index of the maximum value becomes an offset with the scrambling code transmitted from the base station to synchronize, and the mobile station can complete the synchronization acquisition with the base station with the offset.

On the other hand, in the UMTS cell search process, the three-step cell search process, as described above, identifies the cell discrimination code, that is, the scrambling code, of each of the 8 base stations belonging to the code group of the base station, and thus the scrambling code timing of the base station to which the mobile station belongs. The process of acquiring them. Therefore, the three-stage cell searcher performing the three-stage cell search process retrieves the scrambling code of the base station to which the mobile station belongs as a result of using eight different scrambling codes.

Next, a three-step cell searcher structure will be described with reference to FIG. 2.

2 is a diagram illustrating an internal structure of a three-stage cell search apparatus of a general UMTS system.

Referring to FIG. 2, as described above, in the three-step cell search process of the UMTS system, the eight scrambling codes are searched because the scrambling code of the base station to which the actual mobile station belongs is searched with eight scrambling codes. You must search for. In addition, a Tx Diversity technique is used to overcome fading, which uses two or more transmit / receive antennas. The transmit diversity is a technique for receiving a signal transmitted through the other transmit antenna when the signal transmitted through one transmit antenna decreases in signal size due to fading. In FIG. 2, it is assumed that a base station applies transmission diversity for transmitting a signal through two antennas, that is, a first antenna and a second antenna. In this manner, in consideration of the transmit diversity and the eight scrambling codes, the three-stage cell search apparatus may include two correlation banks, that is, a first correlation bank 200 for transmit diversity, as shown in FIG. And a second correlation bank 250, a scrambling code generator 240, and a transmit diversity controller 245, each of the two correlation banks 200, 250 considering the eight scrambling codes. It has eight correlators.

For convenience of description, the operation of the first correlation bank 200 in the first correlation bank 200 and the second correlation correlator in the second correlation bank 250 will be described. Let's do it.

First, the structure of the 1-1 correlator will be described.

First, an analog I channel signal and a Q channel signal received from a base station are input to an analog / digital converter (not shown), and the analog / digital converter digitally converts the analog I channel signal and the Q channel signal. After the output to the descrambler 211 and the descrambler 221, respectively. Here, the digitally converted I channel signal and Q channel signal will be referred to as an ADC_I signal and an ADC_Q signal, respectively. The descrambler 211 descrambles the ADC_I signal with the same scrambling code as the scrambling code generated by the scrambling code generator 240 when the base station transmits the channel signal, and outputs the descrambler to the offset compensator 212. The offset compensator 212 receives the I-channel signal output from the descrambler 211, removes the offset component shifted toward the negative (−) side, and outputs the offset component to the gain multiplier 213. The gain multiplier 213 receives a signal output from the offset compensator 212 in order to adjust the number of data bits generated by correlation energy according to a change in the synchronous cumulative and asynchronous cumulative times. After multiplying by G, it outputs to the sync accumulator 214. The synchronous accumulator 214 performs synchronous accumulation and outputs the signal output from the gain multiplier 213 to the squarer 215 during a period in which the influence of the frequency offset is minimized. Here, the synchronous accumulation period is loaded through a register of the CPU. The squarer 215 receives the synchronous accumulated I-channel data output from the accumulator 214, performs a square operation, and outputs the squared operation to the summer 230.

Next, the descrambler 221 descrambles the ADC_Q signal with the same scrambling code generated by the scrambling code generator 240 when the base station transmits the channel signal, and outputs the descrambler 222 to the offset compensator 222. do. The offset compensator 222 receives the Q channel signal output from the descrambler 221, removes the offset component shifted toward the negative (−) side, and outputs the offset component to the gain multiplier 223. The gain multiplier 223 receives the signal output from the offset compensator 222 and multiplies the gain G in order to adjust the number of data bits generated by the correlation energy according to the change in the synchronous cumulative and asynchronous cumulative times. Output to sync accumulator 224. The sync accumulator 224 accumulates the signal output from the gain multiplier 223 during the period in which the influence of the frequency offset is minimized and outputs the result to the squarer 225. Here, the synchronous accumulation period is loaded through a register of the CPU. The squarer 225 receives the synchronous accumulated Q channel data output from the accumulator 224, performs a square operation, and outputs the squared operation to the summer 230.

The summer 230 sums the synchronous accumulated I channel data and the Q channel data output from each of the squarer 215 and the squarer 225 and outputs the summed data to the asynchronous accumulator 231. The asynchronous accumulator 231 accumulates the value output from the summer 230 as an asynchronous cumulative number of times and outputs the 1-1 correlation energy. Here, the asynchronous accumulation section of the asynchronous accumulator 231 is loaded through a register of the CPU. Here, the correlation energy having the maximum value in the 1-1 correlation energy and the index thereof are offsets from the scrambling code applied by the base station.

In this way, each of the eight correlators of the 1-1 correlator to the 1-8 correlator of the first correlation bank 200 detects a correlation energy, and considering the detected correlation energies, the first correlation bank. The correlation energy of 200 is detected.

Second, the structure of the 2-1 correlator will be described.

The operations of the descrambler 261, the offset compensator 262, the gain multiplier 263, the synchronization accumulator 264, and the squarer 265 in the 2-1 correlator structure are the first-first. The descrambler 211, the offset compensator 212, the gain multiplier 213, the synchronous accumulator 214, and the squarer 215 described in the correlator structure perform the same operation. In the 2-1 correlator structure, operations of the descrambler 271, the offset compensator 272, the gain multiplier 273, the synchronous accumulator 274, and the squarer 275 are performed in the 1-1 correlator structure. The descrambler 221, the offset compensator 222, the gain multiplier 223, the synchronous accumulator 224, and the squarer 225 described above are performed. 280 and the operation of the asynchronous accumulator 281 are the same as those of the summer 230 and the asynchronous accumulator 231 described in the 1-1 correlator structure. The name will be omitted.

However, the scrambling code provided to the descrambler 261 and the descrambler 271 in the 2-1 correlator structure is transferred to the descrambler 211 and the descrambler 221 of the 1-1 correlator structure. It differs from the provided scrambling code for the following reasons. The scrambling code generator 240 generates a scrambling code identical to the scrambling code applied when the base station transmits a channel. The generated scrambling code is input to a transmit diversity controller 245, and the transmit diversity controller 245 applies an antenna modulation pattern used to apply transmit diversity in the base station to the scrambling code. After the multiplication, the descrambler 261 and the descrambler 271 are output. Since the base station transmits the same signal through transmit diversity through the first antenna and the second antenna, the signal transmitted through the second antenna is different from the signal transmitted through the first antenna in order to distinguish the antenna. The modulation pattern, i.e., the second antenna modulation pattern, is multiplied. Therefore, since the second antenna modulation pattern needs to be taken into account, the transmit diversity controller 245 multiplies the scrambling code output from the scrambling code generator 240 by the antenna modulation pattern, and then demultiplexes the descrambler 261 with the descrambler 261. It outputs to the scrambler 271. The descrambler 261 descrambles the ADC_I signal with the scrambling code output from the transmit diversity controller 245 and then outputs the descrambler 262 to the offset compensator 262. In addition, the descrambler 271 descrambles the ADC_Q signal with the scrambling code output from the transmit diversity controller 245, and then outputs the descrambler 271 to an offset compensator 272.

In this way, each of the eight correlators of the second-first correlator to the second-eight correlator of the second correlation bank 250 detects a correlation energy, and considering the detected correlation energies, the second correlation bank. A correlation energy of 250 is detected. Since the correlation energy detected by the second correlation bank 200 and the correlation energy detected by the second correlation bank 250 are added later and input to a peak detector (not shown), 8 The correlation energy for the two scrambling codes can be calculated at the same time. Of course, when the transmit diversity is not applied in the base station, the mobile station can simultaneously search for two groups of base stations using two correlation banks.

On the other hand, the mobile station should receive an optimal base station multipath signal in a radio channel environment or handoff situation. In this case, the mobile station obtains the scrambling code timing of the base station to which the current mobile station belongs to itself through the three-step cell search process, and all hypotheses at regular intervals in a predetermined region, that is, a window section before and after the obtained scrambling code timing. After obtaining correlation values for the points, a plurality of correlation values, which are a peak value and above a predetermined threshold value, are detected. The index of the correlation value which is the detected peak value and the threshold value or more is a timing of the multipath signal components with a delay value from the scrambling code timing generated by the base station. In this way, the operation of searching for multipath signals that are differentiated from the initial cell search is referred to as "multipath search", and in the case of the multipath search, it must be able to perform a fast search to cope with a sudden change in the channel situation. .

Next, an internal structure of the multipath search apparatus for the multipath search will be described with reference to FIG. 3.

3 is a diagram illustrating an internal structure of a multipath search apparatus of a general UMTS system.

Referring to FIG. 3, as described above, the multipath search process of the cell search process of the UMTS system performs an initial cell search process, and then searches for multipath signals before and after scrambling code timing acquired in the initial cell search. It's a process. In FIG. 3, it is assumed that multipath search is performed on eight multipath signals. In addition, it is assumed that the base station has applied transmit diversity, and as an example, it is assumed that two transmit antennas are provided and transmit diversity is applied. Thus, considering the transmit diversity and eight multipath signal components, i.e., 8 scrambling codes, the multipath search apparatus uses two correlation banks, namely, a first correlation bank, for transmit diversity as shown in FIG. 300 and the second correlation bank 350, the scrambling code and the orthogonal variable spreading factor (OVSF) generator 340, and 8 shift registers 344, a transmit diversity controller 346, and each of the first correlation bank 300 and the second correlation bank 350 has eight correlators in consideration of the eight scrambling codes.

In FIG. 3, for convenience of description, the operation of the first correlation bank 300 in the first correlation bank 300 and the second correlation correlator in the second correlation bank 350 will be described as an example. do.

First, the structure of the 1-1 correlator will be described.

First, an analog I channel signal and a Q channel signal received from a base station are input to an analog / digital converter (not shown), and the analog / digital converter digitally converts the analog I channel signal and the Q channel signal. After the output to the descrambler 311 and the descrambler 321, respectively. Here, the digitally converted I channel signal and Q channel signal will be referred to as an ADC_I signal and an ADC_Q signal, respectively. The descrambler 311 descrambles the ADC_I signal with the scrambling code output from the 8 shift register 344 and outputs the descrambler 312 to an offset compensator 312. Here, the eight shift register 344 inputs the scrambling code and the scrambling code generated by the OVSF code generator 340 to generate eight scrambling codes shifted by 1/2 chip at a corresponding time. Here, when transmission diversity is not applied to the scrambling code generated from the scrambling code and the OVSF code generator 340, eight different hypotheses, that is, eight different hypotheses, are applied to the first correlation bank 300 and the second correlation bank 350. You can search 16 hypotheses by 1/2 chip, so It is possible to shift the chip. On the other hand, the scrambling code and the OVSF code generator 340 is not the first common pilot channel (P-CPICH: Primary-Common PIlot CHannel, hereinafter referred to as "P-SPICH") signal in the multi-path search An OVSF code applied to the S-CPICH may also be generated in consideration of a case of using a common pilot channel (S-CPICH) signal. Of course, when using the P-CPICH in the multipath search, since all base stations use the same OVSF code, the scrambling code and the OVSF code generator 340 do not generate an OVSF code separately, and use the S-CPICH. When used, since all base stations use different OVSF codes according to the base station situation, it generates an OVSF code applied to the S-CPICH of the base station to be searched. Hereinafter, for convenience of description, it is assumed that the scrambling code and the OVSF code generator 340 generate only the scrambling code. The offset compensator 312 receives the I-channel signal output from the descrambler 311, removes the offset component shifted toward the negative (−) side, and outputs the offset component to the gain multiplier 313. The gain multiplier 313 receives the signal output from the offset compensator 312 and multiplies the gain G in order to adjust the number of data bits generated by the correlation energy according to the change in the synchronous cumulative and asynchronous cumulative times. Output to sync accumulator 314. The sync accumulator 314 accumulates the signal output from the gain multiplier 313 to the squarer 315 by performing a synchronous accumulation during a period in which the influence of the frequency offset is minimized. Here, the synchronous accumulation period is loaded through a register of the CPU. The squarer 315 receives the synchronous accumulated I channel data output from the accumulator 314, performs a square operation, and outputs the squared operation to the summer 330.

Next, the descrambler 321 descrambles the ADC_Q signal with the scrambling code generated by the 8 shift register 344 and outputs the descrambler 322 to the offset compensator 322. The offset compensator 322 receives the Q channel signal output from the descrambler 321, removes the offset component shifted toward the negative (-) side, and outputs the offset component to the gain multiplier 323. The gain multiplier 323 receives the signal output from the offset compensator 322 and multiplies the gain G in order to adjust the number of data bits generated by the correlation energy according to the change of the synchronous cumulative and asynchronous cumulative times. Output to sync accumulator 324. The synchronization accumulator 324 performs the synchronization accumulation during the period in which the influence of the frequency offset is minimized and outputs the signal output from the gain multiplier 323 to the squarer 325. Here, the synchronous accumulation period is loaded through a register of the CPU. The squarer 325 receives the synchronous accumulated Q channel data output from the accumulator 324, performs a square operation, and outputs the squared operation to the summer 330.

The summer 330 sums the synchronous accumulated I channel data and Q channel data output from each of the squarer 315 and the squarer 325 and outputs the summed data to the asynchronous accumulator 331. The asynchronous accumulator 331 accumulates the value output from the summer 330 by the asynchronous cumulative number of times and outputs the first-first correlation energy. Here, the asynchronous accumulation section of the asynchronous accumulator 331 is loaded through the register of the CPU. Here, the correlation energy having the maximum value in the 1-1 correlation energy and the index thereof are offsets from the scrambling code applied by the base station.

In this way, each of the eight correlators of the first-first correlator to the eighth-correlator of the first correlation bank 300 detects correlation energy, and considering the detected correlation energies, the first correlation bank. The correlation energy of 300 is detected.

Second, the structure of the 2-1 correlator will be described.

In the 2-1 correlator structure, operations of the descrambler 361, the offset compensator 362, the gain multiplier 363, the synchronization accumulator 364, and the squarer 365 are performed in the first-first correlator. The descrambler 311, the offset compensator 312, the gain multiplier 313, the synchronous accumulator 314, and the squarer 315 described in the correlator structure perform the same operation. In the 2-1 correlator structure, operations of the descrambler 371, the offset compensator 372, the gain multiplier 373, the synchronous accumulator 374, and the squarer 375 are performed in the 1-1 correlator structure. The descrambler 321, the offset compensator 322, the gain multiplier 323, the synchronous accumulator 324, and the squarer 325 described above are performed. The operation of the 380 and the asynchronous accumulator 381 is the same as that of the summer 330 and the asynchronous accumulator 331 described in the 1-1 correlator structure. The name will be omitted.

However, the scrambling code provided to the descrambler 361 and the descrambler 371 in the 2-1 correlator structure is transferred to the descrambler 311 and the descrambler 321 of the 1-1 correlator structure. It differs from the provided scrambling code for the following reasons. The scrambling code output from the 8 shift register 344 is input to the transmit diversity controller 346, and the transmit diversity controller 346 uses the antenna modulation used to apply transmit diversity in the base station to the scrambling code. After multiplying a pattern (antenna modulation pattern) and output to the descrambler 361 and the descrambler 371. Since the base station transmits the same signal through transmit diversity through the first antenna and the second antenna, the signal transmitted through the second antenna is different from the signal transmitted through the first antenna in order to distinguish the antenna. The modulation pattern, i.e., the second antenna modulation pattern, is multiplied. Therefore, since the second antenna modulation pattern must also be taken into account, the transmit diversity controller 346 multiplies the scrambling code output from the scrambling code and the OVSF code generator 340 by the antenna modulation pattern, and then descrambles 361. ) And the descrambler 371. Then, the scrambling code output from the transmit diversity controller 346 is input to the descrambler 361 and the descrambler 371, and the descrambler 361 transmits the ADC_I signal to the scrambling code to which transmit diversity is applied. The descrambler 371 also descrambles the ADC_Q signal with a scrambling code to which transmit diversity is applied to consider the transmit diversity applied by the base station.

In this way, each of the eight correlators of the second-first correlator to the second-eight correlator of the second correlation bank 350 detects correlation energy, and considering the detected correlation energies, the second correlation bank. A correlation energy of 350 is detected. As such, the correlation energy detected by the first correlation bank 300 and the correlation energy detected by the second correlation bank 350 are later added and input to a peak detector (not shown), thereby simultaneously providing eight scrambling codes. The correlation energy for can be calculated simultaneously. Of course, when the transmit diversity is not applied in the base station, the mobile station can simultaneously search 16 hypotheses, that is, 8 chips, by using two correlation banks at the same time.

As described above, in the wideband code division multiple access mobile communication system, three steps of cell search processes for initial cell search, that is, one step cell search process, two step cell search process, three step cell search process, and multipath search Correlators must be provided corresponding to each of the multipath search processes. That is, the mobile station separately separates the general synchronization acquisition device as described with reference to FIG. 1 as well as the three-step cell search device for three-step cell search as described with reference to FIG. 2 and the multipath search device as described with reference to FIG. Must have Since a separate search device must be provided for each search process, an increase in hardware size and a cost increase can cause problems. Therefore, there is a need for a method of acquiring various motives as a simple hardware structure.

Accordingly, an object of the present invention is to provide an apparatus and method for obtaining synchronization in a next generation asynchronous mobile communication system.

Another object of the present invention is to provide an apparatus and method capable of performing a three-step cell search and a multipath search in a mobile communication system.

It is still another object of the present invention to provide an apparatus and method for synchronizing hardware minimized in a mobile communication system.

The apparatus of the present invention for achieving the above objects; In a next generation asynchronous mobile communication system in which a base station transmits a reference channel signal by applying transmission diversity with a first transmitting antenna and a second transmitting antenna, an apparatus for receiving the reference channel signal to obtain synchronization, wherein The first correlation bank correlates the reference channel signal transmitted through the first transmission antenna with the scrambling codes generated in the input controller, and the scrambling codes generated in the transmission diversity controller transmit the reference channel signal transmitted through the second transmission antenna. And a second correlation bank to correlate with each other, and when the synchronization acquisition apparatus performs a three-step cell search operation, scrambling codes of respective base stations in the base station group to which the base station belongs are generated, and the synchronization acquisition apparatus performs a multipath search. The scrambling code found in the step 3 cell search. And a transmit diversity controller for inputting the input controller generating the phase shifted scrambling codes, the scrambling codes generated from the input controller, and multiplying the modulation pattern applied to the second transmitting antenna to the second correlator. It is characterized by.

The method of the present invention for achieving the above objects; In a next generation asynchronous mobile communication system in which a base station transmits a reference channel signal by applying transmit diversity with a first transmitting antenna and a second transmitting antenna, a control method of an apparatus for receiving synchronization by receiving the reference channel signal. The scrambling codes of the base stations in the base station group to which the base station belongs are generated when the synchronization acquisition device performs a three-step cell search operation, and the three-step cell search when the synchronization acquisition device performs a multipath search. Generating scrambling codes obtained by phase shifting the scrambling code found in the step C, correlating the reference channel signal transmitted through the first transmitting antenna with the generated scrambling codes, and transmitting the generated scrambling codes by the second transmitting antenna. A reference channel signal is generated with the generated scrambling codes. Characterized by including the process concerned.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that in the following description, only parts necessary for understanding the operation according to the present invention will be described, and descriptions of other parts will be omitted so as not to distract from the gist of the present invention.

4 is a diagram illustrating an internal structure of an integrated synchronization acquisition device of a UMTS system according to an embodiment of the present invention.

Before describing FIG. 4, as described in the prior art, a user equipment (UE) in a Universal Mobile Telecommunication System (UMTS), which is a wideband code division multiple access (WCDMA) communication system, Synchronous operations such as initial cell search, multipath search, neighbor cell search and re-acquisition are performed. In the initial cell search, the mobile station receives a first synchronization channel (P-SCH) signal transmitted from a base station and finds slot timing received at maximum power among the mobile station. A two-stage cell search process for detecting frame synchronization and a base station group to which the mobile station belongs through a second synchronization channel (S-SCH) received from the base station by receiving slot timing information found in the first-stage cell search process. And a first common pilot channel (P-CPICH: Primary-Common PIlot CHannel, hereinafter " P-SPICH ") transmitted by the mobile station based on the frame synchronization and base station group information discovered by the mobile station in the second step cell search. A three-step cell search process is performed to finally search for the base station to which the mobile station belongs with the signal. In particular, in the three-step cell search process, each of the scrambling codes of each of the eight base stations in the base station group must be searched. In addition, in the case of the multipath search, the eight shifted phases of the scrambling code found in the three-stage cell search must be considered in order to consider eight multipath components. Meanwhile, in the UMTS communication system, a Tx Diversity technique is used to overcome fading, and the Tx Diversity technique uses two or more transmit / receive antennas. That is, the transmit diversity is a technique for receiving a signal transmitted through the remaining transmit antenna when the signal transmitted through one transmit antenna decreases in signal size due to fading. Therefore, in the case of the mobile station, when the transmission diversity is applied in the base station, the search must be performed in consideration of the transmission diversity.

The present invention proposes an integrated synchronization acquisition device of a UMTS system capable of supporting both the three-step cell search and the multipath search, and the integrated synchronization acquisition device structure proposed by the present invention will be described with reference to FIG.

Referring to FIG. 4, the integrated synchronization acquisition device includes a plurality of correlation banks, that is, a first correlation bank 400 and a second correlation bank 450, and an input controller 440. And a transmit diversity controller (445). Here, the reason why the integrated synchronization acquisition apparatus has two correlation banks of the first correlation bank 400 and the second correlation bank 450 is that the transmitter, that is, the base station applies a transmission diversity scheme using two transmission antennas. This is because it is assumed. For example, assuming that the base station applies a transmit diversity scheme using four transmit antennas, the integrated synchronization acquisition apparatus is configured to have four correlation banks. In contrast, the base station uses the transmit diversity scheme. If not applied, the integrated synchronization acquisition device may be configured to have only one correlation bank, but may have multiple correlation banks for fast search time. For convenience of description, the operation of FIG. 4 will be described by using a 1-1 correlator in the first correlation bank 400 and a 2-1 correlator in the second correlation bank 450 as an example. Let's do it.

First, the structure of the 1-1 correlator will be described.

First, an analog channel type I channel signal and a Q channel signal received from a base station are input to an analog to digital converter (ADC) (not shown), and the analog type / digital converter is the analog type. After the digital conversion of the I channel signal and the Q channel signal of the descrambler (de-scrambler) 411 and the descrambler 421, respectively. Here, the digitally converted I channel signal and Q channel signal will be referred to as an ADC_I signal and an ADC_Q signal, respectively. The descrambler 411 descrambles the ADC_I signal with the same scrambling code output from the input controller 440 and outputs the descrambler 412 to an offset compensator 412. Here, the scrambling code generation operation of the input controller 440 is different depending on whether the integrated synchronization acquisition device performs a three-step cell search or a multipath search, and the integrated synchronization acquisition device performs a three-step cell search. The interpretation of the correlation energies output from each of the first correlation bank 400 and the second correlation bank 450 is different depending on whether to perform the multipath search or the multipath search. Operation of the input controller 440 and the first correlation bank according to an operation mode of the integrated synchronization acquisition device, that is, whether the integrated synchronization acquisition device operates in a three-step cell search mode or a multipath search mode. An analysis of the correlation energies output from each of the 400 and the second correlation banks 450 will be described with reference to FIG. 5 below, and thus a detailed description thereof will be omitted. The offset compensator 412 receives the I channel signal output from the descrambler 411, removes the offset component shifted toward the negative (−) side, and outputs the offset component to the gain multiplier 413. The gain multiplier 413 receives the signal output from the offset compensator 412 and multiplies the gain G in order to adjust the number of data bits generated by the correlation energy according to the change in the synchronous cumulative and asynchronous cumulative times. Output to sync accumulator 414. The sync accumulator 414 performs the sync accumulator on the signal output from the gain multiplier 413 and outputs the result to the squarer 415 during a period in which the influence of the frequency offset is minimized. Here, the synchronous accumulation period is loaded through a register of the CPU. The squarer 415 receives the synchronous accumulated I channel data output from the accumulator 414, performs a square operation, and outputs the squared operation to the summer 430.

Next, the descrambler 421 descrambles the ADC_Q signal with the same scrambling code output from the input controller 440 and outputs the descrambler 422 to the offset compensator 422. The offset compensator 422 receives the Q channel signal output from the descrambler 421, removes the offset component shifted toward the negative (−) side, and outputs the offset component to the gain multiplier 423. The gain multiplier 423 receives the signal output from the offset compensator 422 and multiplies the gain G in order to adjust the number of data bits generated by the correlation energy according to the change of the synchronous cumulative and asynchronous cumulative times. Output to sync accumulator 424. The synchronous accumulator 424 performs synchronous accumulation and outputs the signal output from the gain multiplier 423 to the squarer 425 during a period in which the influence of the frequency offset is minimized. Here, the synchronous accumulation period is loaded through a register of the CPU. The squarer 425 receives the synchronous accumulated Q channel data output from the accumulator 424, performs a square operation, and outputs the squared operation to the summer 430.

The summer 430 sums the synchronous accumulated I channel data and the Q channel data output from each of the squarer 415 and the squarer 425 and outputs them to the asynchronous accumulator 431. The asynchronous accumulator 431 accumulates the value output from the summer 430 by the asynchronous cumulative number of times and outputs the first-first correlation energy. Here, the asynchronous accumulation section of the asynchronous accumulator 431 is loaded through the register of the CPU. Here, the correlation energy having the maximum value in the 1-1 correlation energy and its index are offset from the scrambling code applied by the base station, and the interpretation differs depending on which mode the integrated synchronization acquisition device operates. . Since this will be described with reference to FIG. 5 below, detailed description thereof will be omitted.

In this way, each of the eight correlators of the 1-1 correlators to the 1-8 correlators of the first correlation bank 400 detects correlation energy, and considering the detected correlation energies, the first correlation bank. A correlation energy of 400 is detected.

Second, the structure of the 2-1 correlator will be described.

The operations of the descrambler 461, the offset compensator 462, the gain multiplier 463, the synchronization accumulator 464, and the squarer 465 in the 2-1 correlator structure are the first-first. The descrambler 411, the offset compensator 412, the gain multiplier 413, the synchronous accumulator 414, and the squarer 415 described in the correlator structure perform the same operation. In the 2-1 correlator structure, operations of the descrambler 471, the offset compensator 472, the gain multiplier 473, the synchronous accumulator 474, and the squarer 475 are performed in the 1-1 correlator structure. The descrambler 421, the offset compensator 422, the gain multiplier 423, the synchronous accumulator 424, and the squarer 425 described above are performed. 480 and the asynchronous accumulator 481 are the same as those of the summer 430 and the asynchronous accumulator 431 described in the 1-1 correlator structure. The name will be omitted.

However, the scrambling code provided to the descrambler 461 and the descrambler 471 in the 2-1 correlator structure is transferred to the descrambler 411 and the descrambler 421 of the 1-1 correlator structure. It differs from the provided scrambling code for the following reasons. The scrambling code output from the input controller 440 is input to the transmit diversity controller 445, and the transmit diversity controller 445 uses the antenna modulation pattern used to apply transmit diversity in the base station to the scrambling code. After multiplying (antenna modulation pattern), the descrambler 461 and the descrambler 471 are output. Since the base station transmits the same signal through transmit diversity through the first antenna and the second antenna, the signal transmitted through the second antenna is different from the signal transmitted through the first antenna in order to distinguish the antenna. The modulation pattern, i.e., the second antenna modulation pattern, is multiplied. Therefore, since the second antenna modulation pattern must be taken into account, the transmit diversity controller 445 multiplies the scrambling code output from the input controller 440 by the antenna modulation pattern, and then descrambler 461 and descrambler. The output is 471.

In this way, each of the eight correlators of the second-first correlator to the second-eight correlator of the second correlation bank 450 detects correlation energy, and considering the detected correlation energies, the second correlation bank. A correlation energy of 450 is detected. Since the correlation energy detected by the first correlation bank 400 and the correlation energy detected by the second correlation bank 450 are added later and input to a peak detector (not shown), 8 The correlation energy for the two scrambling codes can be calculated at the same time.

Next, an internal structure of the input controller 440 will be described with reference to FIG. 5.

FIG. 5 is a diagram schematically illustrating an internal structure of the input controller 440 of FIG. 4.

Referring to FIG. 5, the input controller 440 includes an orthogonal variable spreading factor (OVSF) code generator 500 and a plurality of scrambling code generators, that is, the orthogonal variable spreading factor (OVSF). First scrambling code generator 521 to eighth scrambling code generator 535 and eleventh scrambling code generator 537 to eighteenth scrambling code generator 551, and a plurality of selectors 501 to 515 ), 531, 537, and 561 to 575, and multipliers 533 and 535 and register arrays I01 to I16 and Q01 to Q16. As described with reference to FIG. 4, the scrambling code generation operation of the input controller 440 is different depending on whether the integrated synchronization acquisition device performs a three-step cell search operation or a multipath search operation. As follows.

First, an operation of the input controller 440 when the integrated synchronization acquisition device performs a three-step cell search operation will be described.

First, as shown in FIG. 5, the search mode signal srch_mode is provided to the selectors 501 to 515 and 561 to 575. Here, the search mode signal srch_mode is a signal indicating whether a search operation currently performed by the integrated synchronization acquisition device is a three-stage cell search or a multipath search, and when the integrated synchronization acquisition device performs a three-stage cell search, The search mode signal srch_mode value is set to "0". Alternatively, when the integrated synchronization acquisition apparatus performs a multipath search, the search mode signal srch_mode value is set to "1". The three-stage cell search is an initial cell search, and the scrambling codes of each of the eight base stations in the base station group found in the two-stage cell search must be simultaneously searched. Meanwhile, scrambling codes generated in each of the first scrambling code generator 521 to eighth scrambling code generator 535 and scrambling codes generated in each of the eleventh scrambling code generators 537 to 18th scrambling code generator 551 are generated. The scrambling codes may be the same or may be different. If the base station has applied transmit diversity, only the first scrambling code generator 521 to the eighth scrambling code generator 535 are operated to directly input eight scrambling codes to the first correlation bank 400. In the correlation bank 450, a code obtained by multiplying the eight scrambling codes by an antenna pattern according to transmission diversity is input. Meanwhile, when simultaneously searching for two base station groups A and B to which transmit diversity is not applied as a part of neighbor cell search, the first scrambling code generator 521 to eighth scrambling code generator 535 may be configured to be searched. The first scrambling code generator 537 to the eighteenth scrambling code generator 551 are input to the first correlation bank 400 to be used to search for the base station group A. The eleventh scrambling code generator 537 to the eighteenth scrambling code generator 551 are input to the second correlation bank 450 to search for the base station code A. It is used to

Finally, the scrambling codes generated in each of the first scrambling code generator 521 to the eighth scrambling code generator 535 are descramblers of 1-1 correlators to 1-8 correlators of the first correlation bank 400. Scrambling codes generated in the first scrambling code generator 521 to the eighth scrambling code generator 535, and each of the eleventh scrambling code generators 537 to 18 th scrambling code generator 551. The scrambling codes that occur should be output to the transmit diversity controller 445. That is, the first scrambling code generated by the first scrambling code generator 521 is output to the selector 531 and the multiplier 533. Here, the multiplier 533 is referred to as a second common pilot channel (S-CPICH, hereinafter, "S-CPICH"), not a P-CPICH signal, especially when the integrated synchronization acquisition device performs a multipath search. When performing a multi-path search using a signal, an OVSF code applied to the S-CPIH, that is, an OVSF code output from the OVSF code generator 500 and a code generated by the first scrambling code generator 521 are used. Multiply and print. However, since the integrated synchronization acquisition apparatus performs a three-step cell search, the selector 531 selects the signal output from the first scrambling code generator 531 as it is and scrambling code sc_i01 of the 1-1 correlator. Here, the scrambling code sc_i01 indicates a scrambling code to be descrambled to the ADC_I signal of the 1-1 correlator, and likewise, the selector 537 receives the scrambling code generated by the first scrambling code generator 521. The scrambling code sc_q01 represents a scrambling code to be descrambled to the ADC_Q signal of the 1-1 correlator, and is output as the scrambling code sc_q01 of the 1-1 correlator. 507 is output from the second scrambling code generator 523 to the eighth scrambling code generator 535. A signal is selected as it is and output to the scrambling codes sc_i02 to sc_i08 of the 1-2 correlators to the 1-8 correlators, wherein the scrambling codes sc_i02 to sc_i08 correspond to the 1-2 correlators to 1-8 correlators. The scrambling code to be descrambled to the ADC_I signal is represented, and the selectors 561 to 567 select a signal output from the second scrambling code generator 523 to the eighth scrambling code generator 535 as it is. The scrambling codes sc_q02 to sc_q08 of 1-2 correlators to 1-8 correlators are output, where the scrambling codes sc_q02 to sc_q08 are scrambling to be descrambled to the ADC_Q signals of the 1-2 correlators to 1-8 correlators. In this way, the eleventh scrambling code generators 537 to 18 th scrambling code generator 551 generate sc_i11 to sc_i18 and sc_qi11 to sc_i18. The scrambling codes output from the input controller 440 are output to the transmit diversity controller 445, and the transmit diversity controller 445 outputs the scrambling codes output from the input controller 440. The scrambling codes are selected and output according to the corresponding search operation, and the detailed operation of the transmit diversity controller 445 will be described with reference to FIG. 6.

Secondly, an operation of the input controller 440 when the integrated synchronization acquisition device performs a multipath search operation will be described.

As described above, when the integrated synchronization acquisition apparatus performs a multipath search operation, the search mode signal srch_mode is set to 1. Since the multipath search considers 8 multipath components based on the scrambling code timing of the base station obtained in the three-step cell search of the initial cell search, eight shifted phases of the obtained scrambling code of the base station are obtained. The search for the fields is performed. It is assumed that the first scrambling code generator 521 generates the scrambling code obtained in the third step cell search among the scrambling code generators of the input controller 440. The first scrambling code generator 521 then generates a scrambling code and outputs the scrambling code to the selector 531 and the multiplier 533. Since it is assumed that the S-CPICH signal is not used in the multipath search, the selection signal OVSF_ON indicating whether the S-CPICH signal is used is set to "0", so that the selector 531 is configured to use the first scrambling code. The scrambling code output from the generator 521 is output as it is. The scrambling code output from the first scrambling code generator 521 is sequentially output from the register I01. Here, the register strings I01 to I16 are phase shifted scrambling codes according to a shift operation for searching for up to 16 hypotheses when the transmit diversity is not applied every 1/2 chip as described above. As a result, the scrambling code stored in the register I16 is a code generated 16 hypotheses, that is, 8 chips before the code input to the register I01 from the first scrambling code generator 521. In addition, since the integrated synchronization acquisition apparatus performs a multipath search, the selectors 501 to 518 respectively output scrambling codes stored in the registers I01 to I16. Here, the scrambling codes output from the selectors 501 to 518, that is, sc_i02 to sc_i18 are used for descrambling the ADC_I signal, and as described above, sc_i01 to sc_i08 are used for the first correlation bank 400. , Sc_i01 to sc_i18 are output to the transmit diversity controller 445. Similarly, the selector 537 selects the scrambling code output from the first scrambling code generator 521 and outputs the same to the registers Q01 to Q16, and the selectors 561 to 575 respectively select the registers. Output the scrambling codes of the Q01 to Q16. Here, the scrambling codes output from the selectors 561 to 575, that is, sc_q02 to sc_q18 are used for descrambling the ADC_Q signal, and as described above, sc_q01 to sc_q18 are transmit diversity controllers 445. Will be printed).

Next, an internal structure of the transmit diversity controller 445 will be described with reference to FIG. 6.

6 is a diagram schematically illustrating an internal structure of the transmit diversity controller 445 of FIG. 4.

As illustrated in FIG. 6, the transmit diversity controller 445 includes a scrambling code selection controller 600 and a second antenna modulation pattern generator 650. The scrambling code selection controller 600 selects eight scrambling codes to be provided to the second correlation bank 450 among the 16 scrambling codes output from the input controller 440. Since a detailed description thereof will be omitted herein. The second antenna modulation pattern generator 650 generates a modulation pattern applied to the second antenna when transmission diversity is applied with two transmission antennas at the base station.

Next, the operation of the scrambling code selection controller 600 will be described below.

First, when the transmit diversity is applied in the base station, the transmit diversity select signal td_mode has a value of "1", and when the transmit diversity is not applied, the transmit diversity select signal td_mode has a value of "0". First, a case in which the base station applies transmit diversity will be described. The scrambling codes output from the input controller 440 are selected according to the operation of the scrambling code selection controller 600. Since the base station has applied transmission diversity, it is assumed that the scrambling codes output from the input controller 440 are output. sc_i01 to sc_i08 are respectively multiplied by the second antenna modulation pattern generated by the second antenna modulation pattern generator 650 in the multipliers 625 to 611 and then output to the selectors 626 to selector 612, respectively. . Since the transmit diversity select signal td_mode has a value of “1”, the selector 626 to the selector 612 select a signal output from the multiplier 625 to the multiplier 611 to select the second correlation bank 450. Output as a scrambling code to be used for descrambling the ADC_I signal. Similarly, sc_q01 to sc_q08 output from the input controller 440 are respectively multiplied by the second antenna modulation pattern generated by the second antenna modulation pattern generator 650 in the multipliers 665 to 651, respectively, and then each selector. 666 to selector 652 are output. Since the transmit diversity select signal td_mode has a value of "1", the selector 666 to the selector 652 select a signal output from the multipliers 665 to the multiplier 651 to select the second correlation bank 450. Outputs the scrambling code to be used for descrambling the ADC_Q signal.

Second, when the base station does not apply transmit diversity, the selector 626 to the selector 612 selects and outputs sc_i11 to sc_i18 output from the input controller 440, and selects and outputs the selector 666 to the selector. 652 selects and outputs sc_q11 to sc_q18 output from the input controller 440. In this case, sc_i11 through sc_i18 and sc_q11 through sc_q18 refer to eight scrambling codes belonging to the base station group. Refers to eight scrambling codes shifted by 1/2 chip in code timing.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

As described above, the present invention has the advantage that a three-step cell search and a multipath search can be performed in a mobile communication system in a UMTS system. In addition, there is an advantage to provide an integrated synchronization acquisition apparatus that can minimize the three-step cell search and multi-path search in hardware.

1 is a diagram illustrating a correlator structure inside a synchronization acquisition device of a general CDMA mobile communication system.

2 is a diagram illustrating an internal structure of a three-stage cell search apparatus of a general UMTS system.

3 is a diagram illustrating an internal structure of a multipath navigation apparatus of a general UMTS system.

4 is a diagram illustrating an internal structure of an integrated synchronization acquisition device of a UMTS system according to an embodiment of the present invention.

5 schematically illustrates an internal structure of the input controller 440 of FIG. 4.

FIG. 6 schematically illustrates the internal structure of the transmit diversity controller 445 of FIG. 4.

Claims (11)

In a next-generation asynchronous mobile communication system in which a base station transmits a reference channel signal by applying transmit diversity with a first transmitting antenna and a second transmitting antenna, an apparatus for receiving synchronization by receiving the reference channel signal, A first correlation bank for correlating a reference channel signal transmitted through the first transmitting antenna with scrambling codes generated at an input controller; A second correlation bank for correlating a reference channel signal transmitted through the second transmit antenna with scrambling codes generated in a transmit diversity controller; When the synchronization acquisition device performs a three-step cell search operation, scrambling codes of the base stations in the base station group to which the base station belongs are generated. When the synchronization acquisition device performs a multi-path search, the three-step cell search is performed. The input controller for generating scrambling codes that phase shift one scrambling code; And the transmission diversity controller which inputs the scrambling codes generated by the input controller and multiplies the modulation pattern applied to the second transmission antenna to the second correlator. The method of claim 1, The transmit diversity controller comprises: a scrambling code selection controller configured to select specific scrambling codes according to whether the base station applies transmit diversity among scrambling codes generated from the input controller; And a modulation pattern generator for generating the modulation pattern. The method of claim 1. Each of the first correlation bank and the second correlation bank is composed of a plurality of correlators, and the input controller outputs the generated scrambling codes to the correlators of the first correlation bank and the second correlation bank, respectively. The integrated synchronization acquisition device. The method of claim 1, And the reference channel is a first common pilot channel. The method of claim 1, And the reference channel is a second common pilot channel. The method of claim 5, And the input controller multiplies the scrambling codes by an orthogonal variable spreading coefficient code applied to the second common pilot channel, and outputs the multiplied multiplication code. In a next generation asynchronous mobile communication system in which a base station transmits a reference channel signal by applying transmit diversity with a first transmitting antenna and a second transmitting antenna, a control method of an apparatus for receiving synchronization by receiving the reference channel signal. , When the synchronization acquisition device performs a three-step cell search operation, scrambling codes of the base stations in the base station group to which the base station belongs are generated. When the synchronization acquisition device performs a multi-path search, the three-step cell search is performed. Generating scrambling codes that phase shift one scrambling code, Correlating the reference channel signal transmitted through the first transmitting antenna with the generated scrambling codes; And correlating the reference channel signal transmitted through the second transmitting antenna with the generated scrambling codes. The method of claim 7, wherein The scrambling codes correlating reference channel signals transmitted through the second transmitting antenna are multiplied by a modulation pattern applied to the second transmitting antenna. The method of claim 7, wherein And the reference channel is a first common pilot channel. The method of claim 7, wherein And the reference channel is a second common pilot channel. The method of claim 8, The scrambling codes correlating reference channel signals transmitted through the first transmitting antenna and the second transmitting antenna are multiplied by an orthogonal variable spreading factor code applied to the second common pilot channel.