KR100481195B1 - Process-and-temperature compensating method and clock generator using the same - Google Patents

Abstract

A method for compensating a process and a temperature and a clock synthesizer using the same are provided to improve a yield and a noise property of an IC using a clock generator by checking current variations according to the process and the temperature, inverting the checked current state, and adding the inverted result to an original current. A VCO(Voltage Controlled Oscillator) is formed with a voltage current converter including a current subtraction bias circuit for checking continuously a current changed according to a process state and a temperature state, and inverting the changed current for compensating a process. A programmable frequency divider is used for dividing clock frequency generated from the VCO by N times. A phase/frequency detector compares phases and frequencies of a divided clock frequency generated from the programmable frequency divider with a reference input frequency to each other. A loop filter performs an operation for lowering a clock output frequency by lowering an input voltage of the VCO if the divided clock frequency is larger than the reference input frequency, or raising the clock output frequency if the divided clock frequency is smaller than the reference input frequency. A charge pump supplies a constant current. A bias generator supplies a necessary current for an analog circuit.

Description

Process-and-temperature compensating method and clock generator using the same

The present invention relates to a process and temperature compensation method and a clock synthesizer using the same. More specifically, the current subtraction bias (CSB) for detecting a specific current and inverting it through a current subtractor to cope with process changes and temperature changes. (Hereinafter referred to as CSB) and a clock synthesizer using the same.

The clock synthesizer is the heart of the IC that makes up the most important clock, and most of them use a phase locked circuit (PLL) structure. This is a high frequency clock internally by using a clock signal having a low frequency outside the IC, thereby reducing the problem of high-speed signal is driven outside the IC, and can create an internal clock of various frequencies There is this.

A general clock synthesizer uses a PLL structure as shown in FIG. The PLL includes a programmable N divider 100, a phase / frequency detector (PFD) 101 that compares the phase and frequency of two inputs, and a charge pump (CP) that supplies a constant current. a charge filter (102) and a loop filter (LF) for determining the band and gain of the PLL, and a voltage controlled oscillator (VCO) that changes its oscillation frequency in accordance with voltage. 104) and a bias generator 105 for supplying the current required for the analog circuit.

The operation of a typical clock synthesizer is as follows. In the VCO, the clock output frequency (F _CKO ) is _divided by the divided clock frequency (F _DIV = F _CKO / N) in the divider that generates the clock output itself and divides the frequency by N times. The divided clock frequency is compared at the reference input frequency (F _REF ) and the PFD.If the divided clock frequency is the larger of the compared frequencies, the charge pump and loop filter lower the input voltage of the VCO to lower the clock output frequency. The feedback of the PLL operates in the direction of increasing. As a result, the PLL uses feedback to match the frequencies of the two input signals of the PFD, the reference input and the divided clock, which are shown in Equation 1.

F _REF = F _DIV = F _CKO / N

Equation 1 is summarized as Equation 2 with respect to the clock output frequency.

F _CKO = NF _REF

Therefore, the clock output frequency of the clock synthesizer is in a form proportional to N, which is the division ratio of the programmable divider, and can be synthesized by an integer number (N) times the reference input frequency.

At this time, the range of the clock output frequency is limited within the frequency range of the VCO. Because the VCO is inside the IC, the clock output frequency varies greatly with changes in supply voltage, process, and temperature, so compensation is necessary to ensure a stable frequency range. In general, supply voltage variations can be compensated for by using voltage regulators or replica biases, but cannot compensate for changes in process and temperature. As a result, the design of a typical VCO includes an area that is ± 50% wider than the target frequency area [Larsson. P.; 'A 2-1600 MHz CMOS clock recovery PLL with low-Vdd capability', IEEE J. Solid-State Circuits, 1999, 34, (12), pp. 1951-1960]. However, such a wide frequency range is a factor that degrades the noise performance of the clock synthesizer, and has a large disadvantage because it does not reduce the frequency change over process and temperature at all. Therefore, there is a need for a structure that stabilizes the frequency by lowering the frequency sensitivity of the VCO temperature and process.

2 is a structural diagram of a conventional voltage controlled oscillator. The VCO is largely a voltage-to-current converter (VIC) 200 for linearly converting a voltage into a current, and a current controlled oscillator (CCO) for changing a frequency according to a current. 201). In addition, the CCO is composed of delay cells 203 cascaded to the N-stage with the radiation bias 202.

The VCO is a circuit that converts the input voltage (V _in ) to the output frequency. In the VIC, the input voltage is changed to the current (I _BIAS ) and the current is applied to the CCO to change the output frequency. CCO is composed of delay elements using radiation bias, a structure that is less affected by power and process changes.

3 is a structural diagram of a conventional current controlled oscillator. It is composed of radiation bias 300 and N-stage delay elements 301 which are less affected by power and process variations. Differential delay elements improve noise performance for the supply, and feedback via radiation bias keeps the delay swing's output swing width constant regardless of the supply voltage, reducing frequency variations over the supply voltage. The delay element may change its delay time t _d using the bias current I _BIAS 302, and by connecting it in a ring shape, the delay time or frequency of the entire CCO may be changed.

The current flowing to M ₁ and M ₂ changes according to the input voltages of M ₁ and M ₂ of the delay element. When the maximum gate voltage be hung on M _1, all of the bias current is caused to flow through the M ₁ wherein the first node 303. The voltage is to have a minimum value. The copy bias is copied as it is.

The radiation bias consists of an op amp 304 and a delayed delay element 305 for bias feedback. If M ₅ is equal to M ₁ and M ₂ in the copied delay elements, the operating point at the maximum output swing of the delay elements is copied. At this time, the voltage of the + terminal 306 of the operational amplifier is equal to the voltage (VDD-V _sw ) of the-terminal by the virtual ground. In the PMOS M _R of the radiation bias, the resistance value R = V _SW / I _BIAS is determined by the bias current at the bottom and the voltage of the second node 306. As a result, the PMOS M ₃ and M ₄ of the delay element also have the same resistance as M _R because the gate voltage is fed back by the radiation bias.

In conclusion, since the delay time t _d of the delay element is determined by the resistance value and capacitance seen in the first node 303, it is represented by Equation 3 below.

t _d = RC / 2 = V _sw C _L / (2 I _BIAS )

Where V _sw is the output swing fixed voltage of the radiation bias, C _L is the capacitance seen at the output stage 303, and I _BIAS is the bias current flowing through the delay element. Therefore, since the delay element using the radiation bias has no influence on the power supply voltage primarily and only the influence by the bias current I _BIAS is large, the performance against the process change and the temperature change of the bias current is increased. It is the biggest factor in determining performance.

4A is a detailed view of the VIC 200 of FIG. 2, which is a general VIC generating the bias current 302 of the delay device of FIG. 3. The VIC consists of a linear voltage current block 401 that converts the input voltage V _in linearly into a current and a minimum current generation block 402 that produces a minimum bias current. The minimum current generation block is added to compensate for the absence of the output current (I _VIC ) of the linear voltage current block below the threshold voltage (V _th ) of M1, and is generally fixed current (FB) or less. A fixed bias I _FB through which _FB flows) is used. The output current I _{OUT, FB} of this circuit is the sum of the current I _VIC generated in the linear voltage current block and the fixed current I _FB generated in the minimum current generation block. This is shown in Figure 4 (b) and each current equation is shown in equations (4) and (5).

I _VIC = (V _in -V _th ) / R

I _{OUT, FB} = I _VIC + I _FB = (V _in -V _th ) / R + I _FB

Where V _in is the input voltage of the voltage current converter and V _th is the threshold voltage of M ₁ . Accordingly, it can be seen that the portion of the fixed output currents I _{OUT and FB} of Equation 5 most affected by the process and temperature changes is the threshold voltage of the transistor.

4 (C) is a simulation result of the voltage current converter output current according to the temperature and the process change, it can be seen that the current error occurs by each process and the temperature parameter value. The fast transistor process change is referred to herein as FF (FastFast, FF), the normal transistor process change is TT (TypicalTypical, TT), and the slow transistor process change is referred to as SS (SlowSlow, hereinafter SS). Low temperature of -40 ℃ is LT (Low Temperature), 25 ℃ room temperature is RT (Room Temerature, RT), and 120 ℃ high temperature is HT (High Temperature, HT) Indicates.

Consequently, when used as a general change in the threshold voltage of the transistor of the step and the temperature in the VIC is output as the current (I _{OUT, FB)} appear, and the bias current (I _BIAS) of the delay element of Figure 3 the output current in step and The delay time of the delay element is changed according to temperature, and thus, the delay time or the frequency change of the voltage controlled oscillator of FIG.

Prior art US Pat. No. 58,476,16 is a voltage controlled oscillator that compensates for changes in manufacturing process, power supply, and process temperature using reference voltage generators and comparators. There was a disadvantage.

In addition, the voltage controlled oscillator having the efficient process compensation function of the prior art Korean Patent Application Publication No. 10-1995-7002969 uses a current detector that detects the current between the drain and the source by keeping a second current source but similar in concept of current subtraction bias. To compensate for the range of process, temperature and supply voltage. However, the prior art includes a multi-stage ring oscillator, which has a disadvantage in that the circuit is complicated and the first current source and the second current source must be separated.

Accordingly, the present invention is to solve the above-mentioned disadvantages and problems of the prior art, by providing a CSB concept as a compensation scheme of analog circuits sensitive to temperature changes, improving the yield, performance of the analog circuit and the process and temperature of the VCO. SUMMARY OF THE INVENTION An object of the present invention is to provide a process and a temperature compensating method for reducing a frequency change with respect to a change and a clock synthesizer using the same.

The above object of the present invention is a voltage composed of a voltage current converter (VIC) applying a current subtraction bias (CSB) circuit used for process compensation by continuously checking the current that changes according to the process and temperature conditions and inverting the change current at this time. Controlled oscillator (VCO); A programmable divider for dividing the clock frequency generated by the voltage controlled oscillator N times; A phase / frequency detector for comparing the phase and frequency of the divided clock frequency generated from the programmable divider with a reference input frequency; A loop filter for lowering the clock output frequency by lowering the input voltage of the voltage controlled oscillator if the frequency of the divided clock frequency among the frequencies compared by the phase / frequency detector is large; A charge pump for supplying a constant current; And a bias generator for supplying a current required for the analog circuit, and a temperature compensating method and a clock synthesizer using the same.

In the CSB according to the present invention, the CSB concept is applied to a clock synthesizer, which is one of the core blocks of many ICs.

The clock synthesizer includes an analog circuit such as a voltage controlled oscillator (VCO). Analog circuits are more sensitive to temperature and process variations than digital circuits, making analog circuits an important factor in determining overall IC yield.

Therefore, applying CSB to VCO, an analog circuit sensitive to process and temperature changes, can reduce the influence of frequency variation due to process and temperature changes. Due to the strong frequency response to process and temperature variations, the VCO with CSB is easy to design because of its low frequency error range and improves noise performance because the design frequency range is reduced. In addition, the yield of analog circuits that are most sensitive to process and temperature changes improves the yield and performance of the entire IC, not just the clock synthesizer.

In addition, the CSB circuit of the present invention is well suited not only for a clock synthesizer but also for circuits for process and temperature compensation, such as high-speed I / O, bias circuits, and delay locked circuits (DLLs).

Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

5 is a conceptual diagram of a current subtraction bias (CSB) that compensates for process and temperature variations. The current that changes according to temperature and process conditions is continuously checked and the current changed at this time is inverted and used for process compensation. For example, it can be used for compensation by checking the influence of the process and temperature of a general transistor and inverting it. FIG. 5A is a characteristic of the temperature and process change of the current I _d flowing under a constant gate-source voltage and drain-source voltage in a typical NMOS transistor. The current I _d flows more at a process temperature of FF and at a lower temperature, and conversely, at a process temperature of SS and at a higher temperature. In order to obtain an inverted characteristic constant current source of Fig. 5 (a) current characteristics, as opposed to processing conditions and temperature as shown in (I _C), 5 (b) also by subtracting the detected current (I _d) in (I _CSB = I _C -I _d ). This current is a component of the process and temperature changes that can be used to compensate for the process and temperature.

6 illustrates an example of a circuit implementing the CSB concept of FIG. 5. The CSB circuit includes a constant current source I _C 602 for supplying a constant current, a current detector or sensor 601 for generating a detection current I _d , and a constant current source I. A current subtractor 600 performing subtraction of the detection current I _d at _C. The CSB circuit detects the current I _d to be compensated by the current detector, compares it with the current I _C of the constant current source, and compensates the current in the form of outputting the difference. When the current detector is composed of transistors under a constant gate-source voltage and drain-source voltage as shown in FIG. 5A to generate a detection current I _d , the compensation current I _CSB of the current subtraction bias is shown in FIG. 5B. Inverted current characteristics such as

FIG. 7 applies the inventive CSB to the voltage current converter 200 of FIG. 2. The VIC using the CSB consists of a CSB bias 700, a linear voltage current conversion block 701, and a current adder 706 that sums the two currents. The current detector of the CSB of the invention detects the current using the same structure (M ₁ = M _d and the same resistance) as the VIC 702. M ₁ and M _d and resistors can be placed as close as possible for current matching to minimize the difference between the two transistor threshold voltages and resistance values.

Linear voltage current conversion block is basically a circuit that changes the current linearly with the input voltage, but independently the current also changes with the process and temperature. By separating these two currents, leaving the components that change with voltage as they are, and removing the currents due to process and temperature changes, process and temperature compensation is possible. When the constant voltage source V _c 704 is connected to the detection transistor M _d instead of the input voltage V _in , only components whose current changes according to temperature and process conditions are detected.

The constant voltage source may use a bandgap reference voltage having a very good variation in supply voltage, process variation, and temperature, or may be externally supplied with an independent power supply. The current detecting the temperature and the process change is added to the voltage-current conversion current (I _VIC ) in an inverted form in the current summer 706, thereby reducing the current change with respect to the process and temperature.

8 is a structural diagram of a constant current source using a constant voltage source. That is, the constant current source 705 of FIG. 7 is shown. The constant current source consists of a voltage-to-current conversion block 800 for converting a voltage into a current and a current mirror block 804 using the changed current to make a constant current source of a specific current value. The voltage current conversion block consists of an operational amplifier 801, a resistor 803, and a transistor 802 for feedback. The operation of the voltage current conversion block is as follows. Using the virtual ground (virtual ground) characteristics of the operational amplifier feedback + terminal 805 voltage - is set to a terminal voltage of V _C. At this time, the current flowing through the resistor 803 becomes V _C / R and is independent of process changes, power supply voltages, and temperature changes. A 1: K times current mirror 804 was used to make the constant current generated in the voltage current conversion block 800 into a current source of a desired value. The constant current source 705 of FIG. 7 sets the ratio of the current mirror to 1: 2 to make the current I _C of the desired constant current source 2V _C / R.

Therefore, I _{CSB, which} is a compensation current of the temperature and the process of FIG. 7, is represented by Equation 6 below.

I _CSB = I _c -I _d = (2V _c / R)-((V _c -V _{th, Md} ) / R) = ((V _c + V _{th, Md} ) / R)

Where V _{th, Md} is the threshold voltage of M _d .

Since M ₁ and M _d are arranged as close as possible to have matching characteristics, the threshold voltages of the two transistors are the same (V _{th, M1} = V _{th, Md} ). Therefore, the current subtractive bias currents I _{OUT and CSB} are expressed as shown in Equation (7).

I _{OUT, CSB} = I _VIC -I _CSB = (V _in -V _{th, M1} / R) + ((V _c + V _{th, Md} ) / R) ≒ ((V _in + V _c ) / R)

Comparing I _{OUT, CSB} of Equation 7 and I _{OUT, FS} current of Equation 5 _, the component proportional to the voltage (V _in / R) is the same as Equation 5, but the threshold voltage which is an item that changes in process and temperature It can be seen that the item (V _th ) has been removed to compensate for the temperature and the process. Thus, Equation 7 shows that the current subtraction bias of the present invention can effectively reduce the effects on the process and temperature of the VIC.

9 shows a VCO connecting the invention CSB and CCO. The same CCO 903 was used to compare the existing FB 900 and the CSB 901 of the present invention, and the FB and CSB were selected through a multiplexer (MUX; Mulitiplexer) 902. When selecting the conventional FB and the invented CSB, the frequency of each voltage controlled oscillator can be compared to verify the characteristics of the process and temperature compensation circuits.

Since the operating frequency of the VCO is the inverse of the time to round the loop according to the delay time (t _d ) of each stage when there are N delay elements, Equation (8).

f _VCO = 1 / 2t _d N

The frequencies f _{VCO and FB of} a VCO connected to the existing FB VIC 900 (FB VCO; fixed-biased VCO, hereinafter referred to as FB VCO) may be obtained by using Equations 3, 5, and 8.

f _{VCO, FB} = 1 / 2t _d N ≒ (V _in -V _th + I _FB R) / V _SW RC _L N

Equation 9 shows that the existing FB VCO is a function of a large threshold voltage (V _th ) with respect to process and temperature.

The frequencies f _{VCO and CSB of the VCOs} connected to the CSB VIC 901 (CSB VCOs, hereinafter referred to as CSB VCOs) connected to the invented CSB VIC 901 may be obtained using Equations 3, 7, and 8.

f _{VCO, CSB} = 1 / 2t _d N ≒ (V _in + V _C ) / V _SW RC _L N

Comparing Equation 9 and Equation 10, the frequency of the FB VCO is linearly influenced by the threshold voltage of the transistor, but the invention CSB VCO frequency has no threshold voltage component of the transistor and is affected by the constant voltage source. As a result, it can be seen that the influence on the process and temperature is reduced.

In another important aspect, the frequency of CSB VCO eliminated the threshold voltage change factor as a result of Equation 10, but the influence of temperature change is still influenced by the temperature coefficient (TC) of each element. Remains. The largest temperature coefficient of these factors is the change (+ TC) that increases with the temperature of the resistor. To compensate for this, a constant voltage source, V _c , is designed to have the same TC as the resistance using a proportional-to-absolute-temperature (PTAT) circuit proportional to temperature. Therefore, the constant voltage source V _C to compensate for the frequency variation of the temperature of the VCO CSB By adjusting the temperature coefficient, more effective compensation is possible.

Figure 10 (a) is a result of the temperature and process changes as the output frequency characteristics of the voltage of the FB VCO. In an FB VCO, the frequency difference is nearly doubled between SS (HT) and FF (LT) in the process (temperature) change. Thus, the frequency range that satisfies process and temperature variations is very narrow. On the other hand, the output frequency characteristic of the CSB VCO shown in FIG. 10 (b) is wider in the usable frequency range as the frequency change is reduced through process and temperature compensation, and as a result, the noise and yield of the VCO are improved, and the design is easy. Do.

11 shows the results of measuring the frequency of the voltage controlled oscillator with 98 samples on a fixed input voltage (V _in ). When measuring the frequency variation between chips, the CSB VCO of the present invention was up to 58.5 MHz while the conventional FB VCO was 91.8 MHz, indicating a 36% improvement in the frequency change range or frequency stability for the process. This improvement is achieved through the detection and removal of threshold voltages.

12 is a VCO frequency characteristics according to the temperature change measured from -20 ℃ to 100 ℃. The measured temperature coefficient is +0.058 MHz / ° C in the invented CSB VCO while it is -0.244 MHz / ° C in the conventional FB VCO, indicating a 76% improvement. The compensation effect on temperature is due to the removal of the threshold voltage as well as the compensation of the temperature change of the resistor with a deliberately used PTAT constant voltage source.

Figure 13 shows a block diagram of applying a VCO using the invention CSB to the clock synthesizer. All the blocks of FIG. 1 are used as they are, and only VCOs can be replaced. Since the size and power consumption of the CSB are very small, application is easy and portability is good. It also makes the VCO area and VCO gain small, which improves the noise characteristics of the clock synthesizer and increases the yield.

In addition, the current subtractive bias can be implemented in a very small area and power with less than 50 transistors used, and the replacement and portability of the existing bias is very good.

Fig. 14 is an output waveform when the voltage controlled oscillator using the current subtracting bias is applied to an 800 MHz clock synthesizer to fix the phase. Jitter measurements at 800 MHz phase lock show low noise performance with 7ps rms jitter and 56ps peak-peak jitter.

15 is a block diagram of a DLL using a delay line. The DLL is fundamentally similar to the PLL, but unlike the PLL, it does not make a ring oscillator using a delay element, but instead, phase-locks by changing the delay time of the reference signal. The DLL includes a programmable N divider 1500 that can be added as needed, a phase / frequency detector (PFD) 1501 that compares the phase and frequency of the two inputs, and a charge pump (CP) 1502 that supplies a constant current. And loop filter 1503 for determining a DLL band, a voltage controlled delay line (VCDL) for changing a delay time according to a voltage (hereinafter referred to as a VCDL) 1504, and a bias for supplying a current required for an analog circuit. Generator 1505. Except for each VCDL, the component is the same as the PLL.

16 is a detailed view of the VCDL of a DLL. The VCDL is composed of a voltage current converter (VIC) 1600 for converting a voltage into a current and a current controlled delay line (CCDL) 1601. The CCDL is composed of a delay element 1602. Unlike the CCO (201 of FIG. 2) of the PLL, the CCDL is not connected in a ring shape, and the input and output are connected in a line without being circulated. If the voltage current converter 1600 is the same as (200) of FIG. 2, and the delay element 1602 is the same as (203) of FIG. 2, the compensation for the temperature and the process of the delay time of the delay element is the CSB of the PLL. The same reward as

Therefore, the CSB can be equally compensated for process and temperature changes in the DLL, and can be applied to analog circuits such as high-speed I / O.

The clock synthesizer using the process and temperature compensation circuit of the present invention has an advantage that it is easy to design and does not need to increase the gain of the voltage-controlled oscillator more than necessary because the frequency change range for process and temperature change is not wide. Noise is reduced. The current subtractive bias has the advantage that it can be implemented in very small area and power with less than 50 transistors used, and it is very good to replace the existing bias and portability.

In addition, the current subtractive bias of the present invention can be used as a bias of circuits (high-speed I / O circuits, analog circuits) that vary in process and temperature as well as voltage controlled oscillators, and circuits for detecting process changes. It can be used as an analogue circuit, and the inverted characteristic of the transistor current with respect to the process and temperature is continuously detected by the analog circuit, thereby making it possible to continuously compensate for environmental changes such as temperature changes.

Although the present invention has been shown and described with reference to the preferred embodiments as described above, it is not limited to the above embodiments and those skilled in the art without departing from the spirit of the present invention. Various changes and modifications will be possible.

The process and temperature compensation method of the present invention and the clock synthesizer using the same can continuously check the current change state with respect to the process and temperature, the current subtraction bias added to the original current by inverting the checked current state and the clock synthesizer using the same Compensation for process and temperature can be achieved, and the yield and noise characteristics of the entire IC using a clock generator can be improved.It can be implemented with very small area and power, and it is possible to replace and bias the conventional bias. There is an effect to be improved.

1 is a block diagram of a conventional clock synthesizer

2 is a structural diagram of a conventional voltage controlled oscillator

3 is a structural diagram of a conventional current controlled oscillator

4 is a structural diagram of a conventional voltage current converter and simulation results for the voltage current converter output current according to temperature and process changes.

5 is a conceptual diagram of a current subtraction bias (CSB) that compensates for process and temperature variations of the present invention.

6 is an embodiment of a circuit implementing the CSB concept.

7 illustrates an embodiment in which the CSB of the present invention is applied to a voltage current converter.

8 is a structural diagram of a constant current source using a constant voltage source

9 is a structural diagram showing a VCO connecting the CSB and CCO of the present invention

10 is a result of temperature and process changes as an output frequency characteristic of a voltage of an FB VCO.

11 is a result of measuring the frequency of the voltage controlled oscillator on a fixed input voltage (V _in )

12 is a frequency characteristic of the VCO with temperature changes

13 is a block diagram of applying a VCO using a CSB of the present invention to a clock synthesizer.

14 is an output waveform when the present invention is applied to an 800 MHz clock synthesizer and the phase fixed thereto.

15 is a block diagram of a DLL using a delay line.

16 is a detail view of the VCDL of the DLL.

<Description of the symbols for the main parts of the drawings>

     104. Voltage controlled oscillator 200. Voltage current transducer

     600. Current subtractor 601. Current detector (sensor)

     602. Constant Current Source 903. Current Controlled Oscillator

Claims (13)

A voltage controlled oscillator (VCO) consisting of a voltage current converter (VIC) to which a current subtractive bias (CSB) circuit is used to continuously check a current that changes according to a process and a temperature, and reverse the change current at this time and use it for process compensation; A programmable divider for dividing the clock frequency generated by the voltage controlled oscillator N times; A phase / frequency detector for comparing the phase and frequency of the divided clock frequency generated from the programmable divider with a reference input frequency; A loop filter for lowering the clock output frequency by lowering the input voltage of the voltage controlled oscillator if the frequency of the divided clock frequency among the frequencies compared by the phase / frequency detector is large; A charge pump for supplying a constant current; And Bias Generator Supplying Current Required for Analog Circuits Clock synthesizer using the process and temperature compensation method characterized in that it comprises a. The method of claim 1, The current subtraction bias (CSB) circuit Constant current source using a constant voltage source for supplying a constant current; A current detector or sensor for generating a detection current according to temperature and process changes; And Current subtractor for subtracting the detected current from a constant current source Clock synthesizer using the process and temperature compensation method characterized in that it comprises a. The method of claim 1, The voltage-to-current converter (VIC) Current subtraction bias (CSB) circuits; A linear voltage-current conversion block for converting a voltage into a current; And A current adder for summing the current of the current subtraction bias (CSB) and the current of the linear voltage current bias; Clock synthesizer using the process and temperature compensation method characterized in that it comprises a. The method of claim 3, wherein The current subtraction bias (CSB) circuit and the linear voltage-to-current conversion block are arranged close to each other so that the transistors have a matching characteristic to equalize the threshold voltages of the two transistors, clock synthesizer using a process and temperature compensation method . The method of claim 3, wherein The current subtraction bias (CSB) circuit is a detection transistor structure in which a constant voltage source is connected to detect only a component whose current changes according to a process and a temperature while leaving a change due to a voltage as it is. Clock synthesizer. The method of claim 5, The constant voltage source is a clock synthesizer using a process and temperature compensation method, characterized in that the constant voltage source connected to a bandgap reference or an external independent power source having excellent fluctuation characteristics for power supply voltage, process change and temperature. The method of claim 3, wherein And the current subtraction bias (CSB) circuit uses the same structure of the linear voltage-to-current conversion block, the same transistor and the same resistor. The method of claim 7, wherein The linear voltage-current conversion block Current mirrors; transistor; And resistance Clock synthesizer using the process and temperature compensation method, characterized in that configured to include. The method of claim 2, The constant current source is A voltage-current conversion block for converting a voltage into a current; And A current mirror block that makes a constant current source of a specific current value by using the current converted by the voltage-current conversion block. Clock synthesizer using the process and temperature compensation method, characterized in that configured to include. The method of claim 1, The voltage controlled oscillator (VCO) is a clock synthesizer using a process and temperature compensation method, characterized in that for adjusting the temperature coefficient of the constant voltage source using a PTAT circuit proportional to the temperature in order to compensate for the temperature change according to the temperature of the resistance. The method of claim 1, The current subtraction bias (CSB) circuit is a clock synthesizer using a process and temperature compensation method, characterized in that for performing a compensation function for the process and temperature changes of the DLL using the delay line. A current subtraction bias (CSB) step of continuously checking the current that changes according to the process and temperature conditions and inverting the change current at this time to use for process compensation; A voltage controlled oscillator step of applying a current subtraction bias step to generate a clock output; A frequency division step of dividing the clock frequency generated from the voltage controlled oscillator step by N times; A phase / frequency detection step of comparing a phase and a frequency of the divided clock frequency generated from the frequency division step with a reference input frequency; A loop filter step of lowering the clock output frequency by lowering the input voltage in the voltage controlled oscillation step and increasing the clock output frequency when the frequency is small in the voltage controlled oscillation step if the frequency of the divided clock frequency is large among the frequencies compared in the phase / frequency detection step; A charge pump step of supplying a constant current; And Bias Generation Step to Supply Current for Analog Circuit Clock synthesis method using a process and temperature compensation method characterized in that comprises a. The method of claim 12, The current subtraction bias (CSB) step may include: a current detection step of continuously checking and detecting a current that changes according to a process and a temperature situation; A current subtraction step of inverting the detected current in a constant current source supplying a constant current; And Using the current of the inverted characteristic obtained through the current subtraction step for process and temperature compensation Clock synthesis method using a process and temperature compensation method characterized in that comprises a.