KR100480915B1 - The method and Apparatus for controlling page write and read mode in memory device - Google Patents

Abstract

The present invention relates to a method for controlling a page write / read mode of a memory device, and an apparatus thereof, to maintain an output enable signal high when a page is written in a page write mode, to toggle a write enable signal to control column access, When the normal address is changed in the page read mode, the column address is disabled before the word line by using the address transition detection signal to prevent the column enable and the row disable from overlapping each other.

Description

The method and apparatus for controlling page write / read mode of a memory device {1 and method for controlling page write and read mode in memory device}

The present invention relates to a method and apparatus for controlling page mode read / write of a memory device, and more particularly, to provide a page write and read control and a column control method and a circuit thereof to control a page read and write mode of a memory device. A page mode read / write control method of a memory device and an apparatus thereof are provided.

In the field of memory, devices used in mobile devices are becoming more and more large, and are also increasing in speed to process large amounts of data. The present invention relates to the page mode proposed as a method of improving the speed of such devices and can be widely used in the field of using memory devices.

The chip select signal (/ CS: Chip_select), which is recently developed for mobile use, is an input signal for selecting a chip from the outside. If / CS = 'high', the chip select signal is selected. Toggling the Able signal / WE causes a timing problem, which limits the speed. As shown in FIG. 1, since the write enable signal / WE changes from high to low, a predetermined time (tWHZ; Write to Output in High-Z) should pass. This limits the timing and thus provides a factor in the inability to control the write speed as much.

In addition, when the column is opened at the page read timing, the voltage level to be restored to the cell becomes low when the word line is disabled, thereby causing a problem in which a refresh fail occurs.

As a method of implementing page write, there is a method by toggling the write enable signal at the time of writing, which is a method of using the toggle of the write enable signal as the column access signal.

However, as shown in FIG. 1, the timing problem occurs as the light enable signal is toggled, thereby limiting the speed.

Compared to the normal mode address (Address (normal)), the page mode address (Address (page)) is changed from the address n, n + 1, n + 2, n + 3, ... by the toggle of the write enable signal / WE. It is divided into., And data writing is performed according to the page mode address. However, in FIG. 1, the polling time T1 is 2.5ns, tWHZ (T2) is 10ns, and tDW (T3) is 10ns. Under the conditions shown in FIG. 1, the time tDW for writing actual data is 10ns. This is not possible, because page mode writes are not possible.

 As shown in FIG. 1, after the write enable signal / WE is changed from "high" to "low", a predetermined time tWHZ must pass for data to enter the data input buffer. This limits the timing and thus provides a factor that prevents you from controlling the write speed as much.

Accordingly, an object of the present invention is to provide a method for controlling a page write / lead of a memory device in which a data output speed is increased when a write enable signal is toggled in a page lay mode in order to solve the problems of the related art. .

Another object of the present invention is to provide a method of controlling a page write / read mode of a memory device which eliminates the occurrence of refresh fail in the page read mode by using an address transition detection signal.

The page mode write control method of the memory device of the present invention for achieving the above object is characterized in that to maintain the output enable signal high in the page write mode, and to toggle the write enable signal to control column access.

A page write / read control apparatus of a memory device of the present invention for achieving the above object comprises a first pulse generator for generating a first pulse signal for controlling generation of an address strobe signal by a write signal:

A read detection signal is generated by the write signal and the sense amplifier enable signal, and a second pulse signal is generated by the page mode address transition detection signal, and the reset signal and the read detection signal and the read signal inputted with the write signal are generated. An address strobe signal controller for generating a first latch signal for controlling generation of said address strobe signal in response to a two-pulse signal;

The reset signal is generated in response to a delay of the chip select signal, the sense amplifier enable signal, and the internal second latch signal, and in response to the reset signal, the first latch signal, and the first pulse signal. An address strobe signal generator for generating a second latch signal as an address strobe signal; And

The write / lead enable signal when the address strobe signal, the normal mode address transition detection signal, the word line clear signal, the write signal, and the sense amplifier enable signal are input, and an address is changed or a write enable signal is enabled. When the normal address is changed during the page read operation, the column address is disabled before the word line, and the write / lead strobe signal is enabled when the address strobe signal is enabled and the sense amplifier enable signal is enabled. It characterized in that it comprises a light / lead control unit for enabling the.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram illustrating a page write / read control apparatus of a memory device according to an exemplary embodiment of the present invention. As illustrated, the generation of the address strobe signal Add_stb by the write signal web is illustrated. A read detection signal is generated by the first pulse generator 100 generating the first pulse signal for the first pulse signal, the write signal web and the sense amplifier enable signal SG, and the page mode address transition detection signal ADT ( A second pulse signal, and in response to the first reset signal, the read detection signal Read_det, and the second pulse signal provided from the write signal web and the first reset unit 310, respectively. An address strobe signal controller 200 for generating a first latch signal for controlling generation of the address strobe signal Add_stb, a chip select signal / CS, a sense amplifier enable signal SG, and a second latch unit A second latch signal which is an output signal of 330 is predetermined. The first reset signal is generated in response to the time delayed signal, and the second latch signal is generated in response to the first reset signal, the first latch signal, and the first pulse signal, and the address strobe signal ( The address strobe signal generator 300 generated by Add_stb, the address strobe signal Add_stb, the normal mode address transition detection signal ATD (Nomal), the word line clear signal wlcb, the write signal web, and the sense When the amplifier enable signal SG is input, the address is changed or the write enable (/ WE) is enabled, the write / read strobe signal Wtrd_stb is reset and the word is changed when the normal address is changed during the page read operation. The write / lead strobe signal Wt when the column address is disabled before the line, and the address strobe signal Add_stb is enabled and the sense amplifier enable signal SG is enabled. It consists of a light read control unit 400 to enable rd_stb).

FIG. 3 is a detailed configuration diagram of the address strobe signal controller 200 according to an exemplary embodiment of the present invention. As shown in FIG. 3, the write signal web and the sense amplifier enable signal SG detect whether the read mode is in the read mode. A read detection unit 210 for generating a read detection signal Read_det, a second pulse generation unit 220 for generating a second pulse signal according to the page mode address transition detection signal ADT (Page), and write A first latch signal for controlling generation of the address strobe signal Add_stb in response to the reset signal, the read detection signal Read_det, and the second pulse signal provided by the signal web and the first delay unit 320. It consists of a first latch unit 230 for generating a.

The output signal of the read detector 210 is input to the data input buffer 600 and disables the data input buffer 600 in the page write mode.

The address strobe signal Add_stb is stored in the page address buffer 500.

The first latch unit 230 includes a first NAND gate ND1 for logically combining the read detection signal Read_det and the write signal web, an output signal of the first NAND gate ND1, and the second pulse signal. Is coupled to the first NOR gate NOR1 and the power supply voltage terminal VCC and the first node Nd1 and is driven by the reset signal of the address strobe signal generator 300. A first NMOS transistor NM1 and a first NMOS transistor NM1 coupled to one end of the transistor PM1 and the first node Nd1 and driven by the reset signal of the address strobe signal generator 300. The second NMOS transistor NM2 coupled between the other end and ground and driven by the output of the first NOR gate NOR1 and the first node N1 to generate an address strobe signal Add_stb. The first latch 230a generates a first latch signal for controlling.

The first latch 230a receives a signal output through the first node N1 and inverts and outputs the first inverter INV1 and a second inverter INV2 having a feedback configuration with the first inverter INV1. It is composed of

FIG. 4 is a detailed block diagram of the write / read control unit 400 according to an exemplary embodiment of the present invention. As shown in FIG. 4, the third pulse generator generates a third pulse signal in response to the sense and enable signal SG. 410, a controller 420 for generating a control signal for controlling generation of the write / lead strobe signal Add_stb in response to the sense and enable signal SG and the address strobe signal Add_stb, and a write signal. the fourth pulse generator 430 for generating the fourth pulse signal in the write mode by the web, the normal mode address transition detection signal ADT (normal), the word line clear signal wlcb, and the controller 420. The write / read strobe signal generator 440 generates a write / read strobe signal Wtrd_stb in response to a control signal and the third pulse signal.

FIG. 5 is a detailed block diagram of the write / read strobe signal generator 440 according to an exemplary embodiment of the present invention. As shown in FIG. 5, a normal mode address detection signal ADT and a word line clear signal wlcb are shown. A second reset unit 444 for generating a second reset signal in response to a delay signal provided by the fourth pulse signal and the second delay unit 442, and the second reset signal and the controller 420; And a third latch portion 446 for generating a latch value in response to the control signal of the < RTI ID = 0.0 >) < / RTI > and the third pulse signal as the write / lead strobe signal Wtrd_stb, The second delay unit 442 outputs the delayed signal by delaying the latch signal by a predetermined time.

The second reset unit 444 may include a normal mode address transition detection signal ADT (normal) and a word line clear signal wlcb, and a second NAND gate ND2 for logically combining the fourth pulse signal. A second NOR gate NOR2 logically combines the delay signal of the second delay unit 442 and the output signal of the second NAND gate ND2.

The third latch unit 446 is coupled between an AND gate AND for logically combining the control signal of the controller 420 and the third pulse signal, and is connected between the power supply voltage terminal VCC and the second node N2. A second PMOS transistor PM2 driven by the output signal of the second NOR gate NOR2 and a first end coupled to the second node N2 and driven by the output signal of the second NOR gate NOR2. The fourth NMOS transistor NM3, the fourth NMOS transistor NM4 coupled between the other end of the third NMOS transistor NM3 and ground and driven by an output signal of the AND gate AND a second node The third latch 446a outputs the second latch signal as the write / read straw portion signal Wtrd_stb after latching the output signal of N2.

The third latch 446a receives a signal output through the second node N2 and inverts and outputs a third inverter INV3 and a fourth inverter INV4 having a feedback configuration with the third inverter INV3. It is composed of

6 is a timing of a page read mode in a page read / write of a memory device according to the present invention, FIG. 7 is a timing diagram of a page write mode of a memory device according to the present invention, and FIG. 8 is a timing diagram of a memory device according to the present invention. A timing diagram of the page read mode.

In the embodiment of the present invention, as shown in Fig. 6, in the write mode, the output enable signal (/ OE; Output Enable Bar) is kept " high " and the write enable signal / WE is toggled to access the column. When the control is performed, the data can be input simultaneously with the write enable signal / WE, thereby improving the write speed.

Referring to FIG. 6, in the embodiment of the present invention, the polling and rising edge times T1 and T3 are 5 ns, the tDW (T3) is 15 ns, and the time to write the actual data is 15 ns. The light becomes possible. In order to enable page writing in this manner, the output enable signal (/ OE) should be made high at the time of writing.

When the word line is disabled at the page read timing, when the column line is opened, the voltage level restored to the cell is lowered, which causes a problem of a refresh error. This problem can be solved by disabling the column line first when the previous word line is disabled by using an address transition detection signal (ATD) generated due to an address change.

In FIG. 7 and FIG. 8, the chip select signal / CS is an input signal for selecting a chip from the outside, and if / CS = 'high', the chip is selected; if / CS = 'low', the chip is selected and the address normal ( address normal; add_n is an address input signal input to externally select a memory cell, and when the address normal (add_n) is changed, it is the start of the page mode. Is the beginning. The write enable signal (/ WE: Write Enable Bar) is a signal that distinguishes between the read operation and the write operation from the outside. When the write enable signal / WE is a logic level 'high', the write enable bar is a read enable signal. If (/ WE) is logic level 'low', it is in write mode. The output enable signal (/ OE: Out Enable Bar) is an external input signal that controls the data output during read operation. When the output enable signal (/ OE) is logic level 'high', the output is enabled and the output is enabled. If the enable signal / OE is logic level 'low', the output is disabled. The page mode address transition detection signal (ATD (Page) Transition Detector) is an internal timing signal that generates a pulse when the page address transitions. The word line driving signal W / L is an internal control signal for selecting a memory cell. The word line clear bar (wlcb) is an internal signal for deselecting the selected word line and selects a word line if high, and clears a word line if low. The sans amplifier enable signal (sg: generator) is an internal signal for enabling the bit line sense amplifier.

The read detection signal (Read_det: Read Detection) is a signal that detects whether the current state is read and becomes high when it is read.

In addition, tRC (Read Cycle Time) is a minimum time required to perform a read operation, tWC (Write Cycle Time) is a minimum time required to perform a write operation, and tPRC (Page Read Cycle Time) is a page read operation. The minimum time required, page write cycle time (tPWC) is the minimum time required to perform a page write operation, and the tWHZ (Write to Output in High-Z) indicates that the write enable signal (/ WE) is low to high. The minimum time it takes for data to enter the data input buffer after the change to (Low).

According to an exemplary embodiment of the present invention, a strobe operation for receiving an address is generated by a normal mode address transition detection signal at a timing of opening a page, and the strobe operation is delayed so that the sense amplifier enable signal SG is delayed. Generates a word line access signal, which is a ROW access signal, and operates only by changing the page address after the column access signal and the write / read operation are performed. It is called motion.

The operation of the page write and read modes will now be described with reference to the timing diagrams of FIGS. 7 and 8.

The first pulse generator 100 generates a first pulse signal having a logic level 'high' in response to the write signal web generated at the rising timing of the write enable signal / WE, and thus, the first latch unit 330. To provide. Then, the first latch unit 330 of the address strobe signal generation unit 300 generates a second latch signal in response to the first pulse signal, and the first reset unit through the first delay unit 320. Feedback to 310.

In the address strobe signal controller 200, the read detector 210 receives the read signal web and the sense amplifier enable signal SG to generate a read detection signal Read_det, which is a read detection signal Read_det. ) Is generated by delaying the change of the write enable signal / WE from the logic level 'low' to 'high', that is, the 'high' portion of the write enable signal / WE is constant. If the width is not larger than the width, the read detection signal Read_det does not occur.

When the read detection signal Read_det is not generated as described above, the second latch unit 330 of the address strobe signal generator 300 is provided by the first reset unit 310 as a result of the feedback operation. The signal is reset by the signal to generate an address strobe signal Add_stb having a logic level 'low' level.

If the read detection signal Read_det does not occur, the data input buffer 600 is not disabled by this signal, and the write / read strobe signal Wtrd_stb is generated by the page mode address transition detection signal ADT (page). Also does not occur.

Therefore, in the page write mode, the address strobe signal generated when the write enable signal / WE transitions from the logic level 'high' to 'low' becomes a signal for receiving a valid address.

However, in the page read mode, only the strobe is possible due to the address transition. Therefore, when the write enable signal / WE becomes more than the predetermined width or the output enable signal / OE becomes the logic level 'low', the read detection signal ( Read_det becomes the logic level 'high' to generate the address strobe signal Add_stb by the page mode address transition detection signal ADT (page) and the write / read strobe signal Wtrd_stb.

The address strobe Add_stb signal generated by the address strobe signal generator 300 is written by the write / read controller 400 together with the sense amplifier enable signal SG as shown in FIGS. 7 and 8. Generate the lead strobe signal Wtrd_stb. At this time, the write / read strobe signal Wtrd_stb is generated in response to the falling edge of the address strobe Add_stb signal in the page write mode and in response to the rising edge of the address strobe Add_stb signal in the page read mode.

Meanwhile, as shown in FIG. 8, a column operation for reading data may be performed when the sense amplifier enable signal SG is enabled.

In the write / lead strobe signal generator 440, the second delay unit 442 receives the write / lead strobe signal Wtrd_stb enabled by the sense & enable enable signal SG and the address strobe signal Add_stb. In the case of a write, the signal is generated as a level signal, and in the case of a read, a pulse signal is fed back to the second delay unit 442.

The third pulse generator 410 enables the write / lead strobe signal Wtrd_stb when the sense amplifier enable signal SG is activated, and the fourth pulse generator 430 enables the normal address (normal) during the read operation. When add is changed, the column is disabled before the word line to prevent a failure.

If the sense amplifier enable signal SG is enabled when the address strobe signal Add_stb is enabled, the controller 420 generates a control signal to enable the write / lead strobe signal Wtrd_stb and generates a third latch. Supply to section 441.

As described above, in the present invention, the data enable rate can be improved by keeping the output enable signal high to accelerate the write cycle in the process of toggling the write enable signal during page write to control column access. It has an effect.

In addition, in the present invention, when the normal address is changed during the page read, the column line is disabled before the word line so that the disable of the word line in and the enable timing of the column line do not overlap, thereby eliminating the occurrence of refresh fail in the page read mode. There are other effects that can be done.

In addition, the present invention has another effect of implementing a memory device operating in the page read mode and the page write mode.

1 is a timing diagram illustrating a page write mode of a conventional memory device.

2 is a block diagram for explaining a page write / read control apparatus of a memory device according to the present invention;

3 is a detailed block diagram of the address strobe signal controller of FIG. 3;

4 is a detailed block diagram of the write control signal generator of FIG.

FIG. 5 is a block diagram illustrating the write lead strobe signal generator of FIG. 5. FIG.

6 is a first timing diagram illustrating a page write mode of a memory device according to the present invention.

FIG. 7 is a second timing diagram for describing a page write mode of a memory device according to the present invention. FIG.

8 is a timing diagram for explaining a page read mode of a memory device according to the present invention;

<Explanation of symbols for the main parts of the drawings>

100: first pulse generator 200: address strobe signal controller

210: lead detector 220: second pulse generator

230: second latch unit 300: address strobe signal generation unit

310: first reset part 320: first delay part

400: light / lead controller 410: third pulse generator

420: control unit 430: fourth pulse generator

440: light / lead strobe signal generator

442: second delay unit 444: second reset unit

446: the third latch portion

Claims (12)

delete In the method of controlling the page read mode of a memory device, when the normal address is changed in the page read mode, the column address is disabled before the word line by using the address transition detection signal to prevent the column enable and the row disable from overlapping each other. A method of controlling the page read mode of a memory device. The method of claim 2, And the column access operation by the address transition detection signal is controlled only when the page is read without performing the column access operation by the address transition detection signal during the page write. A first pulse generator for generating a first pulse signal for controlling the generation of the address strobe signal by the write signal: A read detection signal is generated by the write signal and the sense amplifier enable signal, and a second pulse signal is generated by the page mode address transition detection signal, and the reset signal and the read detection signal and the read signal inputted with the write signal are generated. An address strobe signal controller for generating a first latch signal for controlling generation of said address strobe signal in response to a two-pulse signal; The reset signal is generated in response to a delay of the chip select signal, the sense amplifier enable signal, and the internal second latch signal, and in response to the reset signal, the first latch signal, and the first pulse signal. An address strobe signal generator for generating a second latch signal as an address strobe signal; And The write / lead enable signal when the address strobe signal, the normal mode address transition detection signal, the word line clear signal, the write signal, and the sense amplifier enable signal are input, and an address is changed or a write enable signal is enabled. When the normal address is changed during the page read operation, the column address is disabled before the word line, and the write / lead strobe signal is enabled when the address strobe signal is enabled and the sense amplifier enable signal is enabled. And a write / lead control unit for enabling the memory device. The method of claim 4, wherein the address strobe signal controller A read detector for generating a read detection signal for detecting whether the read mode is the read mode and the sense amplifier enable signal, and a second pulse generator for generating a second pulse signal from the page mode address transition detection signal; And a first latch unit configured to generate a first latch signal for controlling generation of the address strobe signal in response to the write signal, the reset signal inputted, the read detection signal, and the second pulse signal. A page write / lead mode control device for a memory device. The method of claim 5, The first latch unit includes: a first NAND gate for logically combining the read detection signal and the write signal; a first NOR gate for logically combining the output signal of the first NAND gate and the second pulse signal; A first PMOS transistor coupled between a first node and driven by a reset signal of the address strobe generator, and a first end coupled to the first node and driven by a reset signal of the address strobe signal generator; A MOS transistor, a second NMOS transistor coupled between the other end of the first NMOS transistor and ground and driven by an output of the first NOR gate, and coupled to the first node to generate the address strobe signal. A page write / restore of a memory device, characterized in that it comprises a first latch for generating a first latch signal for control. Mode control. The method of claim 4, wherein the write / read control unit, A third pulse generator configured to generate a third pulse signal in response to the sense and enable signal, and control to control generation of the write / lead strobe signal in response to the sense and enable signal and the address strobe signal A controller for generating a signal, a fourth pulse generator for generating a fourth pulse signal in a write mode by the write signal, a normal mode address transition detection signal, a word line clear signal, a control signal of the controller, and the third And a write / lead strobe part generator for generating a write / lead strobe signal in response to a pulse signal. The method of claim 7, wherein the write / lead strobe signal generation unit, A second reset unit generating a second reset signal in response to the normal mode address transition detection signal, the word line clear signal, the fourth pulse signal, and a delay signal input; A third latch unit configured to generate a latched third latch signal as a write / lead strobe signal in response to the control signal of the controller and the third pulse signal, and delay the third latch signal by a predetermined time in response to the write signal. And a second delay unit configured to output the delayed signal to the page write / read mode control device of the memory device. The method of claim 8, The second reset unit is configured to logic the normal mode address transition detection signal, the word line clear signal, a second NAND gate that logically combines the fourth pulse signal, the delay signal, and an output signal of the second NAND gate. And a second NOR gate to be combined. The method of claim 8, wherein the third latch portion An AND gate for logically combining the control signal of the control unit and the third pulse signal, a second PMOS transistor coupled between a power supply voltage and a second node and driven by an output signal of the second NOR gate; A third NMOS transistor, one end of which is coupled to a node and driven by an output signal of the second NOR gate, and a second coupled between the other end of the third NMOS transistor and ground, and driven by an output signal of the AND gate. And a third latch for latching the output signal of the second node and outputting a second latch signal as a write / lead straw signal after latching an output signal of the second node. The method of claim 4, wherein And the write / read controller generates a write / lead strobe signal in response to the falling edge of the address strobe signal in the page write mode. The method of claim 4, wherein And the write / read control unit generates a write / lead strobe signal in response to the rising edge of the address strobe signal in the page read mode.