KR100475341B1 - Chip scale package manufacturing method and its structure using wire bonding - Google Patents

Abstract

The present invention relates to a method for manufacturing a chip scale package (CSP) (hereinafter referred to as "CSP") and a structure of a CSP manufactured according to the method, and more particularly to manufacturing a CSP using a substrate. The present invention relates to a CSP manufacturing method and a structure in which a conductive wiring on a substrate and a bonding pad of a semiconductor chip can be electrically connected by using an existing facility. For this purpose, wire bonding is performed by connecting a conductive chip of a semiconductor chip and a substrate. Disclosed is a method of manufacturing a CSP having a simple structure for forming a wire ball using the same, and also discloses a CSP structure manufactured according to the above, and by manufacturing a CSP through such a method, new equipment is required according to a conventional CSP manufacturing method or wafer processing. Disadvantages such as additional equipment required for the process (FAB) can be avoided, and as a result, Simplification can reduce CSP manufacturing costs, improve manufacturing yield, and shorten development time.

Description

Chip scale package manufacturing method using wire bonding and its structure

The present invention relates to a method for manufacturing a chip scale package (CSP) and a structure of a CSP manufactured according to the method, and more particularly, to a conductive wiring and a semiconductor on a substrate when manufacturing a CSP using the substrate. The present invention relates to a CSP manufacturing method and structure using a wire bonding method in order to electrically connect a bonding pad of a chip.

In general, the system tends to be light and thin, and thus, the size of the package to be packaged is also light and short. However, in conventional packages, the above object is difficult to achieve because the size of the package body is relatively larger and thicker than the size of the semiconductor chip. Accordingly, a package that can be assembled within a range that does not significantly deviate from the size of the chip is required as a method according to the above trend, and such a package is called a CSP. CSP has advantages such as smaller size and smaller mounting area than conventional plastic package, but at the same time, new equipment is required during assembly or additional equipment required for wafer fabrication (FAB) fabrication process is required. And many other disadvantages.

Looking at the manufacturing method of the CSP using a conventional flexible (flexible) tape as follows. After forming a metal wiring such as Au on the flexible tape formed of polyimide and copper by using lithography and sheeting technology, between the flexible tape and the semiconductor chip Bonding through an elastomer made of synthetic rubber, connecting the metal ribbons, which are the ends of the metal wires exposed at the ends of the tape, to the bonding pads of the semiconductor chip, and potting the metal ribbons and the joints. Potting) is used to encapsulate with an encapsulation resin (EMC) and then attach solder balls onto the tape. 1 shows a cross-sectional view of a structure of a CSP manufactured through such a manufacturing method. The manufacturing method of the CSP using the flexible tape with reference to the drawings as follows.

The metal wiring 40 is formed on a flexible tape made of polyimide 20 and copper 30 using slab and sheet metal techniques. An end of the metal wire 40 protrudes out of the tape to form a metal ribbon 45 to be electrically connected to the bonding pad 12 later. The flexible tape on which the metal wiring 40 is formed is bonded onto the semiconductor chip 10 with the elastomer 70 interposed therebetween, and the metal ribbons 45 are connected to the corresponding bonding pads 12 to form the semiconductor chip 10 and the metal. The wires 40 are electrically connected. The connection portions of the metal ribbons 45 and the bonding pads 12 exposed to the outside of the flexible tape are encapsulated with the encapsulation resin 80 or the like using a potting method. Bumps 60 are formed on the tape to be connected to the metal wire 45, and the solder balls 50 are attached according to the position of the bump 60 formed on the tape to complete a CSP that can be mounted on an external substrate. .

In addition, look at the CSP manufacturing method using a conventional wafer processing process as follows. The semiconductor chip on the tested wafer has a protective layer formed of an insulating film such as polyimide except for the portion where the bonding pad is formed. Wafer processing such as lithography, etching, thin film, diffusion, etc. is performed on the semiconductor chip to form the metal wiring over the protective layer of the semiconductor chip, and then again on the metal wiring except for a portion to form bumps for mounting the solder balls. A protective layer is formed of an insulating film such as polyimide. After bumps are formed by using lead and tin on a portion of the metal wiring exposed from the protective layer, the wafer is separated into respective semiconductor chips and encapsulated with an encapsulant such as an encapsulating resin in portions except the bumps. Finally, the solder balls are attached to the exposed bumps.

2 is a cross-sectional view of the structure of the CSP manufactured through such a manufacturing method. Referring to the drawings will be described a CSP manufacturing method using a wafer processing process as follows. In the semiconductor chip 110 on the tested wafer, the protective layer 120 is formed except for the region where the bonding pads 112 are formed. The metal wire 130 is formed on the semiconductor chip 110 again through a wafer processing process to form a bump 150 so as to be connected to the bonding pad 112 and the solder ball may be attached to an unconnected end of the metal wire. do. After the bumps 150 are formed, the protective layer 140 is formed on the surface of the semiconductor chip excluding the bumps again using an insulating film, and the surfaces of the semiconductor chips are encapsulated with the encapsulation resin 160 in accordance with the surface on which the bumps 150 are formed. Encapsulate. Finally, solder balls are attached to the bumps to complete the CSP, which can be mounted on an external board.

The conventional method for manufacturing a CSP as described above is difficult to manufacture by the conventional plastic package assembly process (Assembly) process, it is inconvenient to develop a new equipment or to use additional equipment used in the wafer processing process. As a result, a very complicated process and a corresponding cost increase may occur in order to form a material such as a flexible tape, and a disadvantage may arise such as lower efficiency in the efficiency of the wafer processing process. This can lead to higher costs, longer development periods, and lower yields on package assembly.

An object of the present invention is to implement a method for manufacturing a CSP and a structure according to the wire bonding method, which is a conventional plastic package assembly method.

Another object of the present invention is to simplify the manufacturing method of the CSP to reduce the manufacturing cost of the CSP, to improve the production yield, and to shorten the development period.

In order to achieve the above object, the present invention forms a wire ball using a wire bonding method on a bonding pad of a semiconductor chip in the process of manufacturing a CSP using a substrate, thereby conducting conductivity on the bonding pad and the substrate of the semiconductor chip. Provided are a CSP manufacturing method and structure for electrically connecting wiring.

The manufacturing method and structural features of the CSP according to the present invention are as follows.

In the CSP structure of the present invention, a hole corresponding to each bonding pad and a substrate on which conductive wires are formed are bonded on a semiconductor chip on which a plurality of bonding pads are formed, and the other end of the conductive wire is connected to an external substrate such as solder balls. It has a structure in which a terminal can be formed. At this time, a wire bonding method using a wire bonder and a wire is used as a method of electrically connecting the bonding pad of the semiconductor chip and the conductive wiring on the substrate. More specifically, the process of cutting the upper end of the wire ball after forming the wire ball The bonding pads and the conductive wires are connected by completely filling the inside of the hole of the substrate with the wire balls. Therefore, in comparison with the CSP structure according to the conventional method, the present invention has a simple CSP structure by only electrically connecting using a wire ball.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

3 is a flowchart sequentially illustrating a method of manufacturing a CSP according to the first embodiment of the present invention. In the method of manufacturing a CSP according to FIG. 3, the method may include preparing a semiconductor chip having an active surface on which a plurality of bonding pads are formed (220), and preparing a substrate on which a hole and a conductive wiring corresponding to each bonding pad are formed on the upper surface thereof ( 230, adhering the lower surface of the substrate and the active surface of the semiconductor chip (240), electrically connecting the bonding pad of the semiconductor chip and the conductive wiring on the upper surface of the substrate using wire bonding (250) and connecting the conductive wiring Attaching solder balls 260 to the non-end ends.

4A and 4B show a CSP made according to the method of FIG. 3 in cross section and in a general plane of the main part. According to these drawings, the structure of the CSP according to the first embodiment of the present invention will be described. A semiconductor chip 310 having an active surface 314 having a plurality of bonding pads 312 formed thereon, and a substrate having a hole 326 formed corresponding to each bonding pad and an upper surface 322 having conductive wires 328 formed therein. A lower surface 324 of the substrate 320 and an active surface 314 of the semiconductor chip 310 are bonded to each other using an adhesive 344. Each hole 326 is filled with a wire ball 330 to electrically connect the bonding pad 312 of the semiconductor chip 310 and the conductive wiring 328 of the substrate 320, and at the other end of the conductive wiring 328. Solder bump 342 is formed to have a structure attached to the solder ball 340.

5A to 5F show the wire bonding method used in the method of FIG. 3 in cross section around the portion where the wire ball is formed. Referring to these drawings, the wire bonding method used in the present invention will be described. FIG. 5A illustrates a substrate in which a semiconductor chip 310 having an active surface 314 having a bonding pad 312 formed therein, a hole 326 corresponding to the bonding pad 312, and a conductive wiring 328 formed on an upper surface 322. The shape of the 320 and the bottom surface 324 of the substrate 320 and the active surface 314 of the semiconductor chip 310 are bonded to each other using the adhesive 344. 5B to 5E also show that the wire 332 having a predetermined thickness inserted into the wire bonder 350 over the bonding pad 312 forms the wire ball 330, and the wire 322 is connected to an arbitrary disconnection portion 336. After cutting by edge bonding), the process of cutting the upper end of the wire ball 330 again using a cutting tool 360 such as a blade. FIG. 5F illustrates a state in which the wire ball 330 cut at the upper end electrically connects the bonding pad 312 of the semiconductor chip 310 and the conductive wire 328 of the substrate 320.

As shown in FIGS. 5A to 5F, a method of forming a wire ball by using a wire bonding method is to electrically connect the bonding pad of the semiconductor chip and the conductive wiring of the substrate by sufficiently filling the holes. very important. In general, when the size of the bonding pad of the semiconductor chip is set to about 100 μm, the corresponding hole is formed to a diameter of about 150 μm, and the tolerance appearing at this time is about 50 μm, which is a positional tolerance that may occur when bonding the semiconductor chip and the substrate. Is the value of. In addition, it is preferable to use a wire having a diameter of about 50 μm as the wire used to fill the hole having this diameter, which is a rather thick standard than the diameter of the wire used in the existing process. The actual wire ball is formed with a diameter of more than three times the diameter of the wire used, and the diameter of the current wire is used up to about 125 μm, so that there is no restriction in applying the wire bonding method to the present invention.

In addition, when it is difficult to form a wire ball with a thick wire, such as when the thickness of the substrate is thick or the bonding pad is relatively small, an internal connection material is formed on the bonding pad, and then a wire ball is formed on the internal connection material. The method can be applied. In this case, the internal connection material may be formed by forming an internal wire ball using a thin wire as compared to a wire having a predetermined thickness used in the first embodiment, or by forming an internal bump through an additional process in a wafer processing process for manufacturing a semiconductor chip. Can be formed.

6A to 6F illustrate a second embodiment of the present invention, in which an inner wire ball is formed using a wire that goes to an internal connection material, and then a wire ball is formed using a thick wire having a predetermined thickness thereon. It is shown.

FIG. 6A illustrates the semiconductor chip 310 and the substrate 320 as shown in FIG. 5A, and the substrate 320 and the semiconductor chip 310 are bonded using the adhesive 344. 6B-6D also show that the thin wire 372, which is inserted into the small wire bonder 352 over the bonding pads 312, forms the inner wire ball 370 and the subsequent wire 372 at any disconnected portion 376. After cutting by edge bonding, the process of cutting the upper end of the inner wire ball 370 again using a cutting tool 360 such as a blade. FIG. 6E illustrates a view in which an inner wire ball 370 having a cut top is connected to a bonding pad 312 of a semiconductor chip 310 and a conductive wire 328 of a substrate 320. An initial view of a process of forming a wire ball using a thick wire 332 is shown on the inner wire ball 370 formed at 326, indicating that the wire bonding method is repeated.

7A to 7F illustrate a third embodiment of the present invention, in which a wire ball is formed using a thick wire having a predetermined thickness after forming an internal bump using a wafer processing process as an internal connection material. It is shown.

FIG. 7A illustrates a state in which a small inner bump 380 is formed on the bonding pad 312 through an additional process in preparing the semiconductor chip 310, and FIGS. 7B and 7C also show the semiconductor chip 310. FIG. 6 shows a state in which the corresponding hole 326 and the substrate 320 having the conductive wiring 328 are bonded to accommodate the inner bump 380. Lastly, the wire bonding method using the thick wire 332 is applied to the inner bump 380 again in FIG. 7D.

As described above, the CSP manufacturing method according to the present invention is characterized in that it uses a wire bonding method in connecting the conductive wiring on the semiconductor chip and the substrate, the structure is also very simple compared to the conventional CSPs have.

CSP manufacturing method and structure according to the present invention is to electrically connect the bonding pad of the semiconductor chip and the conductive wiring on the substrate using a wire bonding method on the bonding pad of the semiconductor chip in the process of manufacturing the CSP using the substrate, the wire By using the simple structure of the ball, it is possible to prevent inconvenience such as the use of new equipment and the existing wafer processing process according to the conventional method, and consequently, the CSP manufacturing method is simplified, thereby reducing the cost of manufacturing CSP and manufacturing yield. Improve the development and shorten the development period.

1 is a cross-sectional view showing the structure of a CSP using a conventional flexible tape,

2 is a partial cross-sectional view showing a structure of a CSP using a conventional semiconductor device fabrication process (FAB; fabrication);

3 is a flowchart showing a method of manufacturing a CSP according to the first embodiment of the present invention;

4A is a partial cross-sectional view showing the structure of a CSP manufactured according to the method of FIG. 3;

4B is a plan view showing the structure of a CSP manufactured according to the method of FIG. 3;

5a to 5f are cross-sectional views showing the formation of a wire ball in accordance with the method of FIG.

6a to 6f are cross-sectional views showing a state of forming a wire ball according to a second embodiment of the present invention,

7A to 7D are cross-sectional views illustrating the formation of a wire ball according to a third embodiment of the present invention.

<Description of Main Parts of Drawing>

10, 110, 310: semiconductor chip 12, 112, 312: bonding pad

20 polyimide 30 copper

40, 130: metal wiring 45: metal ribbon

50, 340: Solder Ball 60, 150, 342, 380: Bump

70: elastomer 80, 160 encapsulation resin

120, 140: passivation layer 314: active surface

320: substrate 322: upper surface of the substrate

324: bottom surface of substrate 326: hole

328: conductive wiring 330, 370: wire ball

332, 372: wire 336, 376: disconnection part

344: adhesive 350, 352: wire bonder

360: cutting tool

Claims (9)

(a) preparing a semiconductor chip having an active surface on which a plurality of bonding pads are formed; (b) preparing a substrate having upper surfaces each having holes corresponding to the bonding pads and conductive wires having one end connected to the holes; (c) bonding a lower surface of the substrate onto the active surface; (d) electrically connecting one end of each of the bonding pad and the conductive wiring to each other through the hole; And (e) attaching a solder ball to the other end of the conductive wiring; In the chip scale package manufacturing method comprising: Step (d) Forming a wire ball on the bonding pad to sufficiently fill the hole by using a wire and a wire bonder having a predetermined thickness, and electrically connecting the bonding pad and one end of the conductive wire through the wire ball; The method of forming the wire ball of step (d) Forming an internal connection material on the bonding pad according to the size of the hole and then forming the wire ball on the internal connection material; Chip scale package manufacturing method characterized in that. The method of claim 1, wherein the forming of the wire ball of the step (d) (d-1) directly forming an upper end of the wire ball on the bonding pad to maintain a predetermined height above the upper surface of the substrate; And (d-2) cutting the upper end of the wire ball evenly using a cutting tool; Chip scale package manufacturing method comprising a. The method of claim 2, wherein the cutting tool of step (d-2) is a blade. 4. The method of claim 3, wherein the bonding in step (c) uses a nonconductive adhesive, wherein the nonconductive adhesive is applied to the active surface except for the bonding pad. 5. The method of claim 4, wherein the solder balls of step (e) are attached through a solder reflow process. The method of claim 1, wherein the internal connection material is an internal wire ball that can be accommodated in the hole. The method of claim 6, wherein the inner wire ball is formed using a wire thinner than the predetermined thickness. The method of claim 1, wherein the internal connection material is an internal bump that can be received in the hole. The method of claim 8, wherein the internal bumps are formed in the preparing of the semiconductor chip.

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