KR100472769B1 - How to Form Surface-Channel NMOS and PMOS Transistors in CMOS-Compatible Processes - Google Patents

Abstract

Surface-channel NMOS and PMOS transistors are formed in a CMOS compatible process by implanting a substrate to form a source / drain region at the same time a gate is implanted to set the gate conduction shape. Next, the dielectric layer is deposited and baked to densify and reflow the dielectric. The baked dielectric is then etched to expose the top surface of the gate. Next, a metal layer is formed on the top surface of the gate. According to the present invention, the degradation of the metal layer resulting from baking is eliminated by forming the metal layer after the dielectric layer is baked.

Description

How to Form Surface-Channel NMOS and PMOS Transistors in CMOS-Compatible Processes

The present invention relates to methods of forming NMOS and PMOS transistors, and more particularly to methods of forming surface-channel NMOS and PMOS transistors in a CMOS compatible process.

Conventional CMOS fabrication techniques fabricate surface-channel NMOS transistors and buried-channel PMOS transistors, since the deposited silicon layer is subsequently etched to form a gate of both NMOS and PMOS transistors, such as a material such as POCl _3. It is because it is made into N-type using. However, more recently, industry trends have shifted to the use of surface-channel PMOS transistors to achieve lower threshold voltages.

One technique using surface-channel NMOS and PMOS transistors is shown in FIGS. 1A-1D. As shown in FIG. 1A, this technique begins with growing a gate oxide layer 12 on a semiconductor substrate 10 having an N-well and a plurality of field oxide regions (FOX). After the gate oxide layer 12 is formed, the amorphous silicon layer 14 is then deposited.

Next, away from the conventional CMOS stage, photoresist mask 15 is formed and patterned to expose the gate to be formed of the NMOS transistor. Next, the exposed areas are implanted with arsenic or similar material.

After the NMOS gate to be formed is implanted, the NMOS photoresist mask 15 is stripped off and a PMOS photoresist mask (not shown) is formed and patterned to expose the gate to be formed of the PMOS transistor. The exposed area is then implanted with boron or similar material. After this, the PMOS photoresist mask is stripped off.

Next, returning to the conventional step, the tungsten silicide layer 16 used to reduce the resistance of the poly is deposited on the silicon layer 14 as shown in FIG. The photoresist mask 18 is formed. As shown in FIG. 1C, the unmasked region is then etched to form a plurality of gates 20 and a plurality of poly resistors 22.

Next, the mask 18 is stripped off and an N-type implant mask (not shown) is formed to protect the P-channel transistor to be formed. After the implantation mask is formed, the unmasked region is implanted in a small arsenic dose.

Next, the N-type implant mask is stripped off and a P-type implant mask (not shown) is formed to protect the n-channel transistor to be formed. After the implantation mask is formed, the unmasked region is implanted with a low dose of boron. Next, the P-type implant mask is stripped off and the oxide layer (not shown) is deposited. The oxide layer is then anisotropically etched to form spacers 28 as shown in FIG. 1D.

After the spacers 28 are formed, the second N-type injection mask 30 is formed to protect the P-channel transistors to be formed. After the injection mask 30 is formed, the unmasked area is implanted with arsenic. Heat treatment at increased temperature is then performed to activate the arsenic and form an N-type source / drain region.

Next, the second N-type injection mask 30 is stripped off and a second P-type injection mask (not shown) is formed to protect the n-channel transistor to be formed. After the implantation mask is formed, the unmasked region is implanted with boron to form the source / drain regions of the P-channel transistor. Thereafter, the second P-type mask is peeled off.

As shown in FIG. 1E, after the second P-type implant mask is removed, heat treatment at increased temperature is performed to activate boron and form a P-type source / drain region. Dielectric layer 32 containing boron and phosphorus is then deposited on the wafer. The wafer is then heated to 800-900 ° C. for densification and reflow and then polished using conventional chemical-mechanical techniques.

The main drawback of this solution is that two additional masking steps are required beyond many of the steps used for conventional CMOS fabrication processes. In addition, it is difficult to match the etching rates of the N-type and P-type polysilicon. As a result, it is difficult to control critical poly dimensions.

Another technique for fabricating surface-channel NMOS and PMOS transistors is shown in FIGS. 2A-2E. As shown in FIG. 2A, this technique starts from the same steps as the previous technique of growing the gate oxide layer 12 and then depositing the amorphous silicon layer 14.

In contrast to the previous technique, photoresist 18 is then formed on the undoped silicon layer. As shown in FIG. 2B, the unmasked region is then etched to form a plurality of gates 20 and a plurality of poly transistors 22.

This is followed by the same steps as described above for low dose injection, formation of spacers 28, and formation of source / drain regions after the process. However, as shown in FIG. 2C, since the gate is patterned prior to the deposition of tungsten silicide, the doping step of forming the source / drain regions also simultaneously establishes the conductive form of the gate.

After the source / drain regions are implanted, the gate oxide layer 12 formed on the source / drain regions is removed along with a portion of the top surface of the gate 20. This is followed by a titanium layer (not shown). The titanium layer is then annealed at low temperature in N ₂ . The titanium layer in contact with the gate, polyresist, source and drain interacts with silicon to form titanium silicide. The remaining titanium interacts with nitrogen to form titanium nitride.

The titanium nitride is then stripped off selectively so that the titanium silicide cap 34 is formed on the gate, source and drain of the transistor, and on the polyresist, as shown in FIG. 2D. After removing the titanium nitride, the titanium silicide cap 34 is annealed to a high temperature to reduce the resistance of the titanium silicide 34.

Next, as shown in FIG. 2E, a dielectric layer 36 containing boron and phosphorous is deposited on the wafer. The wafer is heated to 700-900 ° C. for magnetization and reflow and then polished using standard chemical-mechanical techniques.

One of the drawbacks associated with this solution is that the heating step required to magnetize and reflow the dielectric degrades the titanium silicide. In addition, there is a micro process window for forming titanium silicide on the source / drain regions.

Thus, there is a need for a technique for forming NMOS and PMOS surface-channel transistors that does not require additional masking steps and does not degrade titanium silicide.

In the present invention, the NMOS and PMOS transistors are formed in a CMOS compatible process by starting from a semiconductor substrate formed with an N-well. Next, a plurality of regularly spaced field oxide regions are formed on the substrate, and then a first oxide layer is formed on the substrate between the field oxide regions. After the first oxide layer is formed, an amorphous silicon layer is formed on the field oxide region and the first oxide layer, which is then etched to form a plurality of gates. Next, a second oxide layer is formed on the field oxide region, the first gate oxide layer, and the plurality of gates. The second oxide layer is then etched back to form spacers along both sides of the gate. Subsequently, a substrate is implanted to form source / drain regions and to set the conductivity of the gates of the NMOS and PMOS transistors. A third oxide layer is then formed over the field oxide region, spacer, gate, source / drain region and poly resist. Next, the wafer is heated to magnetize and reflow the third oxide layer. The third oxide layer is then etched to expose the top surface of the gate. Next, a metal layer is deposited on the third oxide layer, the exposed gate, and the poly resist. The low resistance metal layer is then selectively formed on the gate and the poly resistor to reduce their resistance value.

A better understanding of the features and advantages of the present invention will be realized with reference to the following detailed description and accompanying drawings, which illustrate exemplary embodiments in which the principles of the present invention are used.

3A-3K illustrate cross-sectional views illustrating the steps of forming surface-channel NMOS and PMOS transistors in accordance with the present invention.

The process of the present invention starts from forming an N-well in a P-type semiconductor substrate. As shown in FIG. 3A, an N-well is first formed by growing an oxide layer 110 on the semiconductor substrate 100 to a thickness of approximately 50 kPa. An N-type implant mask 112 is then formed on the oxide layer 110 and patterned to define an N-type implant region. Next, an N-type dopant is injected into the unmasked site to define the N-well 114.

Once the N-well 114 is formed, the N-type implant mask 112 is stripped off and a drive-in step is performed to further define the n-well 114. After the double diffusion step, the oxide layer 110 is removed. The fabrication steps used to form the N-well 114 are conventional and well known in the art. Alternatively, as shown in FIG. 3B, the P-well 118 may be formed in the substrate 116 in the form of an N-type conductivity.

The next step after forming the N-well 114 is to form a plurality of field oxide regions. As shown in FIG. 3C, the field oxide region is first formed by growing a pad oxide layer 122 on the substrate 100 to a thickness of approximately 200 kPa. This is followed by depositing the nitride layer 124 overlying to a thickness of approximately 200 kPa. Next, a field oxide mask 126 is formed on the nitride / pad oxide composite and patterned to define a plurality of regularly spaced field oxide regions (FOX).

Next, the unmasked portion is etched until the underlying nitride layer 124 is removed. As a result of this etching step, a plurality of pad oxide regions are exposed. After the unmasked nitride layer 124 is removed, the field oxide mask is stripped off.

Referring to the 3D diagram, after the pad oxide region is implanted, the resulting device is oxidized to form a field oxide region (FOX). The fabrication steps used to form the field oxide region (FOX) are conventional and well known in the art.

Once the field oxide region (FOX) is formed, the next step is to set the channel limit voltage for the field effect transistor to be formed. The threshold voltage is first set by removing the nitride / pad oxide composite layer. Next, a sacrificial oxide layer (not shown) is grown on the exposed substrate 100. Next, a limit voltage mask is formed and patterned on the sacrificial oxide layer.

After the threshold voltage mask has been formed and patterned, the semiconductor substrate 100 underlying the sacrificial oxide regions unmasked are implanted with boron in 4OKeV forms an injection concentration of approximately 5 × O ^l2 / cm ^2. After this, the limit voltage mask is stripped off and the sacrificial oxide layer is removed. The manufacturing steps used to set the channel limit voltage are also conventional and well known in the art.

After the sacrificial oxide layer is removed, the next step is to form a gate. As shown in FIG. 3E, the gate is first formed by growing a gate oxide layer 130 on the substrate 100 to a thickness of approximately 80-100 GPa. Thereafter, the amorphous silicon layer 132 is deposited on the gate oxide layer 130 and the field oxide region (FOX) at approximately 2000 microns thick. Next, a photoresist mask 134 is formed and patterned on the silicon layer 132.

As shown in FIG. 3F, the unmasked silicon layer 132 is then etched to form a plurality of poly resists 138 along with the plurality of gates 136. Next, the mask 134 is stripped off and an N-type implant mask (not shown) is formed to protect the P-channel transistors to be formed. After the implantation mask is formed, the unmasked region is implanted into the arsenic dose of gate oxide layer 130.

Next, the N-type implant mask is stripped off, and a P-type implant mask (not shown) is formed to protect the n-channel transistor to be formed. After the implantation mask is formed, the unmasked region is implanted at low boron dose through the gate oxide layer 130. Next, the P-type implant mask is stripped off and the oxide layer (not shown) is deposited. The oxide layer is then anisotropically etched to form spacers 150 as shown in FIG. 3G.

After the spacer 150 is formed, the second N-type injection mask 152 is formed to protect the P-channel transistor to be formed. After the injection mask 152 is formed, the unmasked region is implanted with arsenic at 4 OKeV to form an implant concentration of approximately 5 × 10 ¹² / cm ² . This step forms source / drain regions and sets the conductivity type of the gate of the n-channel transistor.

Next, the second N-type injection mask 152 is stripped off, and a second P-type injection mask (not shown) is formed to protect the n-channel transistor. After the implantation mask is formed, the unmasked region is implanted with boron at 4 OKeV to form an implantation concentration of approximately 5 × 10 ¹² / cm ² . This step forms a source / drain region and sets the conductivity type of the gate of the P-channel transistor. Next, the second P-type injection mask is peeled off.

As shown in FIG. 3H, after the second P-type implant mask is removed, the second dielectric layer 156 is deposited. In the present invention, atmospheric or sub-atmosphere TEOS / ozone, BPSG, or other similar materials may be used to form the dielectric 156. Next, the wafer is heated to 700-900 ° C. for magnetization and reflow of dielectric 156. Next, photoresist mask 158 is formed and patterned on dielectric layer 156 to expose gate 136 and poly resist 138. Once the mask 158 is in place, the wafer has a dielectric layer 156 removed from the top surface of the gate 136 and the poly resistor 138.

Next, as shown in FIG. 3I, after the mask 158 is removed, the titanium layer 160 is deposited. The wafer is then annealed at 600-700 ° C. in N ₂ . After annealing the wafer, titanium in contact with the gate and polyresist interacts with the polysilicon to form titanium silicide 162. The remaining titanium interacts with nitrogen to form titanium nitride. The exposed titanium nitride layer is then selectively etched so that the titanium silicide 162 remains intact, as shown in FIG. 3J.

After the titanium nitride layer is removed from the dielectric layer 156, the wafer is annealed at 700-850 ° C. in N ₂ or argon to reduce the resistance of the titanium silicide 162. Next, as shown in FIG. 3K, oxide layer 164 is deposited on the wafer and polished using conventional chemical-mechanical polishing techniques. After oxide layer 164 has been deposited and polished, manufacturing continues using conventional steps.

Thus, according to the present invention, the problem associated with heating the titanium layer to 700-900 ° C. by depositing the titanium layer after the dielectric layer 156 has been magnetized and reflowed is eliminated.

One of the advantages of the present invention is that the titanium silicide is formed in a self aligned manner, i.e. no masking step is required. In addition, cobalt or nickel may also be used instead of titanium to form self-aligned silicides.

Moreover, mask 158 is not necessary if both the poly resistor and gate can be fabricated at the same level using, for example, trench isolation techniques rather than conventional LOCOS isolation techniques.

It should be understood that various modifications to the embodiments of the invention described herein can be used to practice the invention. Accordingly, the appended claims define the scope of the invention and the methods and structures falling within these claims and their equivalents are intended to be included in the invention.

1A through 1E or surface-channel NMOS and PMOS transistors.

Sectional view illustrating a first technique to make.

2A through 2E or surface-channel NMOS and PMOS transistors

Sectional view illustrating a second technique to make.

3A through 3K illustrate a surface-channel NMOS and

A cross-sectional view illustrating the step of forming a PMOS transistor.

Claims (2)

A method of forming surface-channel NMOS and PMOS transistors in a P-type silicon substrate, Forming an N-type well in said P-type silicon substrate; Forming a plurality of field oxide regions on the P-type silicon substrate to define a P-type active element region and an N-type active element region; Forming a gate silicon oxide layer on the P-type active device region and the N-type active device region; Forming an amorphous silicon layer formed on said P-type active element region and said gate silicon oxide layer on said N-type active element region, but also extending on said field oxide region; Patterning the amorphous silicon layer to define a gate electrode on the gate silicon oxide on the P-type and n-type active device regions and to form an amorphous silicon resistor on a selected region of the field oxide region ; Forming silicon oxide sidewall spacers on sidewalls of the amorphous silicon gate electrode on the P-type active device region and the N-type active device region; Forming a photoresist N-type implantation mask on the N-type active device region, but not masking the P-type active device region; Implanting an N-type dopant into the unmasked P-type active element region, thereby adjoining the amorphous silicon gate electrode that defines a P-type channel region in the P-type active element region below the amorphous silicon gate electrode. Forming N-type source and drain regions spaced apart from each other in the P-type active element region; Removing the photoresist N-type implant mask; Forming a photoresist P-type implant mask on the P-type active device region, but not masking the N-type active device region; Implanting a P-type dopant into the unmasked N-type active device region, thereby adjoining the amorphous silicon gate electrode that defines an N-type channel region in the N-type active device region below the amorphous silicon gate electrode. Forming a P-type source and drain region spaced apart from each other in the N-type active element region; Removing the photoresist P-type implant mask; Forming a dielectric material layer over said P-type active device region and said N-type active device region; Heating the dielectric material layer to a temperature of 700-9OO ° C. such that the dielectric material is densified and reflowed; Forming a photoresist mask on the P-type active device region and the N-type active device region; Patterning the photoresist mask to expose the top surface of the silicon gate electrode and the amorphous silicon resist of the P-type active device region and the N-type active device region; Forming a metal layer on the result of the previous step; The metal layer is brought to a temperature of 600-7OO ° C. and an N ₂ atmosphere so that the amorphous silicon gate electrode and the metal layer in contact with the amorphous silicon resist react to form a metal silicide and the rest of the metal layer forms a metal nitride. Annealing at; Selectively removing the metal nitride; Annealing the metal silicide at a temperature of 700-850 ° C. and N ₂ or argon to lower the resistance of the metal silicide; Depositing a layer of dielectric material on the result of the previous step; And And completing the surface-channel NMOS transistor and the surface-channel PMOS transistor while maintaining the temperature of the resultant temperature lower than 7O < 0 > C. 10. The method of claim 1, wherein the metal layer comprises titanium.