KR100470947B1 - Electrically erasable and programmable nonvolatile memory protected against power failure - Google Patents

Abstract

To reduce the risk that error data is written to electrically erased or programmable inactive memory 10 (EEPROM) when a failure occurs in memory 10 power supply Vcc during a programming or erasing operation, memory 10 Means 30 for generating a high voltage Vpp for programming or erasing, and having a high voltage during the time required for programming or erasing operations with cells C _{i, j} and capacitances Chv, CR _{2 of the} memory. Means SW _i and TI _i are provided to maintain a high voltage Vpp supply of sufficient power to maintain Vpp). The present invention is useful for EEPROM memories mounted on chip cards or electronic labels.

Description

Electrically erasable and programmable nonvolatile memory protected against power failure

The present invention relates to EEPROM, ie electrically erasable and programmable nonvolatile memories.

Recently, EEPROM memories have made remarkable advances due to their superior characteristics. In fact, these memories can be programmed and erased as intended by applying a high voltage, commonly referred to as Vpp. Once programmed or deleted, they retain information indefinitely without powering on. Because of these characteristics, EEPROM memories are desirable to store information or processing data in microcircuits mounted in portable devices that do not have their own power supply, such as chip cards or electronic labels that are only electrically supplied when used. Represents the means.

1 schematically shows the structure of a microcircuit 1 of the type described above, equipped with an EEPROM memory 10 having a plurality of memory cells C _{i, j} arranged in rows and columns. The microcircuit allows the generation of the high voltage Vpp needed for erase or programming operations of memory 10 from the supply voltage Vcc of logic circuit 20 (with wired logic or microprocessor) and about 3V to 5V of microcircuit 1. It further comprises a chain 30 of elements. The chain 30 generating the high voltage Vpp is, for example, a booster in series with a charge pump 32 driven by a clock signal H provided by an oscillator 31, a stabilizing capacitance Chv, a voltage regulator 33 and a shaping circuit 34 of voltage Vpp in series. It has a (booster) circuit.

When the erase or programming operation is performed, logic circuit 20 provides an activation signal ACTVPP to oscillator 31 and charge pump 32 supplies a high voltage Vhv of about 22V to 25V at voltage Vcc. The voltage Vhv is provided at the input of the regulator 33 which generates a stabilizing capacitance Chv and a voltage Vpp of about 15V to 20V. The shaping circuit 34, the last of the chain 30, gradually provides the voltage Vpp to the memory cells C _{i, j} in the form of a ramp shown in FIG.

In memory 10, cells C _{i, j} are selected by row decoder DWL and column decoder DBL which receive addresses ADRWL and addresses ADRBL, respectively, provided in logic circuit 20. To program cells C _{i, j} (set to "0") or delete (set to "1"), the high voltage Vpp is driven by the first switch group SWWL and column decoder DBL driven by the low decoder DWL. The second switch group SWBL is transferred to cell C _{i, j} . The voltage Vpp is also controlled by logic circuit 20 and is applied to other internal nodes of memory 10 by an operation selection circuit COM that allows programming or erasing operation selection. Is provided.

In order to cause the programming or erase operation to occur correctly, the high voltage Vpp needs to be maintained for some time, about 4 ms to 5 ms, required to transfer charge to the cells C _{i, j} . However, a problem in using EEPROM memories in chip circuits or electronic circuits of electronic labels is a user's mistake of operation (e.g. abrupt removal of a chip card from a reader with a chip card inserted) or especially (chip card). The poor energy transfer when the voltage Vcc is transmitted by electromagnetic induction can cause the power supply voltage Vcc, which generates a high voltage Vpp, to be cut off momentarily. If a failure of the supply voltage Vcc occurs for a few ms required by the write operation by accident or by intentional attempt, the data in the process of being stored carries the risk of not being stored or erroneously stored. This problem is particularly embarrassing if the stored data represents monetary figures.

In the state of the art, this problem is a microcircuit that does not have a spontaneous power supply, as it is a process of supply voltage failure that occurs in setting logic circuit 20 of microcircuit 1 to zero without considering memory. It is considered a inherent drawback in using EEPROM memories within. However, French Patent No. 2 703 501 provides for adding an auxiliary cell to each row of the EEPROM memory to prevent writing wrong data during a failure of the supply voltage. However, this solution is essentially about a unit that is calculated by abbreviating it to a method called a "counting frame" and does not solve the general problem mentioned above.

Accordingly, it is an object of the present invention to protect EEPROM memories from the risk of writing error data in the event of an improper failure of the supply voltage.

In connection with these features, advantages and the accompanying drawings in conjunction with others of the present invention, embodiments and methods of the EEPROM memory according to the present invention are described in more detail below.

Fig. 1 shows in block diagram the general structure of a microcircuit provided with the EEPROM memory described above.

2 shows a graph with a high voltage ramp surface for programming or erasing EEPROM memory.

3 is an electrical diagram of an EEPROM memory in accordance with the present invention.

4 illustrates the switching element of the memory of FIG. 3 in more detail.

5 is an electrical diagram of a circuit for generating the lamp voltage of FIG. 2 in accordance with the present invention.

6 is an electrical diagram of a circuit for detecting a failure of a power supply voltage according to the present invention.

7 is an electrical diagram of a circuit for sensing high voltage programming or erasing in accordance with the present invention.

FIG. 8 is a logic diagram of a circuit for generating a signal for suppressing the ramp generation circuit of FIG. 5.

9 illustrates another embodiment of the sensing circuit of FIG. 6.

10 is a flowchart showing the operation of a microcircuit having a memory according to the present invention.

In order to achieve this object, the present invention is first of all based on the consumption of very small current in an EEPROM memory to perform the programming or erasing operation of the memory cells. For example, in an EEPROM memory designed as a floating gate MOS transistor, the voltage Vpp is applied between the gate G and the drain D of the MOS transistors that are separated from each other.

Thus, the first concept of the present invention is to maintain the voltage Vpp for the time required for the programming or erasing operation. Due to the fact mentioned above, it is technically possible to carry out such maintenance, for example with capacitive elements. Another concept of the present invention is to maintain a path that sends a high voltage to the memory cells when the supply voltage is interrupted. In fact, the Applicant knows that in conventional EEPROM memories, blocking the supply voltage Vcc means breaking the electrical path that transfers the Vpp voltage to cells in the process of being programmed or erased.

More specifically, the present invention provides a means for generating a high voltage for programming or erasing from a power supply voltage, a means for maintaining a path for delivering a high voltage to memory cells in the process of being programmed or erased if the power supply voltage is bad, and high voltage. Provides a programmable and removable memory having an electrical capacity to maintain.

According to one embodiment, the means for maintaining a high voltage pass to the memory cells in the process of being programmed or erased comprises memory switches coupled to the high voltage, the outputs of which transistors, memory cells to carry the high voltage. Control transistors and transistors connected to ground.

Preferably, the capacity for maintaining the high voltage has a stabilization capacity that appears in the high voltage generating means.

Preferably, when a high voltage is applied by the ramp generation circuit, the memory is provided with means for suppressing the ramp generation circuit when the power supply voltage is bad.

The present invention also relates to a method of reducing the risk of writing error data into an electrically programmable and erasable memory when a power supply voltage failure occurs during programming or erasing operations of memory cells. And a method for maintaining a path for delivering a high voltage to the memory cells when the power supply voltage is lost and for maintaining a high voltage for a time necessary for a programming or erasing operation.

In order to reduce the risk of writing error data to the EEPROM memory 10 of the type already described with reference to FIG. 1, the present invention provides technical devices that ensure that the initiated programming or erase operation is completed even if the power supply voltage Vcc disappears. to provide. In particular, the present invention provides the following devices;

(A) a device which maintains a path for transferring a high voltage Vpp to the memory cells C _{i, j} when the supply voltage Vcc is insufficient,

(B) A device that maintains high voltage Vpp for at least the time required for programming or erasing operations. For this purpose, capacity can be used outside the silicon chip into which the memory is integrated, but this represents an industrial disadvantage, particularly in the manufacture of chip cards or electronic labels. Preferably, the present invention provides for maintaining a high voltage by a capacitive element already present in the chain 30 which generates a high voltage Vpp, in particular by the stabilizing capacitance Chv already described.

(C) a device for suppressing or blocking elements of the chain 30 consuming current to provide a high voltage Vpp. This last device is optional and can reduce the size of capacitive devices that maintain high voltage Vpp.

First, an embodiment of the EEPROM memory corresponding to the device A is described.

Device A: Maintain a pass to deliver high voltage Vpp

FIG. 3 shows in a detailed manner an embodiment according to the invention of an EEPROM memory 10 of the general structure already described in connection with FIG. For simplicity, memory 10 has only six memory cells C _{i, j} arranged in rows and columns, where i and j are subscripts with values from 1 to 3 and represent the number of rows and columns in each cell C _{i, j} Represent each.

In the conventional scheme, each memory cell C _{i, j} has an access transistor TA _{i, j} and a floating gate transistor TFG _{i, j} having a drain D connected to the access transistor TA _{i, j} . The source S of each floating gate transistor TFG _{i, j} is connected to the conductive line AG. The conductive line AG, shared by all floating gate transistors, becomes the floating potential during the programming operation and becomes the potential zero (ground) during the erase operation. The gates G of the floating gate transistors TFG _{i, j in} the same row (same i subscript) are the row select transistors TSWL _i (TSWL ₁ , TSWL ₂ ,) by a common conductive line WLi (WL ₁ , WL ₂ , WL ₃ ). Is connected to the source S of TSWL ₃ ). Gates G of the access transistors TA _{i, j} of the same row cells are connected to the gate G of the row select transistor TSWL _i by a common conductive line WLS _i (WLS ₁ , WLS ₂ , WLS ₃ ). The drains D of the row select transistors TSWL _i are all connected to the drain D of the programming transistor TPGR ₁ and the source S of the erasing transistor TDEL. The source S of the programming transistor TPGR ₁ is connected to ground and the drain D of the erasing transistor TDEL receives a high voltage Vpp when the chain 30 of FIG. 1 is activated. In addition, the drains D of the same row of access transistors TA _{i, j} are connected to the column select transistors TSBL _i (TSBL ₁ , TSBL ₂ , TSBL ₃ ) by a common conductive line BL _i (BL ₁ , BL ₂ , BL ₃ ). Is connected to source S. Finally, the drains D of the column select transistors TSBL _i (TSBL ₁ , TSBL ₂ , TSBL ₃ ) are all connected to the source S of the programming transistor TPGR _{2 where} the drain D receives a high voltage Vpp.

According to the present invention, transistors that allow high voltage Vpp to be transferred to memory 10 and enable cells C _{i, j} and enable ground connection, here row select transistors TSWL ₁ , TSWL ₂ , TSWL ₃ , programming transistors. The gates G of TPGR ₁ , TPGR ₂ , the erasing transistor TDEL and the column select transistors TSBL ₁ , TSBL ₂ , TSBL _{3 maintain} the Vpp voltage or zero voltage (ground) on their output terminal OUT even if the power supply voltage Vcc disappears. It is driven by the memory switches SW ₁ , SW ₂ , SW ₃ , SW ₄ , SW ₅ , SW ₆ , SW ₇ , SW ₈ , and SW ₉ , respectively. Each switch SW _i is composed of an output OUT connected to one gate of the above-described transistors, a control input IN1 and a power input IN2 receiving a high voltage Vpp. The control inputs IN1 of the switches SW ₁ , SW ₂ , SW ₃ are driven by the outputs S1, S2, S3 of the low decoder DWL via the isolation transistors TI ₁ , TI ₂ , TI ₃ . The control inputs IN1 of the switches SW ₄ , SW ₅ , SW ₆ are driven by the outputs S1, S2, S3 of the operation decoder DOP via the isolation transistors TI ₄ , TI ₅ , TI ₆ . Finally, the control inputs IN1 of the switches SW ₇ , SW ₈ , SW ₉ are driven by the outputs S1, S2, S3 of the column decoder DBL via the isolation transistors TI ₇ , TI ₈ , TI ₉ . (In order to conform to the general structure shown in Fig. 1, the switch portions SWWL and SWBL and the operation selection circuit COM are bounded by the dot lines in Fig. 3). Here, the isolation transistors of TI ₁ to TI ₉ have a gate G thereafter. Morse transistors controlled by the signal Vx to be described.

4 shows an embodiment of a memory switch SW _i according to the invention. The switch comprises two inverting gates INV ₁ , INV ₂ , which are arranged in front of one another and which are supplied with a high voltage Vpp. The output of the gate INV ₁ forms the output OUT of the switch SW _i and is fed back to the gate of the gate INV ₂ . The output of the gate INV ₂ forms the control input IN1 of the switch and returns to the input of the gate INV ₁ . The inverting gates INV ₁ , INV ₂ are CMOS type here and include PMOS transistors TSW ₁ , TSW ₃ and NMOS transistors TSW ₂ , TSW ₄ , respectively, and a high voltage Vpp is supplied to the source S of the PMOS transistors. It can be seen that the closed circuit structure of the switches SW _i maintains the state of their output OUT indefinitely as long as the voltage Vpp is present. In addition, the state of the output OUT can be changed by the inverse control of the input IN1, and the switches are inverters here for design simplification. However, it can be noted that the switch SW _i can be designed as a non-inverting inverter, for example four closed-circuit inverting gates or other electronic devices, within the skill of the person skilled in the art.

In order to perform the programming or erasing operation of cells C _{i, j} of memory 10, the output OUT of several switches SW _i is set to 1 (i.e. to voltage Vpp) even if the power supply voltage Vcc is bad. State must be maintained. Referring again to FIG. 3, assume, by way of example, a program in cell C ₁ , ₁ (ie, set to logic state “1”). Transistors TSWL ₁ , TA ₁ , ₁ and TSBL ₁ must be turned on to select cell C ₁ , ₁ . TPGR transistor ₂ has a floating gate transistor TFG must be turned on to transfer the voltage Vpp to the drain of the _{1, 1,} and transistor TPGR transistor ₁ also applies a ground voltage to the gate G of the transistor TFG _{1, 1} and within a tunnel TFG _1,1 It must be turned on to effect the charge transfer. Thus, the following operations must be performed;

(Iii) the beginning of the high voltage Vpp generation chain shown in FIG.

(Ii) The output S1 of the low decoder DWL, the outputs S1 and S2 of the operation decoder DOP, and the output S1 of the column decoder DBL are set to 0, and the outputs of all other decoders are 1, that is, Vcc voltage. Decoders are supplied with Vcc voltage as usual.

(Iii) The signal Vx is set to " 1 " so that the isolation transistors TI _i are turned on for the outputs of the decoders DWL, DOP, DBL to drive the inputs IN1 of the memory switches SW ₁ to SW ₉ . At the end of this step, the voltage Vpp (logic "1" of switches SW _i ) is connected to the outputs OUT of switches SW ₁ , SW ₄ , SW ₅ , and SW ₇ and the outputs OUT are grounded (logical "0"). Input switches SW ₂ , SW ₃ , SW ₆ , SW ₈ , SW ₉ appear at inputs IN1. Because of the voltage Vpp present at the inputs IN1 of the switches SW ₂ , SW ₃ , SW ₆ , SW ₈ , SW ₉ , the source S of the corresponding isolation transistors TI ₂ , TI ₃ , TI ₆ , TI ₈ , TI ₉ Since the potentials are higher than their drain D, which is Vcc, these transistors are in the off state, thus separating the voltage Vpp from the voltage Vcc.

Once these operations are performed, transistors TSWL ₁ , TA ₁ , ₁ , TPGR ₁ , and TSBL ₁ have received the Vpp voltage at gate G. The voltage Vpp is transferred to the drain D of the floating gate transistor TFG ₁ , ₁ by transistors TSBL ₁ and TPGR ₂ . Gate G of TFG _1,1 is connected to ground by transistors TPGR ₁ and TSWL ₁ . Due to the tunnel effect in the floating gate of transistors TFG _1,1 , the normal charge transfer process is started and performed for several ms.

Preferably, even though the Vcc voltage is bad during the programming process and the electrical supply is insufficient and the outputs of the decoders DWL, DOP, DBL go to zero, the switches SW _i remain in their output OUT as long as the Vpp voltage is provided. , The transfer of voltage Vpp is maintained. In addition, transistor TPGR _{1, which} is responsible for the transfer of voltage 0 (ground), is controlled by switch SW ₄ and remains on as long as the Vpp voltage is present. In the prior art, such transistors were directly controlled by voltage Vcc, and a failure of this voltage Vcc meant blocking of the path to ground. As a result, the advantages of the present invention are also found not only in the transistor TSWL _i of the row to be deleted, but also in the erase operation (switching the row of cells C _{i, j} to the " 0 " state) requiring the turn on of the transistor TDEL.

Since the first object of the present invention is achieved, what is needed is done to ensure the maintenance of the Vpp voltage for the time required by the programming or erasing operation. The second object of the present invention is to make the current consumed in the case of a Vcc voltage failure as small as possible, since neither the size of the capacity used for this purpose is enlarged in an unacceptable manner nor the external capacity. The necessary work is done first (device C).

Apparatus C: to switch off or inhibit certain elements

In the case of the chain 30 shown in FIG. 1, the best factors that can discharge the capacitance holding the voltage Vpp are the regulator 33 and the ramp generator 34 which generally consumes a small current in its operation. In fact, oscillator 31 and charge pump 32 (or other booster circuit) stop working when the Vcc voltage disappears.

Fig. 5 shows a particularly simple embodiment with a lamp generator 34 which does not consume current when a failure occurs in the regulator 33 and the power supply voltage Vcc, which can be suppressed by the signal STPRAMP.

The regulator 33 includes the MOS transistor 33-1 in which the gate G is fed back to the drain by the resistor 33-2 in a conventional manner. Gate G of transistor 33-1 is biased by zener diode 33-3, which provides a reference voltage Vref. The voltage at the output of regulator 33 is called the voltage Vppreg.

At the input of ramp generator 34, voltage Vppreg is applied at one end of drain D and resistor R of transistor TR ₁ . The other end of the resistor R is connected to the gate G of the transistor TR ₁ and the anode end of the capacitor CR ₁ . The cathode of the capacitor CR ₁ is coupled to a current source IR to impose a charge current I _c of the smaller value to the gate G and the capacitor CR ₁ of the transistor TR _2. Transistor TR ₂ has its drain D connected to gate G of transistor TR ₁ . Its source S is connected to ground by transistor TR ₃ which acts as a diode (gate is fed back to drain) arranged in series with transistor TR ₄ . Gate G of transistor TR ₄ is controlled by signal STPRAMP which is set to zero when the power supply voltage is bad. The output of the ramp generation circuit 34 is received by the source S of the transistor TR ₁ and regulated by the capacitor CR ₂ .

When the signal STPRAMP is 1 (transistor TR ₄ is on) and the voltage Vppreg rises sharply at the input of circuit 34 (charge pump 32 activated by oscillator 21), the voltage V1 appearing at the cathode of the capacitor CR ₁ is charged. The current I _c increases rapidly because the capacitor CR ₁ is so small that it cannot quickly absorb voltage variations due to the appearance of the Vppreg voltage. When the voltage V1 is a 2VT value, VT is the threshold voltage of the transistors TR ₂ , TR ₃ , when higher, the transistor TR ₂ turns on and slows down the V2 voltage increase that appears at the gate G of the transistor TR ₁ . Due to the charge of the capacitor CR ₁ , the voltage V2 slowly increases until the value Vppreg is reached. The voltage Vpp is equal to the voltage V2 minus the threshold voltage VT of transistor TR ₁ . As shown in Fig. 2, the graph of the Vpp voltage shows a flat section equal to the first part having a ramp shape, followed by the maximum value of the voltage Vppmax;

(1) Vppmax = Vppreg-VT

Where VT represents the threshold voltage of transistor TR ₁ .

It can be seen that the current consumed during the ramp generation is mainly due to the transistors TR ₂ , TR ₃ , TR ₄ and due to the current flowing through the zener diode 33-3 of the regulator 33. When signal STPRAMP is set to zero, transistor TR ₄ and the resulting transistors TR ₂ and TR ₃ are no longer conducting and consume no more current. The capacitor CR ₁ becomes floating and the voltage V2 of the transistor TR ₁ gate rises quickly to the voltage Vppreg. The electrical charge stored in the capacitor Chv is transferred to the capacitor CR ₂ so that the zener diode 33-3 is cut off and the voltage Vpp reaches the maximum value Vppmax in a very short time, as indicated by the dotted line in FIG. 2.

Device B: Maintain Voltage Vpp

In the following, the internal capacities of chain 30 indicate here that Chv, CR ₁ , CR ₂ capacities, alone, can maintain high voltage Vpp without requiring an increase in the unacceptable silicon area occupied by these capacities.

Referring again to FIG. 5, when the signal STPRAMP is set to zero, the capacity Chv at the output of charge pump 32 reaches the capacity CR to quickly reach a value Vprog sufficient to carry out the programming or erasing process in which voltage Vpp is started. _It should be possible to guarantee the transfer of the electrical charge to ₂ . In a specific embodiment given, when STPRAMP switches to zero, the total charge Q1 stored in chain 30 is as follows;

(2) Q1 = Vhv Chv + K Vppreg CR ₁ + (KVPPreg-VT) CR ₂

(VT-KVppreg) is a voltage Vpp value when the power supply voltage Vpp defect, K is a parameter composed of between 0 and 1, VT is the threshold voltage of the transistor TR _1.

After charge transfer, the voltage Vhv at the Chv stage is approximately equal to Vppreg, transistor 33-1 of regulator 33 acts as a simple diode, and zener diode 33-3 is no longer conducting. If charge transfer occurs correctly, the total charge Q1 can be written as:

(3) Q1 = Vprog (Chv + CR ₁ + CR ₂ )-VT CR ₂

Vprog represents the final value of the programming voltage Vpp after charge transfer.

Combining Equations (2) and (3) is inferred as follows:

(4) Chv = (Vprog-K Vppreg) (CR ₁ + CR ₂ ) / [Vhv-Vprog]

Once the programming voltage Vprog has been selected, the determination of the capacity Chv is a practical matter within the skill of one skilled in the art. Despite the careful care taken, it should be taken into account that leakage currents inherent in integrated circuit technology will remain. For example, if the following value is selected;

CR ₁ = 5 pF,

CR ₂ = 3 pF,

Vhv = 22 V,

Vppreg = 20 V,

Vprog = 19 V,

If charge transfer is performed at 75% of the voltage ramp, or K, at 0.75, Equation (4) gives the Chv minimum value of 10.6 pF, which together with the capacities CR ₁ and CR ₂ is about 18 pF overall for the entire chain 30. Means equivalent capacity. If there is a leakage current of 10 nA, this capacity maintains a voltage Vprog that is reduced by only 1V at the end of this period for 1.8 ms, which is sufficient for good programming.

Capacity Chv Size Optimization

Equation (4) shows that the value of the capacity Chv required to transfer electric charges increases as the value of K decreases. Thus, if we want the capacity Chv to have a small value and a small magnitude during the transfer of charge to the capacitor CR ₂ , the K item should be close to 1 and the failure of the voltage Vcc is preferably instantaneous when the voltage Vpp is near the maximum value Vppmax. You must wake up.

Here, the concept of the present invention is not to convey the signal SRPRAMP when the Vpp voltage falls below the efficiency threshold Vppmin starting to act on the memory cells C _{i, j} . Typically, the threshold Vppmin is on the order of 15V for EEPROM memory using floating gate transistors. An optional aspect of the present invention is to optimize the size of the capacity Chv and, on the other hand, to avoid the transfer of charge of the capacity Chv when the programming or erasing operation has not actually started despite the activation of the generation chain 30 of the voltage Vpp.

6, 7 and 8 show circuits that enable the generation of the signal STPRAMP under the conditions described above. Circuit 40 of FIG. 6 is a circuit that detects a failure of the Vcc voltage and generates a failure signal VCCDET. Circuit 50 of FIG. 7 enables the generation of signal DETECT when voltage Vpp reaches efficiency threshold Vppmin. Finally, Figure 8 shows a logic circuit that generates a signal STPRAMP in combination with VCCDET and DETECT. In a general manner, it will be appreciated that most logic gates used in the circuit design of FIGS. 6, 7 and 8 are provided with a voltage Vppreg so as not to be affected by a Vcc voltage failure. Preferably, these logic gates are implemented by CMOS technology so as not to draw current outside the range of the switching interval.

Circuit 40 of FIG. 6 includes a MOS transistor 41 that receives a power supply voltage Vcc at its gate. The source S of transistor 41 is connected in series and connected to ground by two MOS transistors 42, 43 acting as a diode. Drain D of transistor 41 is coupled to voltage Vppreg by current source 44 as well as to the input of inverting gate 45. The output of gate 45 feeds to the input of second inverting gate 46 which generates signal VCCDET. The signal VCCDET switches to 1 when the power supply voltage Vcc becomes lower than the threshold Vccmin equal to the sum of the threshold voltages of the transistors 41, 42, 43. Vccmin may be determined to be 3V, for example.

Circuit 50 of FIG. 7 divides the voltage Vpp and includes a bridge consisting of two capacitances 51, 52. The midpoint 53 of the split bridge is connected to the gate G of the MOS transistor 54. Capacities 51 and 52 are determined such that the midpoint voltage is equal to the threshold voltage VT of transistor 54 when voltage Vpp reaches efficiency voltage Vppmin. The source S of transistor 54 is connected to ground and its drain D is connected to the input of inverting gate 55 which outputs signal DETECT. The logic state of the gate 55 is stabilized by the P-type MOS transistor 56 supplied with the voltage Vppreg. Finally, Morse transistor 57, controlled by signal ACTVPP through inverting gate 58, connects midpoint 53 of the split bridge to ground. Thus, when signal ACTVPP is zero, i.e., outside the activation period of chain 30 which generates voltage Vpp, circuit 50 is disabled, so that output DETECT is zero. When ACTVPP is set to 1, the voltage at midpoint 53 increases until the threshold voltage VT of transistor 54 is reached. At this point, the voltage Vpp is equal to Vppmin, transistor 54 turns on and signal DETECT transitions to one.

As shown in FIG. 8, signals VCCDET and DETECT are coupled by a NAND type logic gate 60 whose output generates a signal STPRAMP. In order for the signal STPRAMP to switch to zero and to suppress the ramp generation circuit 34 in Fig. 5, both VCCDET and DETECT need to be one.

In addition, referring again to FIG. 7, it can be seen that the signal DETECT can be used to generate a signal Vx that controls the isolation transistors TI _i in memory 10 (FIG. 3). The signal Vx is generated by an inverting gate 59 that receives the signal DETECT as input and transitions to zero when the voltage Vpp reaches the efficiency threshold Vppmin. The advantage is that when the signal DETECT switches to 1, the signal Vx is automatically reset and the disconnect switches TI _i are surely disconnected. Thus, in the case of a further failure of the voltage Vcc, there can be no reverse current phenomenon that can flow through the switches TI _i when the signal Vx is not zero.

FIG. 9 shows an alternate circuit 40 'of the circuit 40 of FIG. Circuit 40 'detects the failure of voltage Vcc by monitoring the voltage Vppreg at the output of regulator 33 instead of monitoring the voltage Vcc itself. The advantage is that there is no concern with slight defects or fluctuations in the Vcc voltage for a very short time which allows to start the protective mechanism according to the present invention. A first current source 61 generating current Ivpp is disposed between the output of regulator 33 and the drain D of NMOS transistor 62 which receives signal DETECT at gate G. The source S of transistor 62 is connected to ground by a second current source 62 which generates a current Ignd. Drain D of transistor 62 supplies the input of inverting gate 64, which is supplied with voltage Vppreg and generates signal VCCDET. Finally. The NMOS transistor 65 controlled by the signal DETECT is disposed between the voltage Vppreg and the input of the inverting gate 64. Current sources 61 and 63 are adjusted such that current Ivpp is greater than current Ignd when voltage Vppreg is at its normal value Vregnom. When signal DETECT transitions to 1, transistor 62 is on, current Ivpp exceeds current Ignd and voltage at drain D of transistor 62 is close to Vppreg. In particular, if the voltage Vppreg decreases due to a failure of the supply voltage Vcc, the current Ivpp decreases and the drain D voltage decreases, causing the inversion of the inverted gate 64 to switch the output VCCDET to 1. On the other hand, when signal DETECT is 0, circuit 40 'is cut off and transistor 65 sets signal VCCDET to zero. Thus, signal VCCDET cannot switch to 1 while signal DETECT is not one. Thus, the NAND gate of FIG. 8 becomes unnecessary, and the inverted signal / VCCDET of the signal VCCDET can be used like the signal STPRAMP.

In the foregoing, the protection of the EEPROM memory integrated into the microcircuit 1 including the various functions symbolically represented by the logic circuit 20 has been addressed. In the field of chip cards, these functions are, for example, the management of processing operations, the execution of encrypted operations that enable competition for falsehood, and the like, whereby EEPROM memory is used by microcircuit 1 as data recording and storage means. However, it is evident that the present invention applies to logic circuit 20, microcircuit 1, i.e., a simple EEPROM microcircuit, which does not include externally controllable decoders DWL, DOP and DBL.

When microcircuit 1 includes the functions described above, in some applications the performance of the present invention may represent a difficulty associated with the presence of minor failures in voltage Vcc during shorter periods during programming or erasing operations. In fact, as is common in the prior art, when turned on, the logic circuit 20 is systematically reset (set to zero), the logic circuit 20 reads a new programming operation or read of the memory during the programming operation that was initiated before the minor failure was still over. Initiating an operation may occur. In this case, the present invention provides the following supplemental devices;

(D) providing a time drag step at least equal to the programming or erasing operation period when the supply voltage Vcc appears. After this time dragging phase, the logic circuit 20 can be reset.

(E) The time drag step is only performed when high voltage Vpp appears at the output of chain 30. The replacement of this device D may be to determine whether the capacity Chv is in a charged or discharged state before carrying out the time dragging step. In fact, if microcircuit 1 "wakes up" when the power supply voltage Vcc is turned on, it is not known whether the appearance of Vcc involves a slight failure or long-term shutdown. Confirming the presence of Vpp or Vhv preferably leads to the removal of this question. A simple way to do this verification is to read the output of circuit 50 in FIG. If signal DETECT is 1, the reset of logic circuit 20 should be temporary.

(F) Chain 30, generating voltage Vpp, is active during the time drag. This device is an improvement over devices D and E. In fact, if the voltage Vpp is not zero when the voltage is turned on (for example, because the DETECT signal is 1), the capacitors Chv and CR ₂ will not be charged at the end of the current programming or erasing operation, instead of the charge pump 32's operation. It may be advantageous to allow a restart;

This mode of operation of microcircuit 1 is illustrated by flowchart 70 of FIG. 10. When voltage Vcc is turned on (step 71), logic circuit 20 checks for the presence of a Vpp voltage (step 72). This check is, for example, a signal DETECT to check if the voltage Vpp is higher than Vppmin. If the test result is yes, circuit 20 activates chain 30 (step 74, ACTVPP = 1) and waits for several ms (step 75, TEMPO). The circuit 20 then generates its own reset (step 76, RST). If the 72 step test is negative, circuit 20 immediately resets after it is provided (step 73, RST).

In the above, an example of carrying out the present invention has been described, which is connected to a specific structure of an EEPROM memory using a floating gate transistor and a specific structure of a chain that generates a high voltage Vpp. From the information and examples presented herein, one skilled in the art would apply the present invention to other forms of EEPROM memories as long as these memories do not consume current during programming or erasing intervals, which is a common practice.

In addition, ramp generation circuit 34 may be unnecessary depending on the type of EEPROM memory used. It should be recalled that applying the ramp voltage Vpp to the memory cells has only the purpose of protecting the cells against minor damage that may be caused by the sudden application of voltage Vpp in each programming or erase operation. This ramp voltage can prove to be necessary for some types of cells, especially cells using floating gate transistors. However, such voltage ramps are not inevitable for programming. Moreover, those skilled in the art will appreciate that breaking this ramp voltage in exceptional cases when the present invention occurs does not have a significant burden on the life of the cells. After all, the use of a difference pump is inevitable and one skilled in the art knows another way to design booster circuits.

Claims (18)

An electrically erasable and programmable memory (10) having means (30) for generating a high voltage (Vpp) for programming or erasing from a power supply voltage (VCC). An electrical capacity (Chv, CR ₂ ) capable of maintaining the high voltage (Vpp) when the power supply voltage (Vcc) is bad; When the power supply voltage Vcc is defective, the power supply voltage Vcc is disposed to maintain a path for transferring the high voltage Vpp to the memory cells Ci _{and j} in a program or erase process, and the high voltage is supplied. Memory (10), characterized in that it comprises a memory switching means (SW _i ). The method of claim 1, wherein the memory 10 Memory switching means SW _{i for} outputs OUT to control transistors TPGR ₁ , TPGR ₂ to deliver the high voltage Vpp; Memory switching means SW _i whose outputs OUT control transistors TSWL _i and TSBL _i to select memory cells; And And memory switching means SW _i for controlling the transistors TPGR _{1 to} which the outputs OUT are grounded. The method of claim 2, wherein the memory switching means (SW _i ) is And at least two closed circuit inverting gates (INV ₁ , INV ₂ ) supplied with said high voltage (Vpp) and controlled by isolation transistors (TI _i ). The capacity of any one of claims 1 to 3, wherein the capacitance capable of maintaining the high voltage Vpp is And a stabilizing capacitance (Chv) in said means (30) for generating said high voltage. The method according to any one of claims 1 to 3, The high voltage Vpp is provided to the memory cells through a ramp generation circuit 34, And means (TR4, 40, 40 ', 50, 60) for suppressing the lamp generating circuit (34) when the power supply voltage (Vcc) is bad. 6. The means (TR ₄ , 40, 40 ', 50, 60) of claim 5, wherein the means for suppressing the ramp generating circuit (34) A circuit (40, 40 ') that detects a failure of the power supply voltage (Vcc) and is activated when a failure of the power supply voltage (Vcc) is detected; A circuit 50 for monitoring the lamp voltage Vpp at the output of the lamp generating circuit 34 and activating when the lamp voltage Vpp reaches an efficiency threshold voltage Vppmin (DETECT), The ramp generation circuit (34) is suppressed when both circuits are activated. The circuit of claim 6, wherein the circuit 40 for detecting a failure of the power supply voltage Vcc is And monitor the power supply voltage to be activated when the power supply voltage is below a predetermined threshold voltage (Vccmin). 7. The circuit (40) of claim 6, wherein the circuit (40 ') for detecting a failure of a power supply voltage (Vcc) is And monitoring the high voltage (Vppreg) applied to the ramp generation circuit (34) to activate when the high voltage (Vppreg) falls below its normal value (Vregnom). A memory of any one of claims 1 to 3; And And a logic circuit (20) using said memory (10) as a means for storing data. 10. The method of claim 9 wherein the beginning of the logic circuit 20 And when the power supply voltage appears, delayed during a time interval of about a programming or erasing operation period of the memory (10). 11. The method of claim 10, wherein the beginning of the logic circuit 20 The high voltage (Vpp) appears at the output of the means (30) for generating the high voltage (Vpp), delayed. Risk of writing error data in the electrically erasable or programmable memory 10 when a failure of the power supply voltage Vcc of the memory 10 occurs during the programming or erasing operation of the memory cells C _{i, j} . As a method of reducing the voltage, the memory 10 has means 30 for generating a high voltage Vpp for programming or erasing, Providing an electrical capacity (Chv, CR ₂ ) capable of maintaining the high voltage in the event of a failure of the power supply voltage during the time required for a programming or erasing operation; When the power supply voltage Vcc is bad, the high voltage Vpp is supplied to maintain a path for transferring the high voltage Vpp to the memory cells Ci _{and j} during a program or erase process. Providing a memory switching means (SW _i ). The method of claim 12, wherein the electrical capacitance is And at least a stabilizing capacity (Chv, CR ₂ ) in said means (30) for generating said high voltage (Vpp). The method of claim 12 or 13, wherein the method Memory switching means SW _{i for} outputs OUT to control transistors TPGR ₁ , TFGR ₂ to deliver the high voltage Vpp; Memory switching means SW _i whose outputs OUT control transistors TSWL _i , TSBL _i to select memory cells, and A memory switching means (SW _i ) is provided for controlling transistors (TPGR ₁ ) whose outputs (OUT) are grounded. The method of claim 12 or 13, wherein the method Blocking or inhibiting memory circuits (34) capable of consuming current. The path of claim 12 or 13, wherein the path for delivering the high voltage (Vpp) is And when the high voltage (Vpp) applied to the memory (10) when the failure of the power supply voltage (Vcc) is provided to have a value equal to or higher than the efficiency threshold voltage (Vppmin) is maintained. . The method of claim 12 or 13, wherein detecting the failure of the power supply voltage Vcc is Determining whether the power supply voltage is below a predetermined threshold voltage (Vccmin). The method of claim 12 or 13, wherein detecting the failure of the power supply voltage Vcc is Determining whether the voltage (Vppreg) present in the means (30) for generating the high voltage (Vpp) is below a normal value (Vregnom).