KR100468724B1 - High speed programmable ROM and memory cell structure therefor and method for writing/reading a ROM data in/from the programmable ROM - Google Patents

Abstract

A high speed programmable ROM system and a memory cell structure therefor and a method of writing and reading data in the programmable ROM are disclosed. The programmable ROM system according to the present invention includes a plurality of memory cells each having a gate, a first electrode, and a second electrode, each of a plurality of word lines connected to gates of a plurality of memory cells, and each of a plurality of memory cells. A plurality of bit lines connected to the first electrodes of the plurality of first electrodes, the bit lines disposed in a substantially vertical direction with the word lines, and selectively connected to a ground power source in response to the control signals, and a plurality of bit lines disposed substantially in the vertical direction with the word lines. It is preferable to program the plurality of memory cells to a predetermined logic level by including virtual ground lines, and selectively connecting a second electrode of each of the plurality of memory cells to the plurality of virtual ground lines. By selectively connecting the source of the cell transistor to the virtual ground line in accordance with the ROM data to be written, the capacitance of the bit line can be kept constant without being excessively large or small. This makes it possible to increase the operating speed of the programmable ROM while minimizing the misreading of programmed data.

Description

High speed programmable ROM and memory cell structure therefor and method for writing / reading a ROM data in / from the programmable ROM}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to a programmable ROM system of high speed operation.

A mask read only memory is a semiconductor memory device configured to enable a user to pre-code necessary data in a manufacturing process step and repeatedly read the coded data. Mask ROMs include embedded diffusion-programmable ROMs and embedded metal-programmable ROMs. The embedded diffusion programmable ROM is determined by the ROM process code during the manufacturing process, and the embedded metal programmable ROM is determined by the ROM process code during the manufacturing process.

On the other hand, there is an embedded contact programmable ROM or an embedded Via programmable ROM that is almost identical to an embedded metal programmable ROM. The embedded contact programmable ROM is determined by the ROM process code during the manufacturing process and the embedded via programmable ROM is determined by the via process stage during the manufacturing process.

In general, embedded diffusion programmable ROMs have been preferred over embedded metal programmable ROMs, since the former can achieve approximately 25% to 35% higher integration than the latter.

However, the embedded diffusion programmable ROM has a drawback in that the time required to make a finished product after receiving data from the user, that is, turn-around-time is longer than that of the embedded metal programmable ROM. Recently, with the development of semiconductor manufacturing process technology, the density of embedded metal (or via) programmable ROMs has been greatly improved, and the importance of embedded metal (or via) programmable ROMs, which is advantageous in time-to-market, has been highlighted.

1 is a diagram illustrating a cell array structure of a conventional metal programmable ROM. For convenience of description, two bit lines BL0 and BL1, three virtual ground lines VG0 to VG2, four word lines WL0 to WL3, and sixteen cell transistors M1 to M16 are illustrated in FIG. 1. A 4 * 4 bit cell array structure is shown. Here, the virtual ground line is not shown, but is a line that is selectively connected to the ground power source by a switch. In addition, in FIG. 1, the capacitors C1 to C4 represent coupling capacitances between lines rather than actual circuits. C5 represents the total capacitance of the bit line BL0, and C6 represents the total capacitance of the bit line BL1.

Referring to FIG. 1, gates of each of the sixteen cell transistors M1 to M16 are connected to a word line, and a source is connected to a virtual ground line. In addition, the drains of the transistors M1 to M16 may be selectively programmed by electrically connecting the bit lines. That is, "0" is programmed to the cell transistor by electrically connecting the drains of the cell transistors M1 to M16 to the bit line, and "1" is programmed to the transistor by floating the drain. On the other hand, the speed of the programmable ROM depends on the total capacitance loaded on the bit line. The total capacitance loaded on the bit line determines the time for which the bit line is precharged and then discharged. Therefore, when the total capacitance is large, the operation speed of the entire ROM is reduced.

In addition, the ratio of the total capacitance and the coupling capacitance between the corresponding bit line and the adjacent adjacent line is also an important item in the evaluation of the programmable ROM. If this ratio is large, transitions of adjacent lines may interfere with the corresponding bit lines, thereby preventing the pre-charged bit lines from being charged. As a result, ROM data may be incorrectly read. In order to prevent such a malfunction, the ratio of the coupling capacitance between adjacent lines to the total capacitance is reduced. To do this, the amount of total capacitance loaded on the bit line must be increased, but this causes a problem that the speed is lowered as described above.

In the programmable ROM illustrated in FIG. 1, all cells connected to the bit line BL0 are programmed to "0", and all cells connected to the bit line BL1 are programmed to "1". At this time, the total capacitance C5 loaded on the bit line BL0 becomes maximum, the total capacitance C6 loaded on the bit line BL1 becomes minimum, and the operating speed of the programmable ROM is determined by the bit line BL0.

Here, the factors influencing the capacitance of the bit line BL0 include the capacitance by the bit line length, the capacitance by the programming metal lines 28, the capacitance by the contacts CNT1 connected to the bit line, and It is the capacitance by the transistors M1 to M8 connected to the bit line. Due to the influence of these capacitances, the total capacitance C5 of the bit line BL0 has a very large value, which slows down the program ROM. However, since the ratio (= C1 / C5 or C2 / C5) with the coupling capacitance of the adjacent lines VG0 and VG1 is small, the ROM data can be prevented from being read incorrectly by the coupling capacitance with the adjacent lines. .

On the other hand, since the only factor influencing the capacitance of the bit line BL1 is the capacitance by the bit line length, the total capacitance C6 of the bit line BL1 has a very small value compared to C5. Therefore, the ratio of the coupling capacitance (= C3 / C6 or C4 / C6) with the adjacent lines VG1 and VG2 is increased so that the ROM data of cells connected to the bit line 12 is incorrectly read by the coupling capacitance. May be generated. As such, in order to prevent ROM data misreading by the coupling capacitor, it is necessary to slow down the operating time of the sense amplifier when the ROM data is read or to adjust the precharge and discharge time accordingly so that interference does not occur. Is degraded.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a high speed programmable ROM system for improving the operation speed and a memory cell structure therefor.

Another object of the present invention is to provide a method of recording and reading data in the programmable ROM.

Another object of the present invention is to provide a recording medium in which the data recording method is recorded by program code executable on a computer.

1 is a diagram illustrating a cell array structure of a conventional metal programmable ROM.

2 is a circuit diagram illustrating an embodiment of a cell array structure of a fast programmable ROM according to the present invention.

3 is a vertical cross-sectional view illustrating a vertical cross section of each cell transistor illustrated in FIG. 2.

4 is a circuit diagram illustrating a programmable ROM system according to the present invention.

FIG. 5 shows a timing diagram of signals for controlling the operation of the circuit shown in FIG. 4.

FIG. 6 is a flowchart illustrating a data reading process performed in the programmable ROM system shown in FIG. 4.

In order to achieve the above object, in a programmable ROM including a plurality of programmable memory cells, the programmable memory cell according to the present invention is a virtual ground line and word selectively connected to a ground power source in response to a word line, a bit line, and a control signal. A cell transistor having a gate connected to a line, a first electrode connected to the bit line, and a second electrode, the cell transistor being programmable to a predetermined logic level by selectively connecting the second electrode to a virtual ground line; It is preferable.

In order to achieve the above object, the programmable ROM system according to the present invention includes a plurality of memory cells each having a gate, a first electrode, and a second electrode, each of a plurality of word lines connected to gates of the plurality of memory cells, Each of the plurality of memory cells is connected to the first electrode of the plurality of memory cells, the bit lines disposed in a substantially perpendicular direction to the word lines, and each of which is selectively connected to the ground power supply in response to the control signals, and substantially perpendicular to the word lines. It is preferable to program the plurality of memory cells to a predetermined logic level by including a plurality of virtual ground lines arranged in a direction, and selectively connecting a second electrode of each of the plurality of memory cells to the plurality of virtual ground lines.

In order to achieve the above object, the programmable ROM system according to the present invention includes a plurality of memory cells each having a gate, a first electrode, and a second electrode, each of a plurality of word lines connected to gates of the plurality of memory cells, Each of the plurality of memory cells is disposed in a substantially vertical direction with the word lines, and bit lines to which the first electrodes of two memory cells adjacent in the horizontal direction are shared and connected to the ground power source in response to control signals. A plurality of virtual ground lines selectively connected to the word lines and disposed substantially perpendicular to the word lines, and selectively connecting a second electrode of each of the plurality of memory cells to the plurality of virtual ground lines to connect the plurality of memory cells. It is desirable to program to a predetermined logic level.

In order to achieve the above object, the programmable ROM system according to the present invention includes a plurality of memory cells each having a gate, a first electrode, and a second electrode, each of a plurality of word lines connected to gates of the plurality of memory cells, Each of the bit lines is disposed in a substantially vertical direction with the word lines, and the first and second bit lines of the four memory cells adjacent in the horizontal and vertical directions of the plurality of memory cells are shared and grounded in response to the control signals. And a plurality of virtual ground lines selectively connected to a power source, the plurality of virtual ground lines disposed substantially perpendicular to the word lines, and selectively connected to a plurality of virtual ground lines, respectively, with a second electrode of each of the plurality of memory cells. It is desirable to program the cells to a certain logic level.

In order to achieve the above another object, in a programmable ROM including a plurality of cell transistors having a gate, a first electrode and a second electrode, the method according to the present invention for writing binary data to a cell transistor is a gate and a first electrode. Is connected to a word line and a bit line, respectively, and selectively connects the second electrode to a virtual ground line selectively connected to a ground power source according to the binary data to be recorded. Do.

In order to achieve a further object, in a programmable ROM comprising a plurality of cell transistors having a gate, a first electrode and a second electrode, the method according to the invention for reading binary data stored in a cell transistor is provided. (A) precharging the bit line connected to one electrode to a high level, and if the second electrode of the cell transistor is connected to the virtual ground line, the potential of the bit line precharged in step (a) is replaced by the potential of the bit line. Is discharged to the ground power supply through the virtual ground line, and if the second electrode of the cell cell transistor is not connected to the virtual ground line, the potential of the precharged bit line is maintained in step (a) (c). Step (d) of sensing the potential of the bit line and (e) comparing the potential of the sensed bit line with the reference potential and reading binary ROM data according to the comparison result. This is preferred.

In order to achieve the above another object, in a programmable ROM including a plurality of cell transistors having a gate, a first electrode and a second electrode, a method according to the present invention for reading binary data stored in a cell transistor is provided. (A) precharging the bit line connected to the first electrode to a power supply level; and (b) enabling an internal clock signal when a clock signal requesting data reading from an external source is input; (C) discharging a control signal for disabling the internal clock signal and enabling the sense signal, enabling the word line in response to the internal clock signal, and stopping the precharge of the bit line (d). The second electrode of the cell transistor selected according to the virtual ground line selection signal and the bit line selection signal applied in response to the internal clock signal may be connected to the virtual ground line. (E) discharging the potential of the precharged bit line to the ground power supply through the virtual ground line, if the second electrode of the selected cell transistor is not connected to the virtual ground line ( (f) maintaining the potential of the precharged bit line in step a), disabling the internal clock signal in response to the control signal falling below a predetermined level, and enabling (g) the sense signal, In response to the enabled sense signal, in step (h) and (h) of sensing the potential of the bit line connected to the first electrode of the selected cell transistor, the potential of the sensed bit line is compared with the reference potential, and according to the comparison result. It is preferable that the step (i) be performed to read binary ROM data.

Hereinafter, a high speed programmable ROM system according to the present invention will be described with reference to the accompanying drawings.

2 is a circuit diagram illustrating an embodiment of a cell array structure of a fast programmable ROM according to the present invention. For convenience of description, two bit lines BL0 and BL1, three virtual ground lines VG0 to VG2, four word lines WL0 to WL3, and 16 N-type MOS transistors M1 to M16 are illustrated in FIG. 2. ) Represents a 4 * 4 bit cell array. Here, the capacitors C20 to C23 represent coupling capacitances between lines rather than actual circuits. C24 denotes the total capacitance loaded on the bit line BL0, and C25 denotes the total capacitance loaded on the bit line BL1. Also, for convenience of description, the programmable ROM illustrated in FIG. 2 is a via programmable ROM in which ROM data programming is performed in a via process step.

Referring to FIG. 2, the drains of the cell transistors M1 to M8 are connected to the bit line BL0, and the drains of the cell transistors M9 to M10 are connected to the BL1. At this time, the four cell transistors M1 to M4 and M5 to M8 adjacent to the bit line BL0 in the vertical and horizontal directions share the bit line BL0. Similarly, four cell transistors M9 to M12 and M13 to M16 that are vertically and horizontally adjacent to the bit line BL1 have a structure sharing the bit line BL1.

For convenience of explanation, it is assumed that cell transistors M1 to M8 are programmed with "0", and cell transistors M9 to M16 are programmed with "1". As such, the source of the cell transistors M1 to M8 is connected to the virtual ground line VG0 or VG1 to program "0" to the cell transistors M1 to M8, respectively. Further, in order to program " 1 " to the cell transistors M9 to M16, the source of the cell transistors M9 to M16 is placed in a floating state in which neither of the virtual ground lines VG1 or VG2 is connected. In FIG. 2, denoted by '■' is a state in which a cell transistor is electrically connected to a virtual ground line or a bit line, and '□' represents a non-connected state, respectively.

As such, when ROM data is programmed into the cell transistor depending on whether the source of the cell transistor is connected to the virtual ground line, the total capacitance C24 of the bit lines BL0 and BL1 regardless of programming "0" or "1" to the cell transistor. And C25 will have the same value. However, the capacitance of the virtual ground line may vary depending on the program data. However, since the virtual ground line is a full swing signal from logic high to logic low or vice versa, a large or small line capacitance greatly affects the ROM operation speed unlike a small swing bit line. Does not give.

On the other hand, factors affecting the total capacitances C24 and C25 of the bit lines BL0 and BL1 include the capacitance by the bit line length, the capacitance by the contacts CNT connected to the bit line, and the transistors connected to the bit line ( Capacitance due to M1 to M8). Compared to the total capacitances C5 and C6 of the bit lines BL0 and BL1 shown in FIG. 1, the capacitances C24 and C25 are smaller than C5 since they are not affected by the capacitance by the programming metals. Capacitances C24 and C25 are larger than C6 due to the influence of the capacitance caused by the contact CNT connected to the bit line and the capacitance caused by the transistors M1 to M8 connected to the bit line. Here, smaller C24 than C5 means that the bit line is discharged faster. In addition, since C25 is larger than the capacitance C6, the ratio of the coupling capacitance to the adjacent line is small, and thus, the data programmed in the cell transistor can be reduced from being misinterpreted due to the interference of the adjacent line.

As a result, the programmable ROM according to the present invention selectively connects a source of a cell transistor to a virtual ground line according to the ROM data, and is programmed with a faster operating speed than a conventional programmable ROM that selectively connects a source of a cell transistor to a bit line. Misreading of data can be minimized.

Meanwhile, for convenience of description, the programmable ROM shown in FIG. 2 assumes that the ROM data programming is a via programmable ROM in the via process step, but the same result can be obtained in the contact programmable ROM and the metal programmable ROM.

3 is a diagram illustrating a vertical cross section of each cell transistor illustrated in FIG. 2, and a cross section of a virtual ground line connected to a source of the cell transistor and a bit line cross section connected to a drain of the cell transistor, respectively.

Referring to FIG. 3, ROM data may be programmed into a cell transistor by selectively connecting a source to a virtual ground line through a process of forming a contact 30, a metal 1 20, a via 1 10, or a metal 2 40. Can be. That is, the contact 30, the metal 1 (20), the via 1 (10), and the metal 2 (40) are all formed to electrically connect the source of the cell transistor to the virtual ground line, thereby programming "0" in the cell transistor. do. Also, by forming a source of the cell transistor from the virtual ground line by not forming any of the contacts 30, the metal 1 (20), the via 1 (10), or the metal 2 (40), a "1" is programmed in the cell transistor. do.

4 is a circuit diagram illustrating a programmable ROM system according to the present invention, which includes a cell transistor group 50, a precharge unit 60a, a precharge control unit 60b, a virtual ground line selector 80, and a bit line selector ( 70). In FIG. 4, denoted by '■' is a state in which a cell transistor is electrically connected to a virtual ground line or a bit line, and '□' represents a non-connected state, respectively. That is, in the cell transistor group 50, data "0" is programmed in the cell transistors M41 to M46, and data "1" is programmed in the cell transistors M40 and M47, respectively.

Meanwhile, although one cell transistor group 50 is illustrated in FIG. 4, the programmable ROM system may include a plurality of cell transistor groups 50, and the cell group selection signal SEL is selected from among a plurality of cell transistor groups. A signal for selecting one or some cell transistor groups.

The precharge control unit 60b logically combines the cell group selection signal SEL and the precharge signal to generate a precharge control signal. The precharge circuit 60a turns on / off the transistors connected to the virtual ground lines VG0 to VG2 and the bit lines BL0 and BL1 in response to the precharge control signal, thereby providing the virtual ground lines VG0 to VG2. And precharge the bit lines BL0 and BL1.

The virtual ground line selector 80 combines the cell group selection signal SEL and the virtual ground line selection signals AD_VG0, AD_VG1 and AD_VG2 to connect any one of the virtual ground lines VG0 to VG2 to a ground power source. The on / off of the switches SW0 to SW2 is controlled.

The bit line selector 70 selects any one of the bit lines BL0 and BL1 in response to the bit line select signal AD_BL, and transmits data programmed to a cell transistor connected to the selected bit line. )

FIG. 5 shows a timing diagram of signals for controlling the operation of the circuit shown in FIG. 4.

FIG. 6 is a flowchart illustrating a data reading process performed in the programmable ROM system shown in FIG. 4.

4 to 6, the precharge signal is maintained at the 'low' level until the data read request is received from the outside, and the transistors of the precharge unit 60a are turned on by the 'low' level precharge signal. The bit lines BL0 and BL1 and the virtual ground lines VG0 to VG2 are precharged (step 95).

However, as shown in FIG. 5 (a), when the clock signal CLK requesting data reading from the outside occurs, in response thereto, the internal clock signal IN_CLK is enabled as shown in FIG. 5 (b). (Step 100). In response to the internal clock signal IN_CLK, as illustrated in FIGS. 5C and 5D, the word line WL and the precharge signal are sequentially enabled (step 105). Referring to FIG. 4, when the precharge signal is enabled at the 'high' level, the transistors constituting the precharge unit 60a are turned off by the precharge controller 60b and no longer precharged.

As the internal clock signal IN_CLK is enabled, the virtual ground line selection signals AD_VG0 to AD_VG2 are input. Accordingly, the selected virtual ground line is discharged to the ground power level as shown in FIG. 5 (f). . At this time, although not shown, a control signal for controlling the disable of the internal clock signal IN_CLK and the enable of the sense signal in response to the potential is applied to the internal clock signal IN_CLK as shown in FIG. It is discharged in response. That is, the control signal shown in FIG. 5E starts discharge in response to the internal clock signal IN_CLK, and the internal clock signal IN_CLK is disabled in response to the control signal falling below a specific level. The sense signal is enabled (step 115).

As such, when the sense signal is enabled, the selected source signal is selected depending on whether the source of the cell transistor selected by the virtual ground line selection signals AD_VG0 to AD_VG2 and the bit line selection signal AD_BL is connected to the virtual ground line (step 120). The potential of the bit line connected to the drain of the cell transistor is lower than or higher than the reference voltage.

For example, it is assumed that data programmed in the data of the cell transistors M40 and M44 connected to the bit line BL0 is read by the virtual ground line selection signals AD_VG0 to AD_VG2 and the bit line selection signals AD_BL. First, in order to read the data programmed in the cell transistor M40, the switch SW0 is first turned on by the virtual ground line selection signal AD_VG0 so that the virtual ground line VG0 is connected to the ground power source. At this time, since the source is not connected to the virtual ground line, the potential precharged in the bit line connected to the drain of the cell transistor M40 is not discharged to the ground power source and maintains the precharge potential as it is (step 140). On the other hand, in the case of the cell transistor M44, since the source is connected to the virtual ground line, the potential precharged to the bit line connected to the drain of the cell transistor M44 is discharged to the ground power supply through the virtual ground line VG0 (step 125).

After all, depending on whether the source of the cell transistor is connected to the virtual ground line, the potential of the bit line is maintained as it is discharged or precharged, and the potential of the bit line is equal to the reference potential REF as a reference for data discrimination. The comparison is made (step 130). As the potential of the bit line is discharged through the virtual ground line, as shown in FIG. 5 (h), the potential of the bit line is the reference potential as shown in FIG. 5 (g) when the sense signal is enabled. If it is lower than REF, data of "0" is read as shown in FIG. 5 (i) (step 135). On the other hand, when the potential of the bit line is higher than the reference potential REF at the time when the sense signal is enabled, as shown in FIG. Data is read (step 135).

The invention can also be embodied as computer readable code on a computer readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage, and the like, which are also implemented in the form of a carrier wave (for example, transmission over the Internet). It also includes. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

The best embodiments have been disclosed in the drawings and specification above. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the high-speed programmable ROM system according to the present invention selectively connects the source of the cell transistor to the virtual ground line in accordance with the ROM data to be written, so that the capacitance of the bit line does not become excessively large or small. It can be maintained. This makes it possible to increase the operating speed of the programmable ROM while minimizing the misreading of programmed data.

Claims (23)

In a programmable ROM comprising a plurality of programmable memory cells, In the programmable memory cell, Wordline; Bitline; A virtual ground line selectively connected to a ground power source in response to a control signal; And A cell transistor having a gate connected to the word line, a first electrode and a second electrode connected to the bit line, and selectively programmable to a predetermined logic level by selectively connecting the second electrode to the virtual ground line Programmable memory cell comprising a. The method of claim 1, And the cell transistor is an N-type MOS transistor. The method of claim 1, And a switch for selectively connecting the virtual ground line to the ground power source in response to the control signal. The method of claim 1, And the selective connection of the second electrode to the virtual ground line is determined at a contact hole forming step of a manufacturing process. The method of claim 1, And selectively connecting the second electrode to the virtual ground line at a metal line forming step of a manufacturing process. The method of claim 1, And selectively connecting the second electrode to the virtual ground line at a via hole forming step of a manufacturing process. Each of the plurality of memory cells having a gate, a first electrode and a second electrode; Each of a plurality of word lines connected to gates of the plurality of memory cells; Bit lines connected to the first electrodes of the plurality of memory cells, the bit lines being substantially perpendicular to the word lines; And Each of which comprises a plurality of virtual ground lines selectively connected to ground power in response to control signals, the plurality of virtual ground lines disposed substantially perpendicular to the word lines; And a second electrode of each of the plurality of memory cells is selectively connected to the plurality of virtual ground lines to program the plurality of memory cells to a predetermined logic level. The method of claim 7, wherein Each of the memory cells is an N-type MOS transistor. The method of claim 7, wherein And a plurality of switches for selectively connecting the plurality of virtual ground lines to the ground power source in response to each of the control signals. The method of claim 7, wherein And a precharge unit configured to precharge the plurality of virtual ground lines and the plurality of bit lines in response to a precharge signal and a cell group selection signal for selecting a memory cell group. The method of claim 10, A virtual ground line selection unit for selecting one virtual ground line among the virtual ground lines included in the memory cell group in response to the cell group selection signal and the virtual ground line selection signal; And And a bit line selector configured to select one bit line from among the bit lines included in the memory cell group in response to the cell group selection signal and the bit line selection signal. Each of the plurality of memory cells having a gate, a first electrode and a second electrode; Each of a plurality of word lines connected to gates of the plurality of memory cells; Each of the bit lines disposed in a substantially vertical direction with the word lines, wherein the first electrodes of two memory cells adjacent in a horizontal direction of the plurality of memory cells are shared and connected; And Each of which comprises a plurality of virtual ground lines selectively connected to ground power in response to control signals, the plurality of virtual ground lines disposed substantially perpendicular to the word lines; And a second electrode of each of the plurality of memory cells is selectively connected to the plurality of virtual ground lines to program the plurality of memory cells to a predetermined logic level. Each of the plurality of memory cells having a gate, a first electrode and a second electrode; Each of a plurality of word lines connected to gates of the plurality of memory cells; Each of the bit lines disposed in a substantially vertical direction with the word lines, wherein the first electrodes of four memory cells adjacent in the horizontal and vertical directions of the plurality of memory cells are shared and connected; And Each of which comprises a plurality of virtual ground lines selectively connected to ground power in response to control signals, the plurality of virtual ground lines disposed substantially perpendicular to the word lines; And a second electrode of each of the plurality of memory cells is selectively connected to the plurality of virtual ground lines to program the plurality of memory cells to a predetermined logic level. In a programmable ROM comprising a plurality of cell transistors having a gate, a first electrode and a second electrode, the method of writing binary data in the cell transistors, Coupling the gate and the first electrode to a word line and a bit line, respectively; And And selectively connecting the second electrode to a virtual ground line selectively connected to the ground power source according to the binary data to which the second electrode is to be recorded. The method of claim 14, Connecting the second electrode to the virtual ground line to write binary data " 0 " to the cell transistor, and floating the second electrode from the virtual ground line to write binary data " 1 ". A data recording method characterized by the above-mentioned. The method of claim 14, And selectively connecting the second electrode to the virtual ground line at the step of forming a contact hole during the manufacturing process. The method of claim 14, The selective connection of the second electrode to the virtual ground line is determined in the metal line forming step of the manufacturing process. The method of claim 14, The selective connection of the second electrode to the virtual ground line is determined in the via hole forming step of the manufacturing process. A recording medium in which the data recording method of claim 14 is recorded in a program code executable on a computer. delete delete delete delete