KR100467367B1 - Column Redundancy Circuit in Semiconductor Memory Device - Google Patents

Abstract

The present invention allows the redundancy cell array to be controlled by signals having even and odd information, respectively, so that each redundancy bit line is controlled by a signal having even information and is replaced by an even cell. The goal is to increase the flexibility of redundancy bit lines by replacing them.

In order to achieve the above object, the column redundancy circuit of the semiconductor memory device of the present invention is a semiconductor memory device for outputting data using a prefetch method, comprising: an odd normal cell array, an odd redundancy cell array, and an odd redundancy cell array. A cardinal block including a cardinality redundancy sense amplifier for amplifying the data read out of the cell; An odd redundancy column select signal generation circuit for generating a redundancy column select signal to control the odd redundancy sense amplifier; An even block including an even normal cell array, an even redundancy cell array, and an even redundancy sense amplifier for amplifying data read from cells in the even redundancy cell array; And an excellent redundancy column selection signal generating circuit unit generating a redundancy column selection signal to control the even redundancy sense amplifier, wherein when an error occurs in a cell in the odd-normal cell array, the cell in the even redundancy cell array is configured to perform the redundancy column selection signal generation. To replace the function of the cells in the radix normal cell array.

Description

Column redundancy circuit in semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a column redundancy circuit of a semiconductor memory device, and is applicable to a semiconductor memory device to which a prefetch scheme for reading data such as 2 times, 4 times, etc. from a cell is read out.

In general, a semiconductor memory device is provided in addition to a normal cell array so that any cell in the redundant cell array can take over the above function if any cell in the normal cell array becomes unable to perform normal operation for some reason. A separate redundancy cell array is provided.

1 is an overall block diagram of a column redundancy circuit according to the prior art.

The entire block structure for column redundancy is divided into odd and even blocks when using the prefetch method, and each block includes a number of word lines, a plurality of bit lines / bit bar lines, and a data storage location. In the normal cell array (1) and the normal cell array (1) in which data stored in a plurality of cells connected to the word line is activated, data can be transferred to the bit line / bit bar line and the data is normally stored. Redundancy cell array (2), which replaces using a fuse program when a cell fails, data of cells in normal cell array (1) is read and data of multiple cells connected to word lines Sense amplifiers (3), cells in redundancy cell arrays (2) for amplifying and latching weak signals when loaded on the bit lines Redundancy sense amplifier 4, sense amplifier 3 or redundancy sense amplifier 4 for amplifying and latching a weak signal when the data of a plurality of cells connected to a word line is loaded on a plurality of bit lines. The signal amplified by the transistor in the sense amplifier 3 or 4 is turned on by the column selection signal YS or the redundancy column selection signal RYS transmitted through the column selection line 5 or the redundancy column selection line 6. The data loaded on the sense amplifier input / output line SIO, in which the data is selectively loaded among the plurality of sense amplifiers 3 or the redundant sense amplifiers 4, and at the time of read READ, is switched. 12) the second sense amplifier 11 and the column selection signal YS for writing the data to the cell when the WRITE is second amplified and written to the cell. Column selection It consists of a call generating circuit 9 and a redundancy column select the redundancy column selection signal for generating a signal (RYS) generating circuit 10.

DDR SDRAM, on the other hand, uses a 2-bit prefetch scheme, which requires twice as much data access from the cell as outgoing data. To do this, two column addresses must be activated regardless of address 0, which is the lowest address among the column addresses, and separate sense amplifier I / O lines, local I / O lines, and secondary sense amplifiers are used to access the data of the two column addresses. It is necessary and thus divided into even block and odd block as shown in FIG.

In addition, the column redundancy circuit is also configured separately so that if an error occurs in the even block, the redundancy cell existing in the even block must be used. If an error occurs in the even block, the redundancy cell existing in the odd block must be replaced. If the error occurred in the odd block is replaced with the redundancy cell of the even block, two column selection signals are activated in the odd block, causing data collision in the sense amplifier input / output line, causing a malfunction. Therefore, the column fuse comparison circuit allocates each of even and odd blocks separately. Since the even and odd numbers are already divided into circuit assignments, the column address 0 is unnecessary in this circuit and is not compared.

2 is a circuit diagram of a peripheral circuit of a sense amplifier according to the prior art.

Reference numeral 4 is a sense amplifier for amplifying and latching a bit line / bit bar line signal, and the NMOS transistors nm1 and nm2 connect the amplified signal to a sense amplifier input / output line (SIO / SIOB) through control of a column select signal. give.

3 is a circuit diagram of a redundancy column select signal generation according to the prior art.

The redundancy column select signal generation circuit 10 receives a column fuse enable signal YFEN and enables a fuse enable unit ENABLE FUSE for enabling the column fuse, and the respective column addresses AY <1>, ... And AY <n>) for outputting a redundant column enable signal RYEN by logically multiplying the outputs of a plurality of fuses and the output of the fuse enable unit by the outputs of the plurality of fuses. When AND gate 1 (AND1) and redundancy column select signal (RYS) are activated, the outputs of AND gate 2 (AND2) and AND gate 2 for ANDing the output of AND gate 1 with the BYPREP signal for determining the pulse width and timing It consists of a driver DRV1 for driving.

4 is a timing diagram of the redundancy column select signal generation circuit of FIG. 3.

The DDR SDRAM receives a command and an address in synchronization with the clock signal CLK. Here, the read command will be described as an example. As shown in FIG. 4, when the read command and the address are input, the fuse unit of FIG. 3 compares the information stored in the fuse unit, and when the address matches the information in the fuse unit, the output of the fuse unit becomes “H” and all addresses match. When the "H" state is reached, the redundancy column enable signal that is the output of the AND gate 1 becomes the "H" state. In this case, since the redundancy column selection signal RYS should be a pulse signal, the BYPREP signal, which is a signal for controlling the redundancy column selection signal, is logically multiplied with the redundancy column enable signal and is enabled through the driver.

However, in the related art, when the use of column redundancy is an error occurring in the even block, a good redundancy cell is required, and in the case of an error occurring in the odd block, a restriction to be replaced by the odd redundancy cell is followed, resulting in low repair efficiency. In other words, when a large number of errors occur in the odd block and a small number of errors occur in the even block, the redundancy cell is insufficient in the odd block and the redundancy cell remains in the even block. Due to this lack, there was a problem that the repair efficiency is extremely deteriorated.

In order to solve the above problems, the present invention allows the redundancy cell arrays to be controlled by signals having even and odd information, so that each redundancy bit line is controlled by a signal having even information and is replaced by even cells. Under the control of the signal, the purpose is to increase the flexibility of the redundancy bit line by replacing the odd cell.

1 is an overall block diagram of a column redundancy circuit according to the prior art;

2 is a circuit diagram of a peripheral sense amplifier according to the prior art;

3 is a redundancy column selection signal generation circuit diagram according to the prior art;

4 is a timing diagram of a redundancy column select signal generation circuit according to the prior art;

5 is an overall block diagram of a column redundancy circuit according to the present invention;

6 is a circuit diagram of a peripheral sense amplifier according to the present invention;

7 is a circuit diagram of redundancy column selection signal generation according to the present invention;

8 is a timing diagram of a redundancy column select signal generation circuit according to the present invention;

<Explanation of symbols for the main parts of the drawings>

1: normal cell array 2: redundancy cell array

3: sense amplifier 4: redundancy sense amplifier

5: column select line 6: redundancy column select line

7: sense amplifier I / O line 8: local I / O line

9: column select signal generator 10: redundancy column select signal generator

11: secondary sense amplifier 12: switch

In order to achieve the above object, the column redundancy circuit of the semiconductor memory device of the present invention is a semiconductor memory device for outputting data using a prefetch method, comprising: an odd normal cell array, an odd redundancy cell array, and an odd redundancy cell array. A cardinal block including a cardinality redundancy sense amplifier for amplifying the data read out of the cell; An odd redundancy column select signal generation circuit for generating a redundancy column select signal to control the odd redundancy sense amplifier; An even block including an even normal cell array, an even redundancy cell array, and an even redundancy sense amplifier for amplifying data read from cells in the even redundancy cell array; And an excellent redundancy column selection signal generating circuit unit generating a redundancy column selection signal to control the even redundancy sense amplifier, wherein when an error occurs in a cell in the odd-normal cell array, the cell in the even redundancy cell array is configured to perform the redundancy column selection signal generation. To replace the function of the cells in the radix normal cell array.

Further, while the sense amplifier input / output line of the even block and the sense amplifier input / output line of the odd block are connected in parallel to the even redundancy sense amplifier of the present invention, the superior redundancy sense amplifier and the sense amplifier input / output line of the even block are connected. A switching unit which is controlled by the even redundancy column selection signal output from the even redundancy column selection signal generation circuit unit is connected, and between the even redundancy sense amplifier and the sense amplifier input / output line of the odd block from the odd redundancy column selection signal generation circuit unit. The switching unit under the control of the output odd redundancy column selection signal is connected.

The even redundancy column select signal generation circuit unit of the present invention may include a column fuse enable signal, a plurality of column addresses, an even redundancy column enable signal output from the odd redundancy column select signal generation circuit unit, and the odd redundancy column select signal. The method may further include receiving the column address enable signal BYPREP for determining the pulse width and timing to generate the even redundancy column selection signal and the odd redundancy column selection signal.

The odd redundancy column select signal generation circuit unit of the present invention may include: an even fuse enable unit configured to receive the column fuse enable signal and enable the even column fuse; A plurality of fuses configured to receive and compare the column fuse enable signal and the plurality of column addresses in parallel; An odd fuse enable unit configured to receive the column fuse enable signal and enable an odd column fuse; A first logic element for performing an AND operation on the output of the even fuse enable unit and the outputs of the plurality of fuse units; A second logic element for logically multiplying outputs of the plurality of fuses by an output of the odd fuse enable part; A third logic element for logically multiplying the output of the first logic element with a column address enable signal that determines pulse width and timing when activating the even redundancy column select signal; A fourth logic element for logically multiplying an output of a second logic element with the column address enable signal; And a fifth logic element for logical sum of the even redundancy column enable signal output from the odd redundancy column select signal generation circuit and the output of the first logic element.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

5 is an overall block diagram of a column redundancy circuit according to the present invention.

The basic components of the entire block configuration for column redundancy are the same as those in FIG. 1, except that the redundancy sense amplifier 4, the redundancy sense input / output line 7 connected to the redundancy sense amplifier 4, and the redundancy column select signal ( RYS) and the detailed configuration of the fuse unit in the redundancy column selection signal generation circuit for generating the redundancy column selection signal are different.

6 is a circuit diagram of a peripheral sense amplifier according to the present invention.

The sense amplifier and the peripheral part of the present invention are connected to the redundancy sense amplifier and the radix sense amplifier input and output lines (SIO_O, SIOB_O) and the excellent sense amplifier input and output lines (SIO_E, SIOB_E) in parallel, between the parallel connection point and the odd sense amplifier input and output lines The NMOS transistors mn1 and mn2 under the control of the redundancy column select signal RYS_O are controlled by the MOS transistors mn3 and mn4 under the control of the even redundancy column select signal RYS_E between the parallel connection point and the even sense amplifier input / output line. Is connected.

Therefore, when the even redundancy column select signal RYS_E is activated, the NMOS transistors mn1 and mn2 are turned on, and data of the cell is loaded into the even sense amplifier input / output lines SIO_E and SIOB_E, and the odd redundancy column select signal RYS_O is performed. NMOS transistors mn3 and mn4 are turned on to load cell data to the odd sense amplifier input / output lines SIO_O and SIOB_O.

That is, when a large number of errors occur in the odd block and a small amount of errors occur in the even block, the odd block error is replaced by the redundancy cells of the even block, and the odd error address information is sent to the even redundancy column selection signal generation circuit 10. When input, the odd redundancy column select signal RYS_O of the redundancy sense amplifier RSA is activated, and the cell data is loaded on the odd sense amplifier input / output lines SIO_O and SIOB_O. Therefore, it is possible to replace the cells of the even redundancy block when an error occurs in the cells of the even block without a data collision, which is a problem of the prior art, or the cells of the even redundancy block when an error occurs in the cells of the even block.

7 is an excellent redundancy column select signal generation circuit diagram according to the present invention.

The even redundancy column select signal generation circuit 10 of the present invention receives the column fuse enable signal YFEN and an even fuse enable unit for enabling the even column fuse, and the column fuse enable signal, respectively. Radix column fuses receiving a plurality of fuse units (ADDRESS FUSE) and a column fuse enable signal (YFEN) for receiving and comparing the column addresses (AY <1>, ...., AY <n>) in parallel First AND gate (AND1) for outputting even redundancy column enable signal (RYEN_E) by logically multiplying the output of the even fuse enable section and the output of the plurality of fuse sections by ENABLE FUSE_ODD for enabling the And a second AND gate AND2 for outputting the odd redundancy column enable signal RYEN_O by logically multiplying an output of the plurality of fuses by an output of the odd fuse enable part, and an odd redundancy column select signal generation circuit. OR gate for outputting the redundancy column enable signal RYEN by logical sum of the even redundancy column enable signal RYEN_E and the output of the first AND gate, which are output from the OR, and the output and redundancy column of the first AND gate. A third AND gate AND3 for logically multiplying the column address enable signal BYPREP that determines the pulse width and timing when activating the signal, a first driver DRV1 for driving the output of the third AND gate, and Driving the output of the fourth and gate AND4 and the fourth and gate to logically multiply the output of the two-and-gate and the column address enable signal BYPREP, which determines the pulse width and timing when activating the redundant column select signal. It consists of a second driver DRV1 for.

Here, the redundancy column enable signal RYEN output from the even redundancy column select signal generation circuit 10 and input to the even column select signal generation circuit 9 is output from the odd redundancy column select signal generation circuit 10-1. The odd redundancy column enable signal RYEN_E and the output of the first AND gate are logically summed, so that the odd redundancy column select signal generation circuit is symmetrically applied thereto.

That is, the redundancy column enable signal RYEN output from the odd redundancy column select signal generation circuit 10-1 and input to the odd column select signal generation circuit 9-1 is an excellent redundancy column select signal generation circuit 10. The odd redundancy column enable signal RYEN_O and the first and gate outputs in the odd redundancy column select signal generation circuit 10-1 outputted from the result are logical sums.

8 is a timing diagram of the redundancy column select signal generation circuit of FIG. 7.

When the command and the address are input in synchronization with the clock, the conventional address is compared with the conventional address. Since there is one enable fuse unit, the fuse of the even enable fuse unit is cut and used to replace the error address of the even block. When replacing the address of the block, cut the fuse of the radix enable fuse.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains, and the foregoing embodiments and the accompanying drawings. It is not limited to.

According to the configuration as described above, the present invention can improve the flexibility of the column redundancy circuit, and also has an advantageous effect to improve the yield in mass production.

Claims (4)

delete In a semiconductor memory device for outputting data using a prefetch method, A radix block comprising an radix normal cell array, an radix redundancy cell array, and an radix redundancy sense amplifier for amplifying data read from cells in the radix redundancy cell array; An odd redundancy column select signal generation circuit for generating a redundancy column select signal to control the odd redundancy sense amplifier; An even block including an even normal cell array, an even redundancy cell array, and an even redundancy sense amplifier for amplifying data read from cells in the even redundancy cell array; And A superior redundancy column selection signal generation circuit unit configured to generate a redundancy column selection signal to control the even redundancy sense amplifier, If an error occurs in a cell in the odd normal cell array, the cell in the even redundancy cell array replaces the function of the cell in the odd normal cell array, and in the even redundancy sense amplifier, The even output from the even redundancy column selection signal generation circuit unit between the good redundancy sense amplifier and the good sense block input / output line of the even block while the sense amplifier input / output line of the even block and the odd amplifier input / output line of the odd block are connected in parallel. A switching unit under the control of the redundancy column selection signal is connected, and a switching under the control of the odd redundancy column selection signal output from the odd redundancy column selection signal generating circuit unit between the excellent redundancy sense amplifier and the sense amplifier input / output lines of the odd block. And a column redundancy circuit of the semiconductor memory device, characterized in that additionally connected. The circuit of claim 2, wherein the even redundancy column select signal generation circuit unit comprises: A column fuse enable signal, a plurality of column addresses, an even redundancy column enable signal output from the odd redundancy column select signal generating circuit unit, and a column address enable for determining pulse width and timing when activating the odd redundancy column select signal. And a signal redundancy column selection signal and an odd redundancy column selection signal generated by receiving a signal BYPREP. The method of claim 3, wherein the odd redundancy column select signal generation circuit portion, An even fuse enable unit configured to receive the column fuse enable signal and enable the even column fuse; A plurality of fuses configured to receive and compare the column fuse enable signal and the plurality of column addresses in parallel; An odd fuse enable unit configured to receive the column fuse enable signal and enable an odd column fuse; A first logic element for performing an AND operation on the output of the even fuse enable unit and the outputs of the plurality of fuse units; A second logic element for logically multiplying outputs of the plurality of fuses by an output of the odd fuse enable part; A third logic element for logically multiplying the output of the first logic element with a column address enable signal that determines pulse width and timing when activating the even redundancy column select signal; A fourth logic element for logically multiplying an output of a second logic element with the column address enable signal; And A fifth logic element for logical sum of the even redundancy column enable signal output from the odd redundancy column select signal generation circuit and the output of the first logic element; And a column redundancy circuit of the semiconductor memory device.