KR100462648B1 - Automatic Shape Cognition Apparatus And Method For System Board - Google Patents

Abstract

The present invention relates to an apparatus and method for automatically recognizing a shape of a system board to perform shape management by automatically recognizing shape information of a system board using a boundary scan path of a board physically mounted in the system.

According to the automatic shape recognition apparatus and method of the system board of the present invention, the basic information for system configuration management is provided in a bottom-up that automatically recognizes the actual physically mounted function board and reports it to the upper main board. This enables more efficient system configuration management than top-down and facilitates software implementation of configuration management and maintenance.

In addition, the present invention by using the boundary scan path for component assembly test of the functional board mounted in the system to automatically recognize the shape information including the position information of the board in the system to perform system configuration management, Boundary scan paths can be used not only for component assembly testing but also for system configuration management.

Description

Automatic Shape Cognition Apparatus And Method For System Board

The present invention relates to shape recognition of a board in a system, and more particularly, to a shape management system by automatically recognizing shape information of a system board using a boundary scan path of a board physically mounted in the system. An automatic shape recognition apparatus and method.

In general, data processing systems such as exchanges, gateways, and the like are used as rack-shaped racks, and in recent years, have a shape that can be used in modern and general office installations that are well suited to the surrounding environment. Shelf is configured, and the shelf is equipped with a main board that performs overall management of the system, such as operation, maintenance, maintenance, and configuration management in the system, and a function board that performs each unique function under the management of the main board. Slots and backplane boards are provided for mounting and supporting the boards.

In the case of such a system, the shape management is performed, which is managed in a graphic form by using the position information and the shape information of the functional board physically mounted in the system transmitted from the backplane board in the system.

Here, the location information refers to the physical location where the functional board is mounted in the system, which can be divided into the rack, shelf, backplane board, slot from the top to the bottom, and the shape information is physical Meaning the name of the functional board to be mounted, such position information and shape information is composed of a combination of '0' and '1' which is a logical value generated by the backplane board.

Referring to the above-described system configuration management in more detail with reference to the accompanying drawings, Figure 1 is a view showing a configuration for recognizing position information and shape information for any functional board mounted in the system, the functional board is Mounted on the backplane board via the edge connector 15, the central processing unit 11, the programming unit 12, the jumper stick / cable connection 13, and a number of Joint Test Action Group (JTAG) chips 14- 1, 14-2, 14-3, ..., 14-n) and the edge connector 15.

The central processing unit 11 recognizes the position information and the shape information of the function board where it is located through the programming unit 12 and reports it to the upper main board through the internal connection communication path, and the programming unit 12 is the backplane board. The position information and shape information transmitted from the edge connector 15 to the central processing unit 11 is transmitted.

The jumper stick / cable connection part 13 has JTAG port signals such as TCK (Test ClocK), TMS (Test Mode Signal), TDI (Test Data Input), TRST (Test ReSeT), and TDO (Test Data Output) signals. Each JTAG chip 14-1, 14-2, 14-3, ..., 14-n is connected in a Boundary Scan Chain to transmit the JTAG port signal to the next JTAG chip. Boundary scan tests are performed to test the assembly of parts.

The configuration management operation using the positional information and the shape information of any functional board mounted in the conventional system having such a configuration will be described below.

First, the backplane board assembled into the shelf of the system rack is a logical value 'to indicate where the functional board is physically mounted in the system and the board name when any functional board is mounted through the edge connector 15. Position information and shape information consisting of a combination of 0 'and' 1 'are generated by using a header of a switch or jumper stick, and then transferred to a function board.

Then, the programming unit 12 of the function board mounted on the corresponding backplane board receives the position information and the shape information transmitted from the backplane board through the edge connector 15 and transmits it to the central processing unit 11.

At this time, the central processing unit 11 recognizes the board position information and the shape information transmitted through the programming unit 12 using the firmware, and then transfers the corresponding board position information and the shape information to the main board through the internal connection communication path. The main board performs the shape management of the system based on the board position information and the shape information reported from each functional board.

As described above, in performing the shape management in the conventional system, the central processing unit of the functional board is mounted on another backplane board to transfer the board position information and the shape information to the main board to perform the shape management. The communication path for information transmission in some form must be connected between the board and the functional board, and additional information is required for this information transmission, but there is no stabilized and standardized technology in this regard and it is different from system to system. There is a problem of low reliability.

The present invention has been made to solve the above-mentioned problems, and an object thereof is to automatically obtain shape information including position information of boards in a system by using a boundary scan path for component assembly test of functional boards mounted in the system. An automatic shape recognition apparatus and method for a system board can be recognized.

Another object of the present invention is to provide top-down by automatically identifying basic information for system configuration management in a physically mounted functional board and reporting it to the upper main board. Compared to this, the system configuration management can be performed more efficiently, and the software for configuration management and maintenance can be easily implemented.

1 is a diagram showing a configuration for recognizing positional information and shape information for any functional board mounted in a conventional system.

2 shows an apparatus for automatic shape recognition of a system board according to the invention.

Explanation of symbols on the main parts of the drawings

21 memory unit 22 central processing unit

23: boundary scan path detection unit 23-1: TAP signal control unit

23-2: ID code register analyzer 23-3: location information detector

23-4: Shape information analysis / transmitter 24-1 ~ 24-n: JTAG chip

25: edge connector

A feature of the present invention for achieving the above object is to analyze and transmit the ID code register value of the board in the system, and to include the position information received from the backplane board in the determined board shape information to the upper main board A boundary scan path detection unit for reporting; A central processing unit which compares the ID code register analysis information received from the boundary scan path detection unit with previously stored shape information and transfers the determined board shape information to the boundary scan path detection unit as a result; A firmware for driving the central processing unit is fused, and to provide an automatic shape recognition apparatus of a system board including a memory unit for storing the shape information predefined for the board in the system.

The boundary scan path detector may control the TAP signal to analyze the ID code register value of the JTAG chip obtained through the bound scan path, and transmit the ID code register analysis information to the central processing unit.

The boundary scan path detection unit may further include: a TAP signal controller configured to control a TAP signal provided to a JTAG chip connected through a boundary scan chain to transfer a TDO signal output through a corresponding boundary scan path; An ID code register analyzer for analyzing and transmitting an ID code register value included in the TDO signal received from the TAP signal controller; A position information detector for transferring board position information transmitted from the backplane board through a edge connector in the form of a logical value; The ID connector register information transmitted by the ID code register analysis unit is transmitted to the central processing unit, and the board position information transmitted from the position information sensing unit is included in the board shape information determined by the central processing unit to provide the edge connector. It characterized in that it comprises a shape information analysis / transmission unit for reporting to the upper main board through.

At this time, the JTAG chip is connected to the boundary scan chain and performs a boundary scan test according to the TAP signal provided by the TAP signal controller, and as a result, the ID code register value stored in the internal ID code register is converted into a TDO signal. It is characterized by including in the output.

Another aspect of the present invention includes the steps of fusing the driving firmware in the memory of the board in the system, and storing the predetermined board shape information; When a board is mounted on the backplane board of the system, generating board position information from the backplane board and transmitting the board position information through an edge connector; Analyzing the ID code register value output through the boundary scan path in the board mounted on the system and confirming the shape information of the board mounted in the system by comparing with the board shape information previously stored in the memory; The present invention provides an automatic shape recognition method of a system board comprising the step of including board position information received from the backplane board in the determined board shape information and reporting to the upper main board through the edge connector.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the present invention, in performing system configuration management, a boundary scan path consisting of a TAP (Test Access Port) signal is detected to automatically recognize the shape of a board mounted in the system. By using the TDO signal output as the result of the boundary scan test, it analyzes the ID code register value included in the TDO signal and compares the analysis result with the stored shape information to compare the shape information of the actual board. In addition, by including the position information transmitted from the backplane board in the shape information obtained above to report to the upper main board to automatically recognize the shape of the board in the system.

Here, the boundary scan test will be described. This is due to the recent miniaturization of the system, which is an assembly of a printed board assembly (PBA) in which devices having small size, tight pin spacing, and difficult probing are assembled on a printed circuit board As a new alternative to state testing, the general standards for this include IEEE Standard 1149.1-1990 (includes IEEE Std 1149.1a-1993 Test Access Port and Boundary Scan Architecture) and IEEE Standard 1149.1b-1994 (supplement to IEEE std). 1149.1-1990 and IEEE Std 1149.1a-1993, supplement to IEEE Std 1149.1-1990, IEEE Standard Test Access Port and Boundary Scan Architecture.

In addition, the boundary scan test does not affect the inherent functions of the main board and the function board during system operation, and can be applied from the device level test to the board level and the system level. When manufacturing a device, a resistor called a boundary scan cell must be implemented between the device's input and output pads and the core logic.

At this time, the JTAG port signals (TCK, TMS, TDI, TDO, TRST) are used to control the boundary scan cell, and the TAP signal is controlled by the TCK, TMS, and TRST signals in the TAP signal controller to test the test data (Test Pattern). ) Is applied to the JTAG chip, the infrastructure test, identity test, test reset test, TRST test, interconnection test, and cluster test. After the test is executed with various commands such as and an external test, the corresponding test result is output as a TDO signal.

By capturing and analyzing the TDO signal that is the result of the boundary test at the jumper stick / cable connection, the assembly state of the device under test, that is, stuck-at fault, bridge, and open , Short, etc. will be known.

On the other hand, the apparatus for automatic shape recognition of the system board according to the present invention, as shown in Figure 2, the memory unit 21, the central processing unit 22, the boundary scan path detection unit 23 and , A plurality of JTAG chips 24-1, 24-2,..., 24-n and edge connectors 25.

The memory unit 21 fuses firmware for driving the central processing unit 22 and stores shape information formed by a combination of logical values '0' and '1' defined for each board in the system.

The central processing unit 22 is driven by firmware fused to the memory unit 21 to perform various functions of the board, and the JTAG chips 24-1 and 24- obtained through the boundary scan path detection unit 23. After comparing the ID code register analysis information of 2, ..., 24-n with the board shape information stored in the memory unit 21, the board shape information determined as a result of the comparison is transferred to the boundary scan path detection unit 23. .

The boundary scan path detection unit 23 analyzes the ID code register values of the JTAG chips 24-1, 24-2, ..., 24-n obtained by controlling the TAP signal, and centralizes the position information received from the backplane board. It is included in the board shape information determined by the processing unit 22 and reported to the upper main board through the edge connector 25. The detailed configuration for this is explained by the TAP signal control unit 23-1 and the ID code register. It has the structure containing the analysis part 23-2, the positional information detection part 23-3, and the shape information analysis / transmitting part 23-4.

The TAP signal controller 23-1 controls the TAP signals TCK, TMS, TRST, and TDI provided to the JTAG chips 24-1, 24-2, ..., 24-n connected by the boundary scan chain. The TDO signals 1_TDO, 2_TDO, ..., n_TDO output through the boundary scan path are transmitted to the ID code register analyzer 23-2.

The ID code register analyzer 23-2 analyzes the ID code register value included in the TDO signal received from the TAP signal controller 23-1 and delivers the value to the shape information analyzer / transmitter 23-4.

The position information detecting unit 23-3 transfers the board position information transmitted in the form of logical values '0' and '1' from the backplane board through the edge connector 25 to the shape information analyzing / transmitting unit 23-4. Deliver it.

The shape information analysis / transmitter 23-4 centralizes ID code register analysis information of the JTAG chips 24-1, 24-2, ..., 24-n analyzed by the ID code register analyzer 23-2. The board position information transmitted to the processing unit 22 and the board position information transmitted from the position information detecting unit 23-3 are included in the board shape information determined by the corresponding central processing unit 22, and the upper position is transferred through the edge connector 25. Report to the main board.

Each JTAG chip 24-1, 24-2,..., 24-n is connected in a boundary scan chain to perform a boundary scan test according to the TAP signal provided by the TAP signal controller 23-1. As a result, the ID code register value stored in the internal ID code register is included in the TDO signal and output.

Here, the ID code register is specified in IEEE 1149.1-1990, and when 32 bits are described in detail, the bit number 0 is fixed as '1' as a LSB (Least Significant Bit) bit, and bit 1 is set. Bits 11 through 11 are manufacturer identity identifiers, bits 12 through 27 (16 bits) are part number identifiers, and bits 28 through 31 (4 bits) are versions ( version) identifier, where bit 31 becomes the Most Significant Bit (MSB) bit.

The edge connector 25 is a portion where any board is mounted on a backplane board assembled to the shelf of the system rack, through which the main board and the functional boards are mounted.

The automatic shape recognition operation of the board in the system by the automatic shape recognition device of the system board having the above-described configuration will be described in detail as follows.

First, in order to automatically recognize a board in a system, the firmware for driving the CPU 22 with an ASCII code value must be fused in the memory 21. It should store shape information consisting of a combination of '0' and '1'.

Here, the shape information refers to the shape name of the board in the system. For example, assuming that there are five boards such as 'a', 'me', 'da', 'la', and 'ma' In the memory section of the board, binary (0, 1) information, which is converted into respective ASCII code values through an address and a control signal, is stored as shape information.

In this state, if any board is mounted on the backplane board through the edge connector 25, the backplane board generates position information by a combination of logical values '0' and '1' and transfers it to the corresponding edge connector 25. In this case, the position information detecting unit 23-3 of the boundary scan path detection unit 23 implemented in the board mounted on the edge connector 25 is the board position information transmitted from the backplane board through the edge connector 25. Is transmitted to the shape information analysis / transmitter 23-4.

The TAP signal controller 23-1 of the boundary scan path detection unit 23 controls the TCK, TMS, TRST, and TDI signals, which are TAP signals, and outputs the TDO signals 1_TDO, 2_TDO, and the like through the corresponding boundary scan path. ..., n_TDO is transmitted to the ID code register analyzer 23-2, where the ID code register analyzer 23-2 is an ID code included in the TDO signal received from the TAP signal controller 23-1. The register value is analyzed and transmitted to the shape information analysis / transmitter 23-4.

Accordingly, the ID code register analysis information of the JTAG chips 24-1, 24-2, ..., 24-n analyzed by the ID code register analyzer 23-2 in the shape information analyzer / transmitter 23-4. That is, ID code register analysis information (11 bits of JTAG chip # 1-> JTAG chip # 2 of the JTAG chip # 1, including information that is sequentially connected to the JTAG chips 24-1, 24-2, ..., 24-n) is included. 11 bits-> 11 bits of JTAG chip # 3->…-> 11 bits of JTAG chip #n are sequentially transmitted to the central processing unit 22, the central processing unit 22 is the shape information By transmitting the request signal to the memory unit 21, the board shape information defined in the corresponding memory unit 21 is received through the shape information response signal.

Thereafter, the central processing unit 22 receives the IDs of the JTAG chips 24-1, 24-2, ..., 24-n obtained through the shape information analysis / transmitting unit 23-4 of the boundary scan path detection unit 23. By comparing the code register analysis information with the board shape information previously stored in the memory unit 21, the shape information of the currently mounted board is determined and transmitted to the boundary scan path detection unit 23.

Then, the shape information analyzing / transmitting unit 23-4 of the boundary scan path detection unit 23 determines the board position information received from the position information detecting unit 23-3 by the central processing unit 22. It is included in the information and reported to the upper main board through the edge connector 25, wherein the shape information including the board position information reported to the main board is any position in the system (i.e., rack, shelf, slot,…). Shape information, including board locations (i.e. racks, shelves, slots, ...) reported from functional boards mounted on the main board, in which the main board is reported from each of the lower functional boards physically mounted in the system as such. According to the shape information including the position information, the corresponding system shape management is performed.

For example, suppose five boards are mounted in the system, 'A', 'I', 'D', 'D', 'D', and the JTAG chip connection order of each board is as follows. 'Go' board is' JTAG chip # 1-> JTAG chip # 2-> JTAG chip # 4 ',' I 'board is' JTAG chip # 1-> JTAG chip # 2-> JTAG chip # 4- > In order of JTAG chip # 2, 'D' board is in order of 'JTAG chip # 2-> JTAG chip # 3', 'La' board is' JTAG chip 1 ', and' M 'board is' JTAG Assuming that the chip is connected in the order of chip # 1-> JTAG chip # 2-> JTAG chip # 4-> JTAG chip # 2-> JTAG chip # 5 ', the shape information of each board is determined by the ID code register analyzer ( The board shape information determined by comparing the ID code register analysis information including 11-bit information and JTAG chip connection information of each JTAG chip obtained through 23-2) with the board shape information stored in the memory unit 21 is compared. The board position obtained through the position information detector 23-3. Information contained by the system is accomplished automatically by the configuration management report to a higher main board through the edge connector 25.

Here, the 11-bit information of the JTAG chip means the ID code register value of each JTAG chip, which means that the values to which 'LOW / GND' and 'HIGH / VCC' are applied to the register are TAP signals. 11 bits of binary information (0 or 1) are obtained through the controller 23-1. If the 11 bits of the JTAG chip # 1 are '01011101010', the 11 bits of the JTAG chip # 2 is '11010101110'. If the 11-bit information of JTAG chip # 3 is '01010111111', the 11-bit information of JTAG chip # 4 is '11011101111' and the 11-bit information of JTAG chip # 5 is '01010101011'. ID code register analysis information is' 01011101010/11010101110/11011101111 ',' I 'board ID code register analysis information is' 01011101010/11010101110/11011101111/11010101110', 'C' ID code register analysis information is' 11010101110/01010111111 ID code register analysis information of ',' LA board is '01011101010', ID code of 'Do' board Register analysis information is a "01011101010/11010101110/11011101111/11010101110/01010101011 ', this ID code registers the same board shape information and analysis information, it is possible is stored in the memory of each board.

Therefore, in the present invention, by comparing the ID code register analysis information of the board in the system with the board shape information stored in the memory unit, the shape information of the actual board is recognized, and the board mounted on the backplane board in the system is physical / electrical. As it is connected to 'GND / VCC', the board position information obtained as the binary information (0 or 1) through the position information detecting unit 23-3 is included in the board shape information obtained above and reported to the upper main board. By doing so, it is possible to automatically recognize which board is mounted at each position in the system.

On the other hand, the embodiment according to the present invention is not limited to the above, it can be carried out by various alternatives, modifications and changes within the scope apparent to those skilled in the art with respect to the present invention.

As described above, according to the automatic shape recognition apparatus and method of the system board described in the present invention, the bottom-up (bottom-) to automatically recognize the basic information for the system configuration management in the actual physically mounted function board to the upper main board up), it is possible to perform system configuration management more efficiently than top-down.

In addition, the present invention facilitates a software implementation of shape management and maintenance by performing bottom-up shape management, in which the shape information including the board position information is reported from the functional board to the upper main board.

Furthermore, the present invention automatically recognizes the shape information including the position information of the board in the system using the boundary scan path for the component assembly test of the functional board mounted in the system to perform system configuration management. Boundary scan paths can be used not only for component assembly testing but also for system configuration management.

Claims (5)

A boundary scan path detection unit for analyzing and transmitting an ID code register value of a board in the system and including the position information received from the backplane board in the determined board shape information and reporting the same to the upper main board; A central processing unit which compares the ID code register analysis information received from the boundary scan path detection unit with previously stored shape information and transfers the determined board shape information to the boundary scan path detection unit as a result; And a memory unit for fusing firmware for driving the central processing unit and storing shape information defined for the board in the system. The method of claim 1, The boundary scan path detection unit analyzes the ID code register value of the JTAG chip obtained through the boundary scan path by controlling the TAP signal, and transmits the ID code register analysis information to the central processing unit. Automatic shape recognition device. The method of claim 1, The boundary scan path detection unit includes: a TAP signal controller for controlling a TAP signal provided to a JTAG chip connected through a boundary scan chain to transfer a TDO signal output through a corresponding boundary scan path; An ID code register analyzer for analyzing and transmitting an ID code register value included in the TDO signal received from the TAP signal controller; A position information detector for transferring board position information transmitted from the backplane board through a edge connector in the form of a logical value; The ID connector register information transmitted by the ID code register analysis unit is transmitted to the central processing unit, and the board position information transmitted from the position information sensing unit is included in the board shape information determined by the central processing unit to provide the edge connector. Automatic shape recognition device of a system board comprising a shape information analysis / transmission unit for reporting to the upper main board through. The method of claim 3, wherein The JTAG chip is connected in a boundary scan chain and performs a boundary scan test according to a TAP signal provided by a TAP signal controller, and as a result, includes an ID code register value stored in an internal ID code register in a TDO signal. Automatic shape recognition device of the system board, characterized in that the output. Fusing the driving firmware into a memory of a board in the system and storing predefined board shape information; When a board is mounted on the backplane board of the system, generating board position information from the backplane board and transmitting the board position information through an edge connector; Analyzing the ID code register value output through the boundary scan path in the board mounted on the system and confirming the shape information of the board mounted in the system by comparing the board shape information previously stored in the memory; And including the board position information received from the backplane board in the determined board shape information to report to the upper main board through the edge connector.