KR100457280B1 - Semiconductor integrated circuit device and method for manufacturing the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same, wherein a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM and a logic integrated circuit are mixed to form a direct peripheral circuit of a DRAM. A silicide layer is formed on the surface of the source and drain of the MISFET, the surface of the source and drain of the MISFET constituting the indirect peripheral circuit, and the surface of the source and drain of the MISFET constituting the logic integrated circuit to form a memory cell of the DRAM. By not forming silicide layers on the surfaces of the source and drain of the memory cell selection MISFET, the high speed operation of the logic integrated circuit can be realized and the degradation of the refresh characteristics of the DRAM can be overcome. A technique that can be very preferably applied to a semiconductor integrated circuit device having a system-on-chip structure in which an integrated circuit is mixed is proposed.

Description

Semiconductor integrated circuit device and method of manufacturing the same {SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME}

Recently, in high technology fields such as multimedia and information communication, a system-on-chip structure in which microcomputers, DRAMs, and ASICs are mixed on one chip has been realized to increase data transfer speed, save space (improve mounting density), and reduce power consumption. The movement to seek back is getting active.

As one means for speeding up the logic integrated circuit portion, there is a technique of forming a silicide layer on the surface of a source and a drain. However, when silicide is formed in the source and the drain of the memory cell selection MISFET constituting the memory cell of the DRAM, the leakage current increases and the refresh characteristics are sacrificed.

As described above, when one chip is to be achieved while maintaining the performance of each DRAM and logic integrated circuit, it is necessary to newly develop a mixed process suitable for one chip.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique for realizing one chip while maintaining the performance of each of the DRAM and the logic integrated circuit in a system-on-chip semiconductor integrated circuit device in which the DRAM and the logic integrated circuit are mixed.

The above and other objects and novel features of the present invention will become apparent from the description and the accompanying drawings.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technology thereof, and in particular, to a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM (Dynamic Random Access Memory) and a logic integrated circuit are mixed. To a valid technology.

1 is an overall configuration diagram of a semiconductor chip showing a semiconductor integrated circuit device according to an embodiment of the present invention.

2 is a block diagram of a memory array and a direct peripheral circuit of a DRAM constituting a memory unit of the semiconductor integrated circuit device of the present invention.

3 is a sectional view showing the principal parts of a semiconductor substrate, each of which shows a memory portion and a logic integrated circuit portion of the semiconductor integrated circuit device of the present invention.

4 is a cross-sectional view of a main portion of a semiconductor substrate showing the method for manufacturing the semiconductor integrated circuit device of the present invention.

Fig. 5 is a cross-sectional view of a main portion of a semiconductor substrate showing the method for manufacturing the semiconductor integrated circuit device of the present invention.

Fig. 6 is a sectional view of the main portion of a semiconductor substrate, showing the method for manufacturing the semiconductor integrated circuit device of the present invention.

Fig. 7 is a sectional view of the main portion of a semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device of the present invention.

Fig. 8 is a sectional view showing the main parts of a semiconductor substrate showing the method for manufacturing the semiconductor integrated circuit device of the present invention.

9 is a sectional view showing the principal parts of a semiconductor substrate, which shows a method for manufacturing a semiconductor integrated circuit device of the present invention.

10 is a sectional view of principal parts of a semiconductor substrate, illustrating a method for manufacturing a semiconductor integrated circuit device of the present invention.

Fig. 11 is a sectional view showing the principal parts of a semiconductor substrate, showing the method for manufacturing the semiconductor integrated circuit device of the present invention.

12 is a sectional view showing the principal parts of a semiconductor substrate, showing the method for manufacturing the semiconductor integrated circuit device of the present invention.

Fig. 13 is a sectional view showing the principal parts of a semiconductor substrate, showing the method for manufacturing the semiconductor integrated circuit device of the present invention.

Fig. 14 is a sectional view showing the principal parts of a semiconductor substrate, showing the method for manufacturing the semiconductor integrated circuit device of the present invention.

Fig. 15 is a sectional view showing the principal parts of a semiconductor substrate, showing the method for manufacturing the semiconductor integrated circuit device of the present invention.

Fig. 16 is a sectional view showing the principal parts of a semiconductor substrate, showing the method for manufacturing the semiconductor integrated circuit device of the present invention.

17 is a sectional view of principal parts of a semiconductor substrate, illustrating a method for manufacturing a semiconductor integrated circuit device of the present invention.

Fig. 18 is a sectional view of principal parts of a semiconductor substrate, showing the method for manufacturing the semiconductor integrated circuit device of the present invention.

Fig. 19 is a sectional view showing the principal parts of a semiconductor substrate, showing the method for manufacturing the semiconductor integrated circuit device of the present invention.

20 is a sectional view showing the principal parts of a semiconductor substrate, showing the method for manufacturing the semiconductor integrated circuit device of the present invention.

Fig. 21 is a sectional view showing the principal parts of a semiconductor substrate, showing the method for manufacturing the semiconductor integrated circuit device of the present invention.

Fig. 22 is a sectional view showing the principal parts of a semiconductor substrate, showing the manufacturing method of the semiconductor integrated circuit device of the present invention.

Fig. 23 is a sectional view showing the main parts of a semiconductor substrate, showing the method for manufacturing the semiconductor integrated circuit device of the present invention.

Fig. 24 is a sectional view of principal parts of a semiconductor substrate, illustrating a method for manufacturing a semiconductor integrated circuit device of the present invention.

Fig. 25 is a sectional view showing the principal parts of a semiconductor substrate, showing the method for manufacturing the semiconductor integrated circuit device of the present invention.

Fig. 26 is a sectional view showing the principal parts of a semiconductor substrate, showing the method for manufacturing the semiconductor integrated circuit device of the present invention.

Fig. 27 is a sectional view showing the principal parts of a semiconductor substrate, showing the manufacturing method of the semiconductor integrated circuit device of the present invention.

Fig. 28 is a sectional view showing the principal parts of a semiconductor substrate, showing the method for manufacturing the semiconductor integrated circuit device of the present invention.

29 is a sectional view showing the main parts of a semiconductor substrate, showing the method for manufacturing the semiconductor integrated circuit device of the present invention.

30 is a sectional view showing the principal parts of a semiconductor substrate, showing the method for manufacturing the semiconductor integrated circuit device of the present invention.

<Description of Symbols for Major Parts of Drawings>

1: semiconductor substrate 2, 3: well

4, 9: n-type semiconductor region 5: device isolation groove

6, 7, 79: gate oxide films 8A to 8E: gate electrodes

10, 11, 40, 46, 76: silicon nitride film

11a and 41: sidewall spacers 12 and 16: n ^- type semiconductor region

13, 17: n ⁺ type semiconductor region 14, 18: p ⁻ type semiconductor region

15, 19: p ⁺ type semiconductor region 20, 29: Ti silicide layer

22, 23, 42, 52, 62, 68, 75, 78: silicon oxide film

24-27: First layer wiring

28, 48, 61, 67, 71: plug

30, 31, 34 to 38: contact hole 43: lower electrode (accumulating electrode)

44: capacitive insulating film 35, 45: upper electrode (plate electrode)

47, 58, 59, 60, 65, 66, 70: Thru-hole

51 spin-on glass film 53 to 57 second layer wiring

63, 64: 3rd layer wiring 69: 4th layer wiring

80, 84, 85: photoresist BL: bit line

C: Capacitive element for information storage WL: Word line

Hereinafter, the outline | summary of a typical thing among the invention disclosed in this application is demonstrated briefly.

The present invention relates to a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM and a logic integrated circuit are mixed, the source of the MISFET constituting the direct peripheral circuit of the DRAM, the surface of the drain, and the source of the MISFET constituting the indirect peripheral circuit, The silicide layer is formed on the drain surface, the source and drain surface of the MISFET constituting the logic integrated circuit, and the silicide layer is not formed on the source and drain surfaces of the memory cell selection MSIFET constituting the memory cell of the DRAM. This realizes a high speed operation of the logic integrated circuit and overcomes the deterioration of the refresh characteristics of the DRAM.

In addition, the summary of the invention described in the present application will be described as follows.

The semiconductor integrated circuit device of the present invention comprises a plurality of memory arrays each including a plurality of memory cells including at least a first region of a main surface of a semiconductor substrate, a memory cell selection MISFET and an information storage capacitor connected in series thereto. A DRAM having a direct peripheral circuit and an indirect peripheral circuit including the MISFET is formed, and a logic integrated circuit including the MISFET is formed in a second region of the main surface of the semiconductor substrate, and the direct peripheral circuit of the DRAM is formed. Silicide layers are formed on surfaces of the source and the drain of the MISFETs, the surfaces of the source and the drain of the MISFETs forming the indirect peripheral circuit of the DRAM, and the surfaces of the source and the drain of the MISFETs forming the logic integrated circuit. The silicide layer is not formed on the surfaces of the source and drain of the memory cell selection MISFET constituting the DRAM memory cell.

In the semiconductor integrated circuit device of the present invention, the gate oxide film thickness of the memory cell selection MISFET and the gate oxide film thickness of the MISFET constituting the direct peripheral circuit are the gate oxide film thickness of the MISFET constituting the indirect peripheral circuit and the logic integrated circuit. It is larger than the gate oxide film thickness of the MISFET constituting the.

In the semiconductor integrated circuit device of the present invention, the direct peripheral circuit includes a sense amplifier, a low decoder, and a column decoder, and the indirect peripheral circuit includes an input / output circuit, a logic circuit, an address selection circuit, a read amplifier, and a write amplifier. It includes.

In the semiconductor integrated circuit device of the present invention, the direct peripheral circuit of the DRAM includes a sense amplifier, a row decoder, a column decoder, a logic circuit, an address selection circuit, a read amplifier and a write amplifier. It includes an input / output circuit.

In the semiconductor integrated circuit device of the present invention, the silicide layer is made of titanium silicide.

The semiconductor integrated circuit device of the present invention comprises a gate electrode of the MISFET for memory cell selection of the DRAM, a gate electrode of the MISFET constituting the direct peripheral circuit, a gate electrode of the MISFET constituting the indirect peripheral circuit and the logic integrated circuit. The sheet resistance of the gate electrode of the MISFET to be configured is 2? /? Or less.

The semiconductor integrated circuit device of the present invention comprises a gate electrode of the MISFET for memory cell selection of the DRAM, a gate electrode of the MISFET constituting the direct peripheral circuit, a gate electrode of the MISFET constituting the indirect peripheral circuit and the logic integrated circuit. The gate electrode of the constituent MISFET is composed of a laminated film of a metal film and a polycrystalline silicon film.

The semiconductor integrated circuit device of the present invention is connected to a bit line connected to a memory cell selection MISFET of the DRAM, a first layer wiring connected to a MISFET constituting the direct peripheral circuit, and a MISFET constituting the indirect peripheral circuit. The first layer wiring to be connected to the first layer wiring connected to the MISFET constituting the logic integrated circuit is the wiring of the same layer manufactured in the same process.

The semiconductor integrated circuit device of the present invention is connected to a bit line connected to a memory cell selection MISFET of the DRAM, a first layer wiring connected to a MISFET constituting the direct peripheral circuit, and a MISFET constituting the indirect peripheral circuit. The sheet resistance of the first layer wiring to be connected to the first layer wiring connected to the MISFET constituting the logic integrated circuit is 2? /? Or less.

In the semiconductor integrated circuit device of the present invention, the direct peripheral circuit, the indirect peripheral circuit and the logic integrated circuit include a complementary MISFET.

A semiconductor integrated circuit device according to the present invention includes a memory array including a plurality of memory cells including at least a first region of a main surface of a semiconductor substrate, the memory cell selection MISFET and an information storage capacitor connected in series thereto; DRAMs each having a direct peripheral circuit and an indirect peripheral circuit including MISFETs are formed, and a logic integrated circuit including MISFETs is formed in a second region of the main surface of the semiconductor substrate, and an indirect peripheral circuit of the DRAM is formed. A silicide layer is formed on the surfaces of the source and the drain of the MISFET constituting the circuit, the source and the drain of the MISFET constituting the logic integrated circuit, and the source of the memory cell selection MISFET constituting the memory cell of the DRAM; No silicide layer is formed on the surface of the drain and the surfaces of the source and the drain of the MISFET constituting the direct peripheral circuit of the DRAM.

The manufacturing method of the semiconductor integrated circuit device of the present invention includes the following steps.

(a) A first gate oxide film is formed in a part of the first region of the main surface of the semiconductor substrate, and a second gate oxide film having a thinner film thickness than the first gate oxide film is formed in another part and the second region of the first region. Forming process,

(b) forming a gate electrode of a MISFET constituting a direct peripheral circuit with a gate electrode of a memory cell selection MISFET in a portion of the first region, and forming an indirect peripheral circuit in another portion of the first region. Forming a gate electrode and forming a gate electrode of a MISFET constituting a logic integrated circuit in the second region;

(c) a source and a drain of the memory cell selection MISFET, a source and a drain of the MISFET constituting the direct peripheral circuit, a source and a drain of the MISFET constituting the indirect peripheral circuit, and the logic integrated circuit. Forming the source and the drain of the MISFET,

(d) exposing the source and drain surface of the MISFET constituting the direct peripheral circuit, the source and drain surface of the MISFET constituting the indirect peripheral circuit, and the source and drain surface of the MISFET constituting the logic integrated circuit; Covering a surface of a source and a drain of the memory cell selection MISFET with an insulating film, and then depositing a metal film on a main surface of the semiconductor substrate;

(e) By heat-treating the semiconductor substrate, the source and the drain of the MISFET constituting the direct peripheral circuit, the source and the drain of the MISFET constituting the indirect peripheral circuit, and the source and the drain of the MISFET constituting the logic integrated circuit. Forming a silicide layer in the vicinity of an interface between the metal film and each.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in the whole figure for demonstrating an embodiment, the thing which has the same function attaches | subjects the same code | symbol, and the repeated description is abbreviate | omitted.

As shown in Fig. 1, the semiconductor integrated circuit device of this embodiment is a microcomputer in which a CPU (information processing section), a memory section composed of DRAM, a logic integrated circuit section composed of an ASIC, and an analog circuit section are formed on the main surface of the same semiconductor chip.

As shown in Fig. 2, the DRAM constituting the memory unit of the microcomputer includes a memory array (MARY), a direct peripheral circuit comprising a sense amplifier, a low decoder, and a column decoder adjacent thereto, and an input / output not shown. It consists of an indirect peripheral circuit consisting of a circuit, a logic circuit, an address selection circuit, a read amplifier and a write amplifier.

The DRAM memory array MARY is composed of a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells arranged at their intersections. One memory cell that stores one bit of information includes one information storage capacitor C and one memory cell selection MISFET Qs connected in series thereto. One of the source and the drain of the memory cell selection MISFET Qs is electrically connected to the information storage capacitor C, and the other is electrically connected to the bit line BL.

3 is a cross-sectional view of the main part of the semiconductor substrate, which shows respective portions of the memory array MARY of the DRAM constituting the memory section of the microcomputer and the direct peripheral circuits adjacent thereto, and the right side of FIG. The portion (second region) is a cross-sectional view of the main portion of the semiconductor substrate showing a portion of the logic integrated circuit portion.

The p type well 2 and the n type well 3 are formed in the first region and the second region of the semiconductor substrate 1 made of p type single crystal silicon. Although not particularly limited, the p-type well 2 common to a part of the memory array MARY and the direct peripheral circuit is designed to prevent the influence of noise from a circuit formed in another region of the semiconductor substrate 1. It is electrically separated from the p-type semiconductor substrate 1 by the n-type semiconductor region 4 formed below.

An element isolation groove 5 is formed on the surface of each of the p-type well 2 and the n-type well 3. The device isolation groove 5 has a structure in which a silicon oxide film is filled in the groove formed in the semiconductor substrate 1, and the surface of the device isolation groove 5 is formed in the active region of the p-type well 2 and the n-type well 3; It is flattened to be almost the same height as the surface.

Memory cells are formed in the active region of the p-type well 2 of the memory array MARY. Each of the memory cells has one memory cell selection MISFET (Qs) having an n-channel type, and one information storage capacitor (C) formed on top thereof and connected in series with the memory cell selection MISFET (Qs). Consists of In other words, the memory cell has a stacked capacitor structure in which the information storage capacitor C is disposed on the memory cell selection MISFET Qs.

The memory cell selection MISFET Qs is constituted by the first gate oxide film 6, the gate electrode 8A formed integrally with the word line WL, and the source and drain (n-type semiconductor region 9). The film thickness of the first gate oxide film 6 is about 7 to 8 nm. The gate electrode 8A (word line WL) is formed by stacking a low-resistance polycrystalline silicon film doped with n-type impurities (for example, P (phosphorus)), a TiN (titanium nitride) film, and a W (tungsten) film. It is composed of three conductive films, and its sheet resistance is 2 Ω / □ or less, A silicon nitride film 10 is formed on the gate electrode 8A, and a silicon nitride film 11 is formed on the sidewall. have.

An n-channel MISFET Qn1 is formed in the active region of the p-type well 2 of the direct peripheral circuit, and a p-channel MISFET Qp1 is formed in the active region of the n-type well 3. In other words, the direct peripheral circuit is composed of a complementary metal oxide semiconductor (CMOS) circuit (complementary MISFET circuit) in which an n-channel MISFET Qn1 and a p-channel MISFET Qp1 are combined.

The n-channel MISFET Qn1 is composed of the first gate oxide film 6, the gate electrode 8B, a source and a drain. The film thickness of the first gate oxide film 6 is the same as that of the first gate oxide film 6 of the memory cell selection MISFET Qs (about 7 to 8 nm). The gate electrode 8B is made of the same conductive film as the gate electrode 8A (word line WL) of the memory cell selection MISFET Qs, and its sheet resistance is 2? /? Or less. The silicon nitride film 10 is formed on the gate electrode 8B, and the sidewall spacer 11a of silicon nitride is formed on the side wall. Each of the source and the drain of the n-channel MISFET Qn1 is composed of a lightly doped drain (LDD) structure including an n ⁻ type semiconductor region 12 having a low impurity concentration and an n ⁺ type semiconductor region 13 having a high impurity concentration. The Ti silicide (TiSi ₂ ) layer 20 is formed on the surface of the n ⁺ type semiconductor region 13.

The p-channel MISFET Qp1 is composed of the first gate oxide film 6, the gate electrode 8C, a source and a drain. The film thickness of the first gate oxide film 6 is the same as that of the first gate oxide film 6 of the memory cell selection MISFET Qs (about 7 to 8 nm). The gate electrode 8C is composed of the same conductive film as the gate electrode 8A (word line WL) of the memory cell selection MISFET Qs, and its sheet resistance is 2? /? Or less. The silicon nitride film 10 is formed on the gate electrode 8C, and the sidewall spacer 11a of silicon nitride is formed on the side wall. source, and each drain of the p-channel type MISFET (Qp1) is a low impurity concentration p ^- consists of a-type semiconductor region 14 and the high impurity concentration of p ⁺ type LDD structure comprising a semiconductor region (15), p ⁺ The Ti silicide layer 20 is formed on the surface of the type semiconductor region 15.

An n-channel MISFET Qn2 is formed in the active region of the p-type well 2 of the logic integrated circuit section (second region), and a p-channel MISFET Qp2 is formed in the active region of the n-type well 3. It is. In other words, the logic integrated circuit section is composed of a CMOS circuit combining an n-channel MISFET Qn2 and a p-channel MISFET Qp2.

The n-channel MISFET Qn2 is composed of the second gate oxide film 7, the gate electrode 8D, the source and the drain. The film thickness of the second gate oxide film 7 is thinner than the first gate oxide film 6 in the first region and is about 4 nm. The gate electrode 8D is made of the same conductive film as the gate electrode 8A (word line WL) of the memory cell selection MISFET Qs, and its sheet resistance is 2? /? Or less. The silicon nitride film 10 is formed on the gate electrode 8D, and the sidewall spacer 11a of silicon nitride is formed on the side wall. n sources, each of the drain-channel type MISFET (Qn2) is n in the low impurity concentration ^- consists of an LDD structure comprising a semiconductor region 16 and the high n ⁺ -type semiconductor region 17, the impurity concentration, n ⁺ The Ti silicide layer 20 is formed on the surface of the type semiconductor region 17.

The p-channel MISFET Qp2 is composed of the second gate oxide film 7, the gate electrode 8E, the source and the drain. The film thickness of the second gate oxide film 7 is the same (about 4 nm) as that of the second gate oxide film 7 of the n-channel MISFET Qn2. The gate electrode 8E is composed of the same conductive film as the gate electrode 8A (word line WL) of the memory cell selection MISFET Qs, and its sheet resistance is 2? /? Or less. The silicon nitride film 10 is formed on the gate electrode 8E, and the sidewall spacer 11a of silicon nitride is formed on the side wall. source, and each drain of the p-channel type MISFET (Qp2) is of the p-impurity concentration ^- consists of an LDD structure comprising a semiconductor region 18 and a high p ⁺ type semiconductor region 19 the impurity density, p ⁺ The Ti silicide layer 20 is formed on the surface of the type semiconductor region 19.

An indirect peripheral circuit of a DRAM is formed in a region not shown in the memory section (first region). This indirect peripheral circuit is composed of a CMOS circuit combining an n-channel MISFET and a p-channel MISFET.

The n-channel MISFET of the indirect peripheral circuit has the same configuration as the n-channel MISFET Qn2 of the logic integrated circuit section. That is, the n-channel MISFET of the indirect peripheral circuit has the same conductivity as the second gate oxide film 7 having a film thickness of about 4 nm and the gate electrode 8A (word line WL) of the memory cell selection MISFET Qs. A gate electrode composed of a film, an LDD structure source and a drain composed of a low impurity concentration n ⁻ type semiconductor region and a high impurity concentration n ⁺ type semiconductor region, and a Ti silicide layer on the surface of the n ⁺ type semiconductor region. 20 is formed.

The p-channel MISFET of the indirect peripheral circuit has the same configuration as the p-channel MISFET Qp2 of the logic integrated circuit portion. That is, the p-channel MISFET of the indirect peripheral circuit has the same conductive film as the second gate oxide film 7 having a film thickness of about 4 nm and the gate electrode 8A (word line WL) of the memory cell selection MISFET Qs. as consisting of a gate electrode, a low impurity concentration of the p ^-, and-type semiconductor region and the high is composed of a source and a drain of the LDD structure consisting of a p ⁺ type semiconductor region of the impurity concentration, the Ti silicide layer surface of the p ⁺ type semiconductor region ( 20) is formed.

Since the MISFET constituting the indirect peripheral circuit of the DRAM has the same configuration as the MISFET constituting the logic integrated circuit section as described above, the description thereof will be omitted below.

MISFET (Qs), n-channel MISFET (Qn1), p-channel MISFET (Qp1), n-channel MISFET (Qn2), and p-channel MISFET (Qp2) of the logic section. The silicon oxide film 22 is formed in this. The surface of the silicon oxide film 22 is planarized such that its height is substantially the same on the entire surface of the semiconductor substrate 1.

The silicon oxide film 23 is formed on the silicon oxide film 22. The bit line BL and the first layer wirings 24 and 25 of the direct peripheral circuit are formed on the silicon oxide film 23 in the memory section, and the logic integrated on the silicon oxide film 23 in the logic integrated circuit section. The first layer wirings 26 and 27 of the circuit are formed. These bit lines BL and the first layer wirings 24 to 27 are composed of two layers of conductive films in which a TiN film and a W film are stacked, and the sheet resistance thereof is 2 Ω / square or less.

The bit line BL is electrically connected to one (n-type semiconductor region 9) of the source and the drain of the memory cell selection MISFET Qs through the contact hole 30 filled with the plug 28. The plug 28 is made of a polysilicon film doped with n-type impurities (for example, P). One end of the bit line BL is electrically connected to one (n ⁺ type semiconductor region 13) of the source and the drain of the n-channel MISFET Qn1 of the direct peripheral circuit through the contact hole 32.

One end of the first layer wiring 24 of the direct peripheral circuit is electrically connected to the other (n ⁺ type semiconductor region 13) of the source and the drain of the n-channel MISFET Qn1 through the contact hole 33. The other end is electrically connected to one of the source and the drain (p ⁺ type semiconductor region 15) of the p-channel MISFET Qp1 through the contact hole 34. The first layer wiring 25 of the direct peripheral circuit is electrically connected to the other (p ⁺ type semiconductor region 15) of the source and the drain of the p-channel MISFET Qp1 through the contact hole 35.

The first layer wiring 26 of the logic integrated circuit is electrically connected to one (n ⁺ type semiconductor region 17) of the source and the drain of the n-channel MISFET Qn2 through the contact hole 36. One end of the first layer wiring 27 of the logic integrated circuit portion is electrically connected to the other (n ⁺ type semiconductor region 17) of the source and drain of the n-channel MISFET Qn2 through the contact hole 37. The other end is electrically connected to one of the source and the drain (p ⁺ type semiconductor region 19) of the p-channel MISFET Qp2 through the contact hole 38.

The silicon nitride film 40 is formed on the bit lines BL and the first layer wirings 24 to 27, and the sidewall spacers 41 of the silicon nitride film are formed on the sidewalls. The silicon oxide film 42 is formed further on the bit line BL and the first layer wirings 24 to 27.

On the silicon oxide film 42 of the memory array MARY, an information storage capacitor formed of a lower electrode (accumulating electrode) 43, a capacitor insulating film 44, and an upper electrode (plate electrode) 35 is formed. C) is formed. The lower electrode 43 of the information storage capacitor C is made of a W film, and fills the through-hole 47 filling the plug 48 of the W (or polycrystalline silicon) film and the plug 28 of the polycrystalline silicon film. The contact hole 31 is electrically connected to the other (n-type semiconductor region 9) of the source and the drain of the memory cell selection MISFET Qs. The capacitor insulating film 44 is made of a tantalum oxide (Ta ₂ O ₅ ) film, and the plate electrode 45 is made of a TiN film. The silicon nitride film 46 is formed on the plate electrode 45.

On the information storage capacitor C, a spin on glass film 51 and a silicon oxide film 52 are formed. Second layer wirings 53 to 56 are formed on the silicon oxide film 52 in the memory portion, and second layer wiring 57 is formed on the silicon oxide film 52 in the logic integrated circuit portion. These second layer wirings 53 to 57 are composed of three conductive films in which a TiN film, an Al (aluminum) alloy film, and a TiN film are laminated.

The second layer wiring 55 of the memory portion is electrically connected to the upper electrode 45 of the data storage capacitor C through the through hole 58 filled with the plug 61 of the W film, and the upper electrode 45 Supply a plate voltage (e.g. Vdd / 2) to the The second layer wiring 56 of the direct peripheral circuit is electrically connected to the first layer wiring 24 through the through hole 59 filled with the plug 61 of the W film. The second layer wiring 57 of the logic integrated circuit portion is electrically connected to the first layer wiring 27 through the through hole 60 filled with the plug 61 of the W film.

The silicon oxide film 62 is formed on the second layer wirings 53 to 57, and the third layer wiring 63 of the direct peripheral circuit and the third layer wiring 64 of the logic integrated circuit portion are formed thereon. Formed. These third layer wirings 63 and 64 are composed of three layers of conductive films in which a TiN film, an Al alloy film, and a TiN film are laminated. The third layer wiring 63 of the direct peripheral circuit is electrically connected to the second layer wiring 56 through the through hole 65 filled with the plug 67 of the W film, and the third layer wiring 64 of the logic integrated circuit portion. ) Is electrically connected to the second layer wiring 57 through the through hole 66 filled with the plug 67 of the W film.

The silicon oxide film 68 is formed on the third layer wirings 63 and 64, and the fourth layer wiring 69 of the logic integrated circuit portion is formed on the upper portion of the third layer wirings 63 and 64. The fourth layer wiring 69 is composed of three conductive films in which a TiN film, an Al alloy film, and a TiN film are stacked. The fourth layer wiring 69 is electrically connected to the third layer wiring 64 through the through hole 70 filled with the plug 71 of the W film.

On the upper part of the fourth layer wiring 69, there are formed one to three layers of wiring of the logic integrated circuit section, and a passivation film composed of two layers of insulating films and the like laminated with a silicon oxide film and a silicon nitride film is formed thereon. It is formed, the illustration thereof will be omitted.

Next, an example of the manufacturing method of the semiconductor integrated circuit device described above will be described with reference to FIGS.

First, as shown in FIG. 4, the silicon substrate film 75 having a film thickness of about 10 to 30 nm is formed on the surface by heat-treating the semiconductor substrate 1 made of single crystal silicon having a p-type low resistance of about 10? Cm. On this silicon oxide film 30, a silicon nitride film 76 having a film thickness of about 100 to 140 nm is deposited by CVD (Chemical Vapor Deposition) method. Next, as shown in FIG. 5, using the photoresist 77 formed on the silicon nitride film 76 as a mask, the silicon nitride film 76, the silicon oxide film 75, and the semiconductor substrate 1 in the element isolation region. Are sequentially etched to form grooves 5a having a depth of about 350 to 400 nm in the semiconductor substrate 1. The gas for etching the silicon nitride film 76 uses CF ₄ + CHF ₃ + Ar or CF ₄ + Ar, and the gas for etching the semiconductor substrate 1 uses HBr + Cl ₂ + He + O ₂ . .

Next, as shown in FIG. 6, the silicon oxide film 78 deposited on the semiconductor substrate 1 by the CVD method is polished by chemical mechanical polishing (CMP) and left in the groove 5a. As a result, the device isolation groove 5 is formed. Thereafter, heat treatment at about 1000 ° C. to increase the density of the silicon oxide film 78 filled in the device isolation grooves 5, and then wet etching using thermal phosphoric acid on the semiconductor substrate 1. The remaining silicon nitride film 76 is removed.

Next, as shown in FIG. 7, the n-type semiconductor region 4 is placed on the semiconductor substrate 1 in the region forming the DRAM memory array MARY and a part of the direct peripheral circuit (n-channel MISFET Qn1). After the formation, a p-type well 2 is formed in the semiconductor substrate 1 in the region where the thin portion of the n-type semiconductor region 4 and the portion of the logic integrated circuit portion (n-channel MISFET Qn2) are formed. N in the semiconductor substrate 1 in the region forming another part of the direct peripheral circuit of the DRAM (p-channel MISFET Qp1) and the other portion of the logic integrated circuit part (p-channel MISFET Qp2). The mold well 3 is formed. The n-type semiconductor region 4 is formed by implanting P (phosphorus) into the semiconductor substrate 1 and then diffusing P broadly by heat treatment at about 1000 占 폚. In addition, the p-type well 2 and the n-type well 3 are ion-implanted with P in a part of the semiconductor substrate 1, and ion implantation of B (boron) in another part, followed by P treatment by heat treatment at about 950 ° C. It is formed by diffusing and B widely.

Next, the silicon oxide film 75 remaining on the surface of the p-type well 2 and the surface of the n-type well is removed using a HF (fluoric acid) -based cleaning solution, and then wetted at about 800 ° C. as shown in FIG. 8. A clean gate oxide film 79 is formed on the surface of the p-type well 2 and the surface of the n-type well by the oxidation method.

Next, as shown in FIG. 9, the regions forming the memory array MARY and the direct peripheral circuit are covered with the photoresist 80, and the surfaces of the p-type wells 2 and n-type wells 3 of the logic integrated circuit section are next. The gate oxide film 79 is removed using a HF-based cleaning solution. The boundary of the photoresist 80 is disposed on the element isolation groove 5 spaced apart from the region forming the memory array MARY and the direct peripheral circuit and the logic integrated circuit portion.

Next, as shown in FIG. 10, the second gate oxide film 7 having a film thickness of about 4 nm is formed on the surfaces of the p-type wells 2 and n-type wells 3 of the logic integrated circuit section by performing wet oxidation once more. ). At this time, the gate oxide film 79 on the surface of the p-type well 2 and the n-type well 3 in the region forming the memory array MARY formed by the first wet oxidation and the direct peripheral circuit also grows to form a first gate oxide film ( 6), the film thickness of the gate oxide film 79 is set in advance so that the film thickness is about 7 to 8 nm.

Next, as shown in FIG. 11, a gate electrode 8A (word line WL) is formed on the first gate oxide film 6 of the memory array MARY, and is formed on the gate oxide film 6 of the direct peripheral circuit. And gate electrodes 8B to 8E on the second gate oxide film 7 of the logic integrated circuit portion, respectively. In order to form the gate electrode 8A (word line WL) and the gate electrodes 8B to 8E, first, a polycrystalline silicon film having a film thickness of about 70 nm deposited with P on the semiconductor substrate 1 is deposited by CVD. A TiN film having a film thickness of about 50 nm and a W film having a film thickness of about 100 nm are deposited on the upper portion thereof, and a silicon nitride film 10 having a film thickness of about 200 nm is deposited on the upper portion thereof by CVD. . Next, the silicon nitride film 10, the W film, the TiN film, and the polysilicon film are patterned by etching using the photoresist as a mask. The gas for etching the silicon nitride film 10 uses CF ₄ + CHF ₃ + Ar or CF ₄ + Ar, and the gas for etching the W film uses Cl ₂ + SF ₆ . In addition, the gas for etching the TiN film uses Cl ₂ , and the gas for etching the polysilicon film uses Cl ₂ + O ₂ .

Next, as shown in FIG. 12, an n-type semiconductor region 9 (source, drain) of the memory cell selection MISFET Qs is formed in the p-type well 2 of the memory array MARY, and the direct peripheral circuit N ^- type semiconductor region 12 of n ^- channel MISFET Qn1 is formed in p-type well 2 of the circuit, and n ^- type of n ^- channel MISFET Qn2 is formed in p-type well 2 of the logic integrated circuit section. The semiconductor region 16 is formed. Further, the p ⁻ type semiconductor region 14 of the p channel type MISFET Qp1 is formed in the n type well 2 of the direct peripheral circuit, and the p channel type MISFET Qp 2 is formed in the n type well 2 of the logic integrated circuit portion. P ^- type semiconductor region 18 is formed. The n-type semiconductor region 9 and the n ⁻ -type semiconductor regions 12 and 16 are formed by implanting P into the p-type well 2 using a photoresist covering the n-type well 3 as a mask, and p ^The type semiconductor regions 14 and 18 are formed by implanting B into the n type well 3 using a photoresist covering the p type well 2 as a mask.

Next, as shown in FIG. 13, a silicon nitride film 11 having a film thickness of about 10 to 50 nm is deposited on the semiconductor substrate 1 by CVD, and then the memory array MARY is formed as shown in FIG. The sidewall spacers 11a are formed on the sidewalls of the gate electrodes 8B to 8E by anisotropically etching the silicon nitride film 11 directly covered with the photoresist 81 and the peripheral circuit portion and the logic integrated circuit portion. At this time, the boundary of the photoresist 81 is disposed on the element isolation groove 5 that separates the memory array MARY from the direct peripheral circuit. In order to minimize the amount of chipping of the silicon oxide film filled in the device isolation groove 5 and the silicon nitride film 10 on the gate electrodes 8B to 8E, the etching amount is reduced to the minimum necessary, An etching gas (e.g., CH ₂ F ₂ , CH ₃ F or Cl ₂ + O ₂ ) that can take a large selectivity to the silicon oxide film is used.

Next, as shown in FIG. 15, the n ⁺ type semiconductor region 13 of the n channel type MISFET Qn1 is formed in the p type well 2 of the direct peripheral circuit, and the p channel type is formed in the n type well 2. The p ⁺ type semiconductor region 15 of the MISFET Qp1 is formed. Further, the n ⁺ type semiconductor region 17 of the n channel type MISFET Qn2 is formed in the p type well 2 of the logic integrated circuit portion, and the p ⁺ of the p channel type MISFET Qp2 is formed in the n type well 2. The type semiconductor region 19 is formed. The n ⁺ -type semiconductor regions 13 and 17 are formed by ion implantation of As (arsenic) into the p-type well 2, and the p ⁺ -type semiconductor regions 15 and 19 ionize B into the n-type well 3. Formed by injection.

Next, as shown in FIG. 16, the Ti film 82 having a film thickness of about 40 nm is deposited on the semiconductor substrate 1 by sputtering, and then heat-treated in a nitrogen environment at 600 to 700 ° C. As shown in Fig. 17, since the memory array MARY is covered with the silicon nitride film 11, no silicide reaction occurs in this region, whereas in the direct peripheral circuit and the logic integrated circuit portion, the semiconductor substrate 1 In the exposed portions (n ⁺ -type semiconductor regions 13 and 17 and p ⁺ -type semiconductor regions 15 and 19), silicide reaction occurs, and Ti silicide (TiSi ₂ ) layer 20 is formed on their surfaces. .

Next, after the unreacted Ti film 82 is removed by wet etching, the silicon oxide film 22 is deposited on the semiconductor substrate 1 by CVD as shown in FIG. 18, and then chemical mechanical polishing is performed. To planarize the surface of the silicon oxide film 22.

Next, as shown in FIG. 19, the silicon oxide film 22 on the n-type semiconductor region 9 (source and drain) of the memory cell selection MISFET Qs is formed by etching using the photoresist 84 as a mask. Remove This etching is performed under the condition that the etching rate of the silicon oxide film 22 with respect to the silicon nitride films 10 and 11 can be large, so that the silicon nitride film 11 on the n-type semiconductor region 9 is not removed. do.

Next, as shown in FIG. 20, the silicon nitride film 11 above the n-type semiconductor region 9 (source and drain) of the memory cell selection MISFET Qs by etching using the photoresist 84 as a mask. By removing the second gate oxide film 7, a contact hole 31 is formed over one of the source and drain (n-type semiconductor region 9). In order to minimize the amount of shaving of the semiconductor substrate 1, this etching uses an etching gas capable of suppressing the overetching amount to the minimum necessary and taking the selectivity to silicon large. Further, this etching is performed under the condition that the silicon nitride film 10 can be anisotropically etched, leaving the silicon nitride film 11 on the sidewall of the gate electrode 8A (word line WL). In this way, the contact holes 30 and 31 are formed in self-alignment with the silicon nitride film 11 on the sidewall of the gate electrode 8A (word line WL).

Next, as shown in FIG. 24, the bit line BL is formed on the silicon oxide film 23 of the memory array MARY, and the first silicon oxide film 23 is formed on the first peripheral circuit and the logic integrated circuit part. The layer wirings 24 to 27 are formed. The bit lines BL and the first layer wirings 24 to 27 deposit a TiN film and a W film on the silicon oxide film 23 by sputtering, and then a silicon nitride film (CVD) on the W film. 40) are formed by patterning these films by etching using a photoresist as a mask.

Next, as shown in FIG. 25, the sidewall spacers 41 are formed on the sidewalls of the bit lines BL and the first layer wirings 24 to 27, and then the bit lines BL and the first layer wirings ( After depositing the silicon oxide film 42 on top of the 24-27 by CVD, the silicon oxide films 42 and 23 on the contact hole 31 are removed by etching using a photoresist as a mask. 47). The sidewall spacer 41 is formed by processing an anisotropic etching of a silicon nitride film deposited by CVD on the bit lines BL and the first layer wirings 24 to 27. The etching for forming the through holes 47 is performed under conditions in which the etching rate of the silicon oxide film with respect to the silicon nitride film 40 and the side wall spacer 41 can be increased, and the through holes 47 are sidewalled. The spacers 41 are formed in self-alignment.

Next, as shown in Fig. 26, the plug 48 of the W film is filled in the through hole 47, and then the lower electrode (accumulating electrode) 43 of the information storage capacitor is formed thereon. The plug 48 is formed by depositing a W film on top of the silicon oxide film 42 by CVD or sputtering, and then polishing the W film by chemical mechanical polishing to leave the inside of the through hole 47. The lower electrode 43 is similarly formed by depositing a W film on the silicon oxide film 42 by CVD or sputtering and patterning the W film by etching using a photoresist as a mask.

Next, as shown in FIG. 27, the capacitor insulating film 44 and the upper electrode (plate electrode) 45 of the information storage capacitor C are formed on the lower electrode (accumulating electrode) 43. As shown in FIG. The capacitive insulating film 44 and the upper electrode 45 deposit a tantalum oxide film on the silicon oxide film 42 by CVD or sputtering, deposit a TiN film on the upper by sputtering, and further, on top of the silicon oxide film 42. After the silicon nitride film 46 is deposited, these films are formed by etching using a photoresist as a mask.

Next, as shown in FIG. 28, the spin-on glass film 51 is formed on the information storage capacitor C by the spin coating method, followed by the CVD method on the spin-on glass film 51. After the silicon oxide film 52 is deposited, the silicon oxide film 52, the spin-on-glass film 51 and the silicon nitride film 46 are etched using the photoresist as a mask, thereby capturing the information storage capacitor C. Through-holes 58 are formed in the upper portion of the upper electrode 45. At this time, the silicon oxide film 52, the spin-on-glass film 51, the silicon oxide film 42, and the silicon nitride film 40 of the direct peripheral circuit and the logic integrated circuit portion are simultaneously etched to form the first peripheral circuit of the direct peripheral circuit. Through-holes 59 are formed in the upper portion of the layer wirings 24, and through-holes 60 are formed in the upper portion of the first layer wirings 27 in the logic integrated circuit portion.

Next, as shown in FIG. 29, after filling the plug 61 of the W film into the through holes 59 to 60, the second layer wirings 53 to 57 are formed on the silicon oxide film 52. Next, as shown in FIG. do. The second layer wiring 55 of the memory array MARY is electrically connected to the upper electrode 45 of the information storage capacitor C through the through hole 58, and the second layer wiring of the direct peripheral circuit ( 56 is electrically connected to the first layer wiring 24 through the through hole 59, and the second layer wiring 57 of the logic integrated circuit part is connected to the first layer wiring 27 through the through hole 60. Electrically connected. The second layer wirings 53 to 57 are formed by depositing a TiN film, an Al alloy film, and a TiN film on the silicon oxide film 52 by sputtering, and then patterning these films by etching using a photoresist as a mask.

Next, as shown in FIG. 30, the silicon oxide film 62 is deposited on the second layer wirings 53 to 57, and the third layer wirings 63 and 64 are formed thereon. To form the third layer wirings 63 and 64, first, a silicon oxide film 62 is deposited on the second layer wirings 53 and 57 by CVD, and then a silicon oxide film (using a photoresist as a mask) is formed. Through etching 62, a through hole 65 is formed in the upper portion of the second layer wiring 56 in the direct peripheral circuit, and the through hole 66 is formed in the upper portion of the second layer wiring 57 in the logic integrated circuit portion. . Subsequently, after filling the plug 67 of the W film into the through holes 65 and 66, a TiN film, an Al alloy film, and a TiN film were deposited on the silicon oxide film 62 by sputtering to form a photoresist. These films are patterned by etching using the mask as a mask. The third layer wiring 63 of the direct peripheral circuit is electrically connected to the second layer wiring 56 via the through hole 65, and the third layer wiring 64 of the logic integrated circuit part is the through hole 66. Is electrically connected to the second layer wiring 57 through the reference numeral).

Thereafter, the silicon oxide film 68 is deposited on the third layer wiring 64 of the logic integrated circuit portion and the fourth layer wiring 69 is formed on the semiconductor integrated circuit shown in FIG. The device is roughly complete. In order to form the fourth layer wiring 69, a silicon oxide film 68 is first deposited on the third layer wirings 56 and 57 by CVD, and then the silicon oxide film 68 using a photoresist as a mask. The through holes 70 are formed in the upper portion of the third layer wiring 64 of the logic integrated circuit portion by etching the. Subsequently, after filling the plug 71 of the W film into the through hole 70, a TiN film, an Al alloy film, and a TiN film are deposited on the silicon oxide film 70 by sputtering to mask the photoresist. These films are patterned by etching. The fourth layer wiring 69 is electrically connected to the third layer wiring 64 through the through hole 70.

According to the semiconductor integrated circuit device of the present embodiment configured as described above, the following effects can be obtained.

(1) A logic integrated circuit is formed by forming a thin gate oxide film of the MISFET constituting the logic integrated circuit section and simultaneously forming a gate electrode with a conductive material so as to have a sheet resistance of 2? /? High speed operation can be realized.

(2) By not silencing the source and drain of the memory cell selection MISFET constituting the memory cell of the DRAM, it is possible to prevent an increase in the leakage current by silicide and overcome the deterioration of the refresh characteristics.

(3) By configuring the gate electrode of the memory cell selection MISFET constituting the memory cell of the DRAM with a conductive material such that the sheet resistance is 2? /? Or less, the gate delay can be reduced. In addition, since the word wiring is not required by the metal wiring, the DRAM manufacturing process is simplified and the productivity is improved.

As mentioned above, although the invention made by this inventor was demonstrated concretely based on the Example, this invention is not limited to the said Example, It can change variously in the range which does not deviate from the summary.

In the above embodiment, a sense amplifier, a low decoder and a column decoder of a DRAM are defined as direct peripheral circuits. For example, a sense amplifier, a low decoder, a column decoder, a logic circuit, an address selection circuit, The read and write amplifiers may be defined as direct peripheral circuits, and the input / output circuits may be defined as indirect peripheral circuits.

In the above embodiment, the surface of the source and the drain of the MISFET constituting the direct peripheral circuit of the DRAM, the surface of the source and the drain of the MISFET constituting the indirect peripheral circuit, and the surface of the source and the drain of the MISFET constituting the logic integrated circuit. The silicide layer was formed on the silicon cell, and the silicide layer was not formed on the surfaces of the source and the drain of the memory cell selection MISFET constituting the DRAM memory cell.For example, the source and the drain of the MISFET constituting the DRAM indirect peripheral circuit. A silicide layer is formed on the surface of the MISFET and the surface of the source and the drain of the MISFET constituting the logic integrated circuit, and the surfaces of the source and the drain of the memory cell selection MISFET constituting the memory cell of the DRAM and the direct peripheral circuit of the DRAM The silicide layer may not be formed on the surfaces of the source and the drain of the MISFET. In this case, since the manufacturing process of the DRAM memory array and the direct peripheral circuit can be shared, it is possible to distribute the DRAM memory array and the direct peripheral circuit alone as the DRAM core. In addition, the logic integrated circuit portion in which the source and drain are silicided may be distributed alone as a logic core.

In the above embodiment, Ti is used as the silicide material, but other metal materials such as Co (cobalt) may be used.

According to the present invention, since the high speed operation of the logic integrated circuit can be realized and the degradation of the refresh characteristics of the DRAM can be overcome, the semiconductor integrated circuit device of the system-on-chip structure in which the DRAM and the logic integrated circuit are mixed is highly desirable. Can be applied.

Claims (32)

At least in the first region of the main surface of the semiconductor substrate, A memory array including a plurality of memory cells comprising a memory cell selection MISFET and an information storage capacitor connected in series thereto; DRAMs each having a direct peripheral circuit and an indirect peripheral circuit each including a MISFET are formed, In the second region of the main surface of the semiconductor substrate, In a semiconductor integrated circuit device having a logic integrated circuit comprising a MISFET, A surface of a source and a drain of the MISFET constituting the direct peripheral circuit of the DRAM; A surface of a source and a drain of the MISFET constituting the indirect peripheral circuit of the DRAM; Silicide layers are formed on surfaces of the source and drain of the MISFET constituting the logic integrated circuit, Silicide layers are not formed on the surfaces of the source and drain of the memory cell selection MISFET forming the memory cells of the DRAM, and the plugs and wirings connected to the MISFETs of the logic circuit are the same as the bit lines following the memory cell selection MISFET. A semiconductor integrated circuit device, which is formed of a material. The method according to claim 1, The gate oxide film thickness of the memory cell selection MISFET and the gate oxide film thickness of the MISFET constituting the direct peripheral circuit are: And a gate oxide film thickness of the MISFET constituting the indirect peripheral circuit and a gate oxide film thickness of the MISFET constituting the logic integrated circuit. The method according to claim 1, The direct peripheral circuit, A sense amplifier, a low decoder and a column decoder, The indirect peripheral circuit, A semiconductor integrated circuit device comprising an input / output circuit, a logic circuit, an address selection circuit, a read amplifier and a write amplifier. The method according to claim 1, The direct peripheral circuit of the DRAM, A sense amplifier, a low decoder, a column decoder, a logic circuit, an address selection circuit, a read amplifier and a write amplifier, The indirect peripheral circuit, A semiconductor integrated circuit device comprising an input / output circuit. The method according to claim 1, The silicide layer, A semiconductor integrated circuit device comprising titanium silicide. The method according to claim 1, The gate electrode of the DRAM memory cell selection MISFET, the gate electrode of the MISFET constituting the direct peripheral circuit, the gate electrode of the MISFET constituting the indirect peripheral circuit, and the gate electrode of the MISFET constituting the logic integrated circuit, A semiconductor integrated circuit device, wherein the sheet resistance is 2? /? Or less. The method according to claim 1, The gate electrode of the DRAM memory cell selection MISFET, the gate electrode of the MISFET constituting the direct peripheral circuit, the gate electrode of the MISFET constituting the indirect peripheral circuit, and the gate electrode of the MISFET constituting the logic integrated circuit, A semiconductor integrated circuit device comprising a laminated film of a metal film and a polycrystalline silicon film. The method according to claim 1, A bit line connected to the memory cell selection MISFET of the DRAM; A first layer wiring connected to the MISFET constituting the direct peripheral circuit; A first layer wiring connected to the MISFET constituting the indirect peripheral circuit; And the first layer wiring connected to the MISFET constituting the logic integrated circuit is a wiring of the same layer manufactured by the same process. The method according to claim 1, A bit line connected to the memory cell selection MISFET of the DRAM; A first layer wiring connected to the MISFET constituting the direct peripheral circuit; A first layer wiring connected to the MISFET constituting the indirect peripheral circuit; And the first layer wiring connected to the MISFET constituting the logic integrated circuit has a sheet resistance of 2? /? Or less. The method according to claim 1, The direct peripheral circuit, the indirect peripheral circuit and the logic integrated circuit, A semiconductor integrated circuit device comprising a complementary MISFET. At least in the first region of the main surface of the semiconductor substrate, A memory array including a plurality of memory cells comprising a memory cell selection MISFET and an information storage capacitor connected in series thereto; DRAMs each having a direct peripheral circuit and an indirect peripheral circuit each including a MISFET are formed, In the second region of the main surface of the semiconductor substrate, A semiconductor integrated circuit device having a logic integrated circuit including a MISFET, A surface of a source and a drain of the MISFET constituting the indirect peripheral circuit of the DRAM; Silicide layers are formed on surfaces of the source and drain of the MISFET constituting the logic integrated circuit, A surface of a source and a drain of a memory cell selection MISFET constituting the memory cell of the DRAM; Silicide layers are not formed on the surfaces of the source and drain of the MISFET constituting the direct peripheral circuit of the DRAM, and the plugs and wirings connected to the MISFET of the logic circuit are made of the same material as the bit line following the memory cell selection MISFET. A semiconductor integrated circuit device, characterized in that formed. delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete