KR100456464B1 - A Data Recovery and Retiming Unit for Multi-Link using Multi-Phase Clocks - Google Patents

Abstract

The present invention relates to data reconstruction and retiming, and more particularly, to data reconstruction and retiming using a multi-phase clock that reconstructs an input binary data bit using a multi-phase clock and retimes it back to a reference bit clock. Relates to a device. To this end, the present invention, in a multi-link data recovery and retiming apparatus using a multi-phase clock, N-N (N is a natural number of two or more) multi-phase clock signal frequency-synchronized to the input data and the input data received N Phase comparison means for outputting two phase comparison result signals; Receives the input data and the N multi-phase clock signals and retimes the input data so that the timing is consistent with a phase comparison result signal output from the phase comparing means, and outputs data aligned with the N multi-phase clock signals. Delay compensation means; And the N multi-phase clock signals, the N phase comparison result signals output from the phase comparing means, the data aligned with the N multi-phase clock signals output from the delay compensating means, and a predetermined reference bit clock signal. And buffer buffer means for recovering the input data and absorbing alignment jitter and wander of the input data by selecting and combining data optimally retimed with the reference bit clock signal.

Description

A data recovery and retiming unit for multi-link using multi-phase clocks

The present invention relates to data reconstruction and retiming, and more particularly, multi-link data using a multi-phase clock for reconstructing input binary data bits using a multi-phase clock and retiming them back to a reference bit clock. A restoration and retiming apparatus.

In general, data transmitted over a link can be transmitted through a transmission line, such as a cable or printed circuit board (PCB), such as temperature variations, power supply noise, interference from ambient signals, or impedance irregularities in the transmission line. The factor includes the jitter component. In particular, data transmitted at high speed through multiple links may have different phases due to differences in transmission line lengths and characteristic differences between transmitting and receiving units, thereby making it difficult to process data using a single bit clock.

The data reconstruction and retiming device in multiple links reconstructs the phase of the reconstructed data to match the phase of the single-bit clock and the data reconstruction function that extracts the correct data values from the data including jitter input through each link. It is a device that performs the function of timing.

Conventional data recovery and retiming apparatuses are largely divided into analog methods using phase locked circuits and digital methods using digital phase aligners (Ref. RR Cordell et al., IEEE Journal of Solid-State Circuits, Vol. 23, No. 2, Apr. 1988.). The method of using the former phase synchronization circuit is a method of arranging one phase synchronization circuit per link to generate a bit clock synchronized with input data and retiming the input data using the same. This method has excellent stability and does not require frequency synchronization between the data transmitter and receiver, but the area occupied by the phase synchronization circuit makes it difficult to implement multiple links on a single chip, and generates a separate bit clock for each link. Because the data is retimed, a buffer buffer is needed to retime the retimed data back to a single system clock. However, since the phase relationship between the bit clocks generated in each link is not constant, the buffer buffer design becomes very complicated. On the other hand, the latter method of using a digital phase aligner has a disadvantage in that frequency synchronization is required between the data transmitter and receiver, but it is generally used in a multi-link design because only a digital circuit can be used and a small area can be realized.

As shown in FIG. 1, a data reconstruction and retiming apparatus using a conventional digital phase aligner includes a clock selector 10, a clock combiner 11, a determiner 12, and a buffer buffer 13. (HY Jung et al., US Patent 5,887,040). The clock selector 10 compares the phase of the input data and the multi-phase clock signal to select one or more clocks whose rising transition points are adjacent to the center of the input data among the multi-phase clock signals. The reason for selecting one or more clocks is to prepare for the case where the clock selection is not made due to instability that may occur during the phase comparison between the input data and the multi-phase clock signal. The clock synthesizing unit 11 receives one or more selection signals output from the clock selecting unit 10 and n multi-phase clocks to generate a synthesized bit clock using a combination circuit of the selected multi-phase clock signals. . The decision unit 12 is composed of a D-flip flop, which retimes the input data into a synthesized bit clock. The buffer buffer unit 13 retimes the data retimed with the synthesized bit clock back to the reference bit clock so that the output data is aligned with the reference bit clock.

However, the conventional data restoration and retiming apparatus as described above has the following problems.

First, since the conventional apparatus uses a clock obtained by synthesizing one or more clock signals as a bit clock, the jitter component of the data is transferred to the bit clock, which causes the duty cycle of the bit clock to be distorted. As a result, the phase relationship between the synthesized bit clock and the reference bit clock is not constant, and the design of the buffer buffer for resynchronizing the data synchronized with the synthesized bit clock to the reference bit clock is complicated, and the timing margin is caused by the duty cycle distortion. It was difficult to increase the data transfer rate because of the need to design larger.

Second, the conventional apparatus has a problem in that the time point at which the bit clock is selected due to the transition of data bits does not coincide with the time point at which the corresponding data bit is input to the determining unit. This resulted in a bit error as the jitter frequency could not be restored because the jitter component included in the data was reflected in real time.

Meanwhile, as another example of the conventional method using the digital phase aligner, a method of generating multi-phase input data from input data instead of the bit clock and retiming the data to the reference bit clock has been proposed (US Patent-CJ Georgiou). et al., US Pat. No. 5,668,830). The method generates N multi-phase input data by using the multi-phase data generator having the same structure as that of the multi-phase clock generator, and compares the phase between them and the reference bit clock to increase the reference bit clock among the multi-phase input data. This method selects and outputs the signal where the center of data is located at the point closest to the transition point. This method does not delay the bit clock, so that the data output from each link is aligned with respect to the reference bit clock without using the buffer buffer. However, as described below, the design of the multi-phase data generator is difficult. In general, the multi-phase data generator is formed by connecting a plurality of delay elements in series, and the delay elements use the same ones as the delay elements of the voltage controlled oscillator included in the phase locked circuit used to generate the bit clock. When the rising and falling transition time of the signal is small so as to be relatively small for one period of the signal, and thus appears in the form of a pulse, the delay time of the delay element has the same characteristic regardless of the frequency of the input signal. However, when the frequency of the input signal is increased and the rising and falling transition time of the signal becomes relatively large for one period of the signal and appears as a sine wave, the delay time varies depending on the frequency of the input signal. Therefore, when high-speed data of the Gbps level is input, the delay time of the delay element constituting the multi-phase data generator is different depending on the frequency of transition of the input data, thereby showing different characteristics according to the input pattern of the data.

On the contrary, since the clock signal is generated every transition period, unlike the data signal, the delay characteristic of the delay element is constant. Therefore, the multi-phase clock generation method is advantageous in design, compared to the multi-phase data generation method.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and its object is to use a multi-phase clock signal as it is, instead of using a clock synthesis method having a duty cycle distortion problem, so that a constant timing margin is always ensured so that stable operation is possible. At the same time, a high frequency jitter of up to 0.5 bit period or less can be made by facilitating the design of the buffer buffer section and selecting a bit clock from among the multi-phase clocks to determine the binary value of the input data at each rising or falling transition point of the input data. An apparatus for restoring and retiming data for multiple links using a multi-phase clock capable of restoring and retiming input data including a component is provided.

1 is a block diagram of a conventional data restoration and retiming apparatus.

2 is a block diagram of a data recovery and retiming apparatus according to the present invention.

3 is an embodiment of a data recovery and retiming apparatus according to the present invention.

4 is an embodiment of a multi-phase comparison unit.

5 is an embodiment of a retiming and extension portion.

6 is an embodiment of a valid section selection controller.

7 is an embodiment of delay compensation means.

8 is an embodiment of a determination unit.

9 is a timing diagram of a multi-phase comparison unit, a retiming and expansion unit, and an effective section selection control unit shown in FIGS. 4, 5, and 6.

10 is a timing diagram of the delay compensation means, the retiming and expansion unit, and the determination unit shown in FIGS. 7, 5, and 8.

Explanation of symbols on the main parts of the drawings

100: phase comparison means 101: multi-phase comparison unit

102: effective section selection control unit 200: delay compensation means

300: buffer buffer means 301: determination unit

30a: first retiming and extension part 30b: second retiming and extension part

N: Number of multi-phase clock signals X: Minimum integer greater than (N + 1) / 2

Y: Maximum integer less than (N + 1) / 2 HV, LV: Effective section selection control signal

CP [1], CP [2], ..., CP [N]: multi-phase clock

D [1], D [2], ..., D [N]: Sampled data

In order to achieve the above object, the present invention, in the multi-link data recovery and re-timing device for reconstructing the input data transferred to the multi-link using a multi-phase clock,

Comparing the input data with N multi-phase clock signals (N is a natural number of 2 or more) frequency-synchronized to the input data for each bit, and outputting a phase comparison signal representing a clock signal closest to the center of each bit. Phase comparing means;

Delay compensation means for retiming the input data to coincide with a phase of each of the N multi-phase clock signals to output input data having different N phases; And

The phase comparison signal output from the phase comparing means and the phase delay data output from the delay compensating means are retimed by a reference clock set as one of the multi-phase clock signals, respectively, and then logically summed to reconstruct the reference bit clock signal. And buffer buffer means for selecting and combining the timing bits.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail the present invention.

2 is a block diagram of a data restoration and retiming apparatus according to an embodiment of the present invention. As shown in FIG. 2, the apparatus according to the present invention includes a phase comparing means 100, a delay compensating means 200, and a buffer buffer means 300. The phase comparing means 100 comprises N multi-phase clocks CP [n] where N is the number of multi-phase clock signals (N is a natural number of two or more) that is frequency-synchronized with the input data Din. N? N is inputted, and N phase comparison result signals S [n] are output. The delay compensation means 200 receives the input data Din and the N multi-phase clocks CP [n], and compares the phase comparison result signal S [n] of the phase comparison means 100 with the input data Din. The data D [aligned with the N multi-phase clock signals CP [n] by retiming the input data Din with the N multi-phase clock signals CP [n] so as to have a matching timing. n]). In addition, the buffer buffer means 300 compares the phase D with the data D [n] aligned with the N multi-phase clock signals CP [n] that are outputs of the delay compensation means 200. The N phase comparison result signals S [n], the N multiphase clock signals CP [n], and the N multiphase clock signals CP [which are outputs of the means 100. n]) receives any reference bit clock signal CPref, one of which is selected, and selects and combines data reoptimized optimally to the reference bit clock CPref to recover the input data Din to output data Dout. ) Furthermore, the buffer buffer means 300 absorbs alignment jitter and wander of the input data Din.

3 is a block diagram of a data restoration and retiming apparatus according to another embodiment of the present invention. As shown in Fig. 3, the apparatus comprises a phase comparison means 100 comprising a multiphase comparator 101 and an effective section selection controller 102, a delay compensating means 200, two retiming and It is composed of a buffer buffer means 300 including the expansion portion (30a, 30b) and the determination portion 301.

The multi-phase comparison unit 101 receives input data Din and N multi-phase clock signals CP [n] where 1 ≦ n ≦ N, and inputs the input data Din and each of the multi-phase clocks. The phases between the signals CP [n] are compared, and as a result, N phase comparison result signals S [n] are output, and the valid section selection control unit 102 performs the N phase comparison result signals S. [0] is input to output valid period selection control signals HV and LV to select valid ones of the phase comparison result signals S [n].

The delay compensation means 200 receives the input data Din and the N multi-phase clocks CP [n], and compares the phase comparison result signal S [n] of the phase comparison means 100 with the input data Din. The data D [aligned with the N multi-phase clock signals CP [n] by retiming the input data Din with the N multi-phase clock signals CP [n] so as to have a matching timing. n]).

The first retiming and extension part 30a of the two retiming and extension parts 30a and 30b of the buffer buffer means 300 includes N sampled data D [n] from the delay compensation means 200. ) And the N multi-phase clock signals CP [n] are input and retimed to a reference bit clock CPref, and then 2N (N is even) to 2N-1 (N is odd) extended sampling. Data (D _-1 [X], D _-1 [X + 1], ..., D _-1 [N], D ₀ [1], D ₀ [2], ..., D ₀ [N ], D ₊₁ [1], D ₊₁ [2], ..., D ₊₁ [Y]), where N is the number of multiphase clock signals and X is greater than (N + 1) / 2 Minimum integer, Y is the maximum integer less than (N + 1) / 2). In addition, the second retiming and expansion unit 30b has the same structure as the retiming and expansion unit 30b, and includes the N phase comparison result signals S [which are input from the phase comparison unit 100. n]) and the N multi-phase clock signals CP [n], and the N phase comparison result signals S [n] are one of the multi-phase clock signals CP [n]. After retiming to a reference bit clock (CPref), these are 2N (N is even) to 2N-1 (N is odd) extended phase comparison result signals (S _-1 [X], S _-1 [X + 1). ], ..., S _-1 [N], S ₀ [1], S ₀ [2], ..., S ₀ [N], S ₊₁ [1], S ₊₁ [2] _,. .., S ₊₁ [Y]).

The determination unit 301 is configured to input the 2N to 2N-1 extended sampled data D ₋₁ [X] and D ₋₁ [X received from the first and second retiming and expansion units 30a and 30b. +1], ..., D _-1 [N], D ₀ [1], D ₀ [2], ..., D ₀ [N], D ₊₁ [1], D ₊₁ [2] , ..., D ₊₁ [Y] and the 2N to 2N-1 extended phase comparison result signals S _-1 [X], S _-1 [X + 1], ..., S _-1 [N], S ₀ [1], S ₀ [2], ..., S ₀ [N], S ₊₁ [1], S ₊₁ [2], ..., S ₊₁ [Y] ), The valid period selection control signals HV and LV, and the reference bit clock signal CPref inputted from the phase comparison means 100 are determined and output as binary values of the input data Din.

Hereinafter, the present invention will be described in detail through an embodiment of the case where the number N of the multi-phase clock signals is 7. Although the configuration of the present invention is different from the case where N is an even number and an odd number, the case of an odd number that is easy to configure is taken as an example, and the description of the even case will be described later.

First, set the following: The multi-phase clocks CP [1], CP [2], ..., CP [7] with N = 7 have the same frequency as the data bit rate, and CP [n] for an integer n with 1 ≦ n ≦ N. The delay time between CP [n + 1] is 1/7 of one period of data bits. Also, the CP [4] signal located at the center of CP [n] signals is defined as a reference bit clock. Multi-phase clocks can be easily generated by known techniques using multi-stage signal delay means.

FIG. 4 shows the multiphase comparison unit 101 when N = 7 as an embodiment of the multiphase comparison unit 101 of FIG. As shown in FIG. 4, the multiphase comparator 101 receives a CP [n] as a data input and a dual-edge triggered D-type flip-to receive input data Din as a clock input. The flop 11n and the inverted output of the flip-flop 11 (n-1) and the output of the flip-flop 11n when 2 ≤n ≤ 7 are input, and when n = 1 Data input is a two-input AND gate 12n receiving the inverted output of the flip-flop 117 and the output of the flip-flop 111 as an input, and an output T [n] of the AND gate 12n. A positive-edge triggered D-type flip-flop 13n receiving a CP [n] as a clock input, and a positive-receiving output of the flip-flop 13n as a data input and a CP [n] as a clock input. An edge triggered D flip-flop 14n, and a two-input OR gate 15n that receives an output of the flip-flop 13n and an output of the flip-flop 14n as inputs.

The flip-flop 11n samples and outputs a binary value of CP [n] at the time of rising or falling of Din. The AND gate 12n receives the inverted output of the flip-flop 11 (n-1) and the output of the flip-flop 11n and receives CP [n-1 at a rising or falling transition time of Din. T [n] is outputted as '1' only when] is '0' and CP [n] is '1', indicating that the rising transition of CP [n] is the closest clock to the center of the input data bit. The clock with the rising transition at the position closest to the center of the data bits will have a maximum error of 0.5D (where D is 1 / N of one period of data bits, N = 7).

The flip-flop 13n retimes the T [n] signal to CP [n] and the flip-flop 14n retimes the output of the flip-flop 13n to CP [n] once more. The OR gate 15n receives an output of the flip-flop 14n and an output of the flip-flop 15n and sets S [n] to '1' when at least one of the two outputs is '1'. And the interval of binary value '1' in S [n] is extended by one period of the clock compared to T [n] so that the flip-flop ( 11n) ensures that the previous output is maintained even if there is a problem of instability.

FIG. 5 is an embodiment of the first and second retiming and extension portions 30a and 30b of the buffer buffer means 300 of FIG. 3. As shown in FIG. 5, the retiming and extension unit 30 receives a S [n] signal output from the multi-phase comparison unit 10 as a data input and receives a CP [n] as a clock input. D-type flip-flop 31n and negative-edge triggered D-type flip-flop that receives an output of the flip-flop 31n as a data input and receives CP [4] as a clock input when 1 ≦ n ≦ 4 32n and, when 1 ≦ n ≦ 4, receives the output of the flip-flop 32n as a data input, and when 5 ≦ n ≦ 7, receives the output of the flip-flop 31n as a data input and CP A positive-edge triggered D flip-flop (34n) receiving [4] as a clock input, and when 5 ≤n ≤7, receives the output of the flip-flop (34n) as a data input and receives CP [4]. It consists of a positive-edge triggered D-type flip-flop (36n) received from the clock input.

In the case of 1 ≦ n ≦ 4, S [n] is retimed to CP [n] by the flip-flop 31n and then at the falling transition point of CP [4] by the flip-flop 32n. A phase comparison result signal S '[n] is generated which is retimed and then retimed by the flip-flop 33n at the rising transition point of CP [4] and retimed by a reference bit clock, where 5 < When n ≤ 7, S [n] is retimed to CP [n] by the flip-flop 31n, and then retimed at the time of the rising transition of CP [4] by the flip-flop 33n. The S '[n] signal is then retimed by the reference bit clock. The flip-flop 34n delays the S '[n] signal by one period to output S ₀ [n].

When 5 ≦ n ≦ 7, the flip-flop 35n outputs a signal S ₋₁ [n] delayed by 2 cycles in total for S ′ [n] by delaying S ₀ [n] by 1 cycle, When 1 ≤ n ≤ 3, S '[n] is outputted as S ₊₁ [n] so that a signal preceding the S ₀ [n] by one cycle is output. As a result, the seven phase comparison result signals S [n] are (2 × 7-1) extended phase comparison result signals S ₋₁ [5], S ₋₁ [6], and S ₋₁ [7]. ], S ₀ [1], S ₀ [2], ..., S ₀ [7], S ₊₁ [1], S ₊₁ [2], S ₊₁ [3].

On the other hand, when N is an even number, since there is no signal located in the center of CP [n] signals, it may be retimed to CP [1] or CP [N]. For example, the signals retimed by each of the N multi-phase clock signals CP [n], 1 ≦ n ≦ N, use N × N flip-flops to change the clock input of the flip-flop as follows. It is thus possible to eventually retime all of the CP [1]. That is, in order to retime the signal retimed with CP [i] to CP [1], data input / output of N flip-flops are connected in series, and the first flip-flop to the N-i + 1 flip-flop are connected. Input CP [i] to the clock input, CP [i-1] for the clock input of the N-i + 2th flip-flop, CP [i-2 for the clock input of the N-i + 3th flip-flop ] And finally the CP [1] is connected to the clock input of the Nth flip-flop to narrow the timing up to D, resulting in a retimed signal at CP [1], the reference bit clock.

In addition, in the case of using N / 2 flip-flops 35n similarly to the embodiment shown in FIG. 5, the N signals retimed by the reference bit clock as described above are 2N extended signals. You get Therefore, the retiming and expansion unit 30 of the present invention can be configured for any N, wherein the configuration of the extended signal is as follows.

S _-1 [X], S _-1 [X + 1], ..., S _-1 [N], S ₀ [1], S ₀ [2], ..., S ₀ [N], S ₊₁ [1], S ₊₁ [2], ..., S ₊₁ [Y] (where X is the smallest integer greater than (N + 1) / 2, Y is greater than (N + 1) / 2 Is the smallest minimum integer)

FIG. 6 is an embodiment of the effective section selection unit 102 of FIG. 3. As shown in FIG. 6, the effective section selecting unit 50 includes a latch 51n for receiving S [n] as a data input and a reset input for S [4] for n with n? A switch means 52n for turning on / off the current source 53n by receiving an output of 51n), a current source 533 connected to the load means 541 via a switch 523, and a switch 522 A current source 532 connected to the load means 541, a current source 531 connected to the load means 541 via a switch 521, and a current source 535 connected to the load means 542 via a switch 525. And a current source 536 connected to the load means 542 via a switch 526, a current source 537 connected to the load means 542 via a switch 527, between a power supply VCC and an A node. Connected between the load means 541, the power supply VCC, and a B node to provide a load to the current sources 531, 532, 533 through the switches 521, 522, 523 and a phase. The load means 542 for providing a load to the current sources 535, 536, 537 through switches 525, 526, 527 and the signals A and B voltage-dropped by the load means 541, 542 as positive and negative inputs, respectively. A differential amplification means 550 for receiving the input and amplifying the difference, and an output including the output of the differential amplifying means 550 and S [4] as an input and indicating that the section including S ₀ [1] is a valid interval. A two-input NOR gate 560 for outputting a section selection control signal LV, a section including S ₀ [7] by receiving the output of the NOR gate 560 and S [4] as an input is a valid section. It consists of a two-input NOR gate 570 that outputs an effective section selection control signal LH to be displayed, and the current amount of the current sources satisfies condition 1 as follows.

[Condition 1]

(Current source 531 = current source 535)> (current source 532 = current source 536)> (current source 533 = current source 537)

The latch 51n outputs '1' when S [n] becomes '1' one or more times while the reset input S [4] is '0', and then S [n] becomes '0'. If the reset input S [4] becomes '1' one or more times, the output will be '0' even if S [4] becomes '0'. Function to keep '.

When S [4] becomes '1', S ₀ [1] and S ₀ [7] do not become '1' at the same time. Therefore, the valid section selection signals LV and LH are both reset to '0'. . If S [4] is '0', switch 521 is on if S [1] has had a value of '1' more than once and S [7] has never had a value of '1' at all The switch 527 remains off so that the voltage level of the signal A becomes smaller than the voltage level of the signal B so that the output of the differential amplification means 550 becomes 0, LV is '1', and LH is '0'. ₀ [1] indicates that it is a valid selection signal. Similarly, if S [7] has had a value of '1' more than once and S [1] has never had a value of '1', then LV becomes '0', LH = '1' and S ₀ [7 ] Is a valid selection signal. If both S [1] and S [7] have a value of '1' more than once, the valid interval is selected by the conditions of S [2] and S [6], and S [2] If the conditions of S and S [6] are the same, the effective section is selected by the conditions of S [3] and S [5]. On the other hand, the difference in the amount of current in the current source 53n is to weight the comparison condition of S [n], and even if it is set variously, the fundamental principle of operation is the same.

7 is an embodiment of the delay compensation means 200 of FIG. As shown in FIG. 7, the delay compensating means 200 is composed of a positive-edge triggered D-type flip-flop 20n receiving Din as a data input and CP [n] as a clock input. Compensating the delay time by the D-flip-flop 13n in the multiphase comparison unit 101 shown in Fig. 4 by outputting the sampled data D [n] by judging the value at the rising transition point of CP [n]. Function. The configuration of the delay compensation means 200 depends on the configuration of the phase comparison means 100. The delay time to be compensated is a unit of bit periods of the input data, so that the delay compensation means 200 shown in FIG. By connecting a plurality in series, it is possible to appropriately compensate for the delay time in the phase comparing means 100.

The data D [n] aligned and sampled to N CP [n] input from the delay compensating means 200 is one of the components of the buffer buffer means 300, and is shown in FIG. Extended sampled data D _-1 [5], D _-1 [6], D, which are input to the retiming and extension part having the same structure as the extension part 30a or 30b and are aligned to the reference bit clock CP [4]. _{Convert to -1} [7], D ₀ [1], D ₀ [2], ..., D ₀ [7], D ₊₁ [1], D ₊₁ [2], D ₊₁ [3] And output.

8 is one embodiment of the determination unit 40 that is one of the components of the buffer buffer means 300 of FIG. As shown in FIG. 8, the determination unit 301 is extended with the sampled data D ₋₁ [5] output from the retiming and expansion unit 30a and the output from the retiming and expansion unit 30b. Extended sampled data D ₊ output from the three-input AND gate 401 to the retiming and expansion unit 30a, which takes in the phase comparison result signal S- ₁ [5] and the SW- ₁ [5] signal to be described later. ₁ [3] and retiming, and 3-input aND gate 413 as a phase comparison result signal S ₊₁ [3] and input the SW ₊₁ [3] signal to be described later extension outputted from the extension unit (30b), A (2x7-1) input OR gate 420 that receives the outputs of the AND gates 401 to 413, and an output of the OR gate 420 as a data input and clock a CP [4] which is a reference bit clock. It consists of a positive-edge triggered D flip-flop 430 as an input.

Validity period selection signal SW _-1 [5] to SW ₊₁ [3] is for receiving the phase comparison result signals of the S ₀ [1] to S ₀ [7] and the effective block selection control signals LV and LH S ₀ [ When n] is '1', a total of seven extended phase comparison signals based on S ₀ [n] are combined and generated as follows to make a valid period.

SW _-1 [5] = (LV AND S ₀ [1])

SW _-1 [6] = (LV AND S ₀ [1]) OR S ₀ [2]

SW _-1 [7] = (LV AND S ₀ [1]) OR S ₀ [2] OR S ₀ [3]

SW ₀ [1] = (LV AND S ₀ [1]) OR S ₀ [2] OR S ₀ [3] OR S ₀ [4]

SW ₀ [2] = (LV AND S ₀ [1]) OR S ₀ [2] OR S ₀ [3] OR S ₀ [4] OR S ₀ [5]

SW ₀ [3] = (LV AND S ₀ [1]) OR S ₀ [2] OR S ₀ [3] OR S ₀ [4] OR S ₀ [5] OR S ₀ [6]

SW ₀ [4] = (LV AND S ₀ [1]) OR S ₀ [2] OR S ₀ [3] OR S ₀ [4] OR S ₀ [5] OR S ₀ [6] OR (LH AND S ₀ [7])

SW ₀ [5] = S ₀ [2] OR S ₀ [3] OR S ₀ [4] OR S ₀ [5] OR S0 [6] OR (LH AND S ₀ [7])

SW ₀ [6] = S ₀ [3] OR S ₀ [4] OR S ₀ [5] OR S ₀ [6] OR (LH AND S ₀ [7])

SW ₀ [7] = S ₀ [4] OR S ₀ [5] OR S ₀ [6] OR (LH AND S ₀ [7])

SW ₊₁ [1] = S ₀ [5] OR S ₀ [6] OR (LH AND S ₀ [7])

SW ₊₁ [2] = S ₀ [6] OR (LH AND S ₀ [7])

SW ₊₁ [3] = (LH AND S ₀ [7])

In addition, the effective interval region is shown in FIGS. 9 and 10 to be described later. For example, at CP [4] reference time t ₂ , D ₀ [1] and D ₀ [2] have a binary value of bit 2. S ₀ [1] and S ₀ [2], SW _-1 [5], SW _-1 [6], SW _-1 [7], SW ₀ [1], SW ₀ [2], SW ₀ [3 ], SW ₀ [4], and SW ₀ [5] are '1', so the outputs of the AND gates 404, 405 are '1'. Accordingly, the output of the OR gate 420 becomes bit 2, so that the output Dout of the decision unit 40 represents the binary value of bit 2 retimed to CP [4].

9 is a timing diagram of the multiphase comparison unit, the retiming and expansion unit, and the effective section selection control unit shown in FIGS. 4, 5, and 6; In the timing diagram shown in FIG. 9, it is assumed that Din has the following jitter component.

Din Bit0 Bit1 Bit2 Bit3 Bit 4 Bit 5 Bit6 Bit7 Bit8 Bit9 Jitter 0 -1D -1D + 1D + 1D 0 -1D 0 0 0

(Where D is 1 / N of 1 data bit cycle, N = 7)

As shown in FIG. 9, the binary values of CP [n] are 0, 1, 1, 1, X, 0, 0, respectively, where the transition time of Din bit 0 is 0, where X is a binary value. In this case, the signals T [n] in the multiphase comparator 101 become 0, 1, 0, 0, 0, 0, 0, respectively. Therefore, the output S [n] of the multiphase comparator 101 is as shown in FIG. The hatched portion of the S [n] signal waveform represents a section in which the phase comparison result is maintained for one bit period by the flip-flop 14n and the OR gate 15n in the multiphase comparator 101. The S [n] signals retimed by CP [n], respectively, are the signals S '[n] retimed by CP [4], which are the reference bit clocks by the retiming and extension sections 30a and 30b. N = 7 S '[n] signals are converted into 2x7-1 extended phase comparison signals S ₋₁ [5], S ₋₁ [6], S ₋₁ [7], and S ₀ [1] ], S ₀ [2], ..., S ₀ [7], S ₊₁ [1], S ₊₁ [2], S ₊₁ [3]. Since the extended phase comparison result signal represents a phase comparison result for a time domain of a 2-bit period, the phase comparison result is overlapped in the set of extended phase comparison result signals as shown in FIG. 9. That is, since S ₀ [n] is a result of phase comparison in the time domain of 1-bit period, there is at least one n where binary values of S ₀ [n] become '1' due to the rising or falling transition of Din. do. When more than one value of n exists, the multi-phase comparator 10 maintains the phase comparison result by one bit period. For example, in the CP [4] reference time t ₆ in FIG. 9, when the S '[n] signal waveform is viewed, S' [2] and S '[3] become' 1 'at the same time, and the corresponding Din reference time t _{6 is shown.} In the phase relationship between Din and CP [n], CP [2] has a maximum error range of 0.5D while rising transition occurs in the center of bit 6 of Din. CP [3] has a maximum error range of 1.5D. It can be seen that rising transition occurs in the center of bit 6 of Din, so that CP [2] and CP [3] are valid clocks for determining the binary value of bit Din. However, as CP [2] and CP [3] are signals adjacent to each other at a time interval of D, CP [7] and CP [1] are signals adjacent to each other at a time interval of D. If we look at the S '[n] signal waveform at time t ₂ , S' [1] and S '[7] become' 1 'at the same time, and the phase relationship between Din and CP [n] at the corresponding Din reference time t ₂ As a result, CP [1] has a maximum error range of 0.5D and a rising transition occurs at the center of bit Din 6, and CP [7] has a maximum error range of 1.5D and a rising transition at the center of bit Din 6 Is generated, CP [1] and CP [7] should be a valid clock for determining the binary value of Din bit 2. However, CP [7] here is a data bit section one bit earlier than CP [1]. CP [7] becomes an invalid clock signal because it is a clock signal having a rising transition at. Therefore, as shown in FIG. 9, when S ₀ [n] is '1' for n having 2 ≦ n ≦ 6, seven extended phase comparison result regions are selected as valid intervals around S ₀ [n]. , when n = 1 or n = 7, the valid section is determined by the valid section selection control signal provided by the valid section selector 50.

FIG. 10 is a timing diagram of the delay compensation means 200 and the retiming and expansion unit 30a shown in FIGS. 7 and 5. In the timing diagram shown in FIG. 10, Din is the same as Din shown in FIG. As shown in FIG. 10, the delay compensation means 200 samples the Din signal into a CP [n] signal and outputs a D [n] signal. Therefore, the D [n] signal becomes a retimed signal at CP [n], respectively. For example, the sampled data D [n] in the section indicated by box in the CP [n] signal waveform is bit 0, bit 0, and bit, respectively. 0, X, bit 1, and bit 1. Here, X means that the data transition occurs at the time of the rising transition of the clock, so that the binary value of the output of the flip-flop 20n in the delay compensation means 200 is unknown. In addition, in FIG. 10, N = 7 D [n] signals are converted by the retiming and expansion unit 30a into seven retimed signals D '[n] by CP [4], which is a reference bit clock. And converted back to 2x7-1 extended sampled data. As in the case of the extended phase comparison result signal shown in FIG. 9, sampling data is also overlapped in the extended sampled data signal shown in FIG. 10. The valid sampling data is determined by the determination unit 301 described above by the extended phase comparison result signal and the valid section selection control signal.

The present invention has the following unique effects by using the above configuration.

First, it is easy to increase the data bit rate because the duty cycle is kept constant by not using a synthesized clock during data restoration and retiming, thereby ensuring timing margin.

Second, since the multi-phase clock is used as it is during the data restoration and retiming process, the phase relationship between the clock signals is fixed, so that the buffer buffer means can be easily configured and the operation is stable.

Third, by selecting a bit clock from among the multi-phase clocks to determine the binary value of the input data at each rising or falling transition time of the input data, the input data including the high frequency jitter component up to 0.5 bit period or less is restored. And retiming, and the buffer buffer means can recover and retime the wander component to the low frequency jitter component of up to one bit period.

Claims (5)

In the multi-link data recovery and retiming apparatus for recovering and retiming the input data transferred to the multi-link using a multi-phase clock, Comparing the input data with N multi-phase clock signals (N is a natural number of 2 or more) frequency-synchronized to the input data for each bit, and outputting a phase comparison signal representing a clock signal closest to the center of each bit. Phase comparing means; Delay compensation means for retiming the input data to coincide with a phase of each of the N multi-phase clock signals to output input data having different N phases; And The phase comparison signal output from the phase comparing means and the phase delay data output from the delay compensating means are retimed by a reference clock set as one of the multi-phase clock signals, respectively, and then logically summed to reconstruct the reference bit clock signal. And a buffer buffer means for selecting and combining the timing bits for outputting the multi-link data recovery and retiming apparatus. The method of claim 1, wherein the delay compensation means Multi-link using a multi-phase clock, characterized in that each of the N multi-phase clock signal input to the clock stage, and outputs the delayed input data according to the clock signal input to the clock stage Device for data restoration and retiming. The method of claim 1, And a reference clock signal of the buffer buffer means is a clock signal having a phase located at the center of the N multi-phase clock signals. The method of claim 1, wherein the phase comparison means, Comparing the input data with N multi-phase clock signals (N is a natural number of 2 or more) frequency-synchronized to the input data for each bit, and outputting a phase comparison signal representing a clock signal closest to the center of each bit. Multi-phase comparison unit; And A multiphase clock is divided into an upper section and a lower section on the basis of a reference clock, and the N phase comparison result signals output from the multiphase comparator are input to receive a clock signal corresponding to each bit string of the input data. And a valid section selection control unit for outputting a valid section selection control signal indicating whether the upper section corresponds to the upper section or the lower section. The method of claim 1, wherein the buffer buffer means, 2N (N is an even number) to 2N-1 (retimed by the reference bit clock signal after receiving the data aligned with the N multi-phase clock signals and the N multi-phase clock signals outputted from the delay compensating means). N is a first retiming and expansion unit for outputting an odd number of extended sampling data signals; 2N (N is even) to 2N-1 (N is odd) re-timed by the reference bit clock by receiving the N phase comparison result signals and the N multi-phase clock signals output from the phase comparator A second retiming and extension unit for outputting an extended phase comparison result signal; And A determination unit configured to receive the extended sampling data signal and the extended phase comparison result signal respectively output from the reference bit clock signal, the first and second retiming and expansion units, and determine a binary value of the input data; Data recovery and retiming device for multi-link using a multi-phase clock comprising a.