KR100454633B1 - Treatment method of wafer surface - Google Patents
Treatment method of wafer surface Download PDFInfo
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- KR100454633B1 KR100454633B1 KR10-2002-0000491A KR20020000491A KR100454633B1 KR 100454633 B1 KR100454633 B1 KR 100454633B1 KR 20020000491 A KR20020000491 A KR 20020000491A KR 100454633 B1 KR100454633 B1 KR 100454633B1
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- substrate
- palladium
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- semiconductor substrate
- electroless plating
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 238000007772 electroless plating Methods 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 230000003213 activating effect Effects 0.000 claims abstract description 13
- 239000003054 catalyst Substances 0.000 claims abstract description 13
- 238000004381 surface treatment Methods 0.000 claims abstract description 12
- 239000003638 chemical reducing agent Substances 0.000 claims abstract description 7
- 229910021645 metal ion Inorganic materials 0.000 claims abstract description 7
- 238000004140 cleaning Methods 0.000 claims abstract description 4
- 239000008139 complexing agent Substances 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims abstract description 4
- 239000003446 ligand Substances 0.000 claims abstract description 4
- 239000012190 activator Substances 0.000 claims abstract description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 38
- PIBWKRNGBLPSSY-UHFFFAOYSA-L palladium(II) chloride Chemical compound Cl[Pd]Cl PIBWKRNGBLPSSY-UHFFFAOYSA-L 0.000 claims description 28
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 25
- 229910052802 copper Inorganic materials 0.000 claims description 25
- 239000010949 copper Substances 0.000 claims description 25
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 19
- 229910052763 palladium Inorganic materials 0.000 claims description 19
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 230000004913 activation Effects 0.000 abstract description 5
- 230000008569 process Effects 0.000 abstract description 5
- 230000008859 change Effects 0.000 description 10
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 6
- 238000011534 incubation Methods 0.000 description 6
- 238000007747 plating Methods 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 238000007654 immersion Methods 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 4
- 239000008367 deionised water Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000004630 atomic force microscopy Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 229910021641 deionized water Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- VMQMZMRVKUZKQL-UHFFFAOYSA-N Cu+ Chemical compound [Cu+] VMQMZMRVKUZKQL-UHFFFAOYSA-N 0.000 description 1
- 101100396546 Neurospora crassa (strain ATCC 24698 / 74-OR23-1A / CBS 708.71 / DSM 1257 / FGSC 987) tif-6 gene Proteins 0.000 description 1
- 101150003085 Pdcl gene Proteins 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- IXCSERBJSXMMFS-UHFFFAOYSA-N hcl hcl Chemical compound Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 1
- 238000001000 micrograph Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- -1 palladium ions Chemical class 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemically Coating (AREA)
Abstract
무전해 도금 전에 실시하는 기판 표면 처리 방법에 관하여 개시한다. 본 발명에 따른 기판 표면 처리 방법은: 반도체 기판을 마련하는 단계와, 반도체 기판의 표면에 형성된 자연 산화막을 식각하여 세정하는 단계와, 세정된 반도체 기판을 환원제를 산화시키는 데 필요한 촉매와 기판의 표면을 활성화하는 활성화제와 상기 촉매의 금속 이온과 리간드를 형성하는 착화제로 이루어지는 활성화 용액에 침지시켜 상기 표면을 활성화하는 단계를 포함하는 것을 특징으로 한다. 본 발명에 의하면, 무전해 도금을 실시하는 반도체 배선 공정의 전처리 공정으로서 기판 표면 처리를 실시함으로써, 기판 표면에 균일한 촉매층을 형성하여 낮은 면저항을 갖는 것과 동시에 표면이 고른 무전해 도금막을 형성할 수 있어서 반도체의 질적 향상을 도모 할 수 있다.A substrate surface treatment method performed before electroless plating is disclosed. A substrate surface treatment method according to the present invention comprises the steps of: preparing a semiconductor substrate, etching and cleaning a natural oxide film formed on the surface of the semiconductor substrate, and a surface of the catalyst and the substrate required to oxidize the cleaned semiconductor substrate to a reducing agent And activating the surface by immersing in an activation solution consisting of an activator for activating and a complexing agent for forming a ligand with a metal ion of the catalyst. According to the present invention, by performing a substrate surface treatment as a pretreatment step of a semiconductor wiring process in which electroless plating is performed, a uniform catalyst layer can be formed on the surface of the substrate to form an electroless plated film having a low sheet resistance and an even surface. Therefore, the quality of the semiconductor can be improved.
Description
본 발명은 기판 표면 처리 방법에 관한 것으로서, 특히 무전해 도금 전에 실시하여 무전해 도금막 질을 향상하는 기판 표면 처리 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate surface treatment method, and more particularly, to a substrate surface treatment method performed before electroless plating to improve electroless plating film quality.
지금까지는 대체로 직접회로 내 배선 재료로서 알루미늄을 사용하였다. 그러나, 직접회로 내 소자의 직접도가 증가함에 따라 배선 폭은 점차로 감소하게 되고 이로써, 알루미늄의 큰 문제점이 드러나게 되었다. 알루미늄은 상대적으로 높은 비저항을 갖게 되어 전류가 효과적으로 흐르지 못하며, 열이 발생하여 소자의 손상을 가져온다. 또한, 전자 이동에 의한 원자 이동 현상(electromigration)이 일어나는 문제점이 발생된다.Until now, aluminum has generally been used as a wiring material in integrated circuits. However, as the directivity of the devices in the integrated circuit increases, the wiring width gradually decreases, thereby revealing a big problem of aluminum. Aluminum has a relatively high resistivity, which prevents current from flowing effectively and generates heat, resulting in damage to the device. In addition, a problem arises in that an electron migration phenomenon occurs due to electron transfer.
그리하여, 최근에, 배선 재료를 알루미늄에서 구리로 대체하여 구리의 알루미늄에 비해 낮은 비저항을 갖는 특성으로 인해 저항-축전 지연(RC delay)을 감소시켜 집적회로를 보다 빠르게 동작 가능함으로써, 차세대 로직칩(logic chip)과 디램(DRAM)반도체의 성능을 향상시킬 수 있었다. 또한, 구리는 전기이동에 대한 저항성(electromigration resistance)이 좋기 때문에 소자 내에서의 금속 회로의 단락을 줄일 수 있어 알루미늄을 대신하여 0.18㎛이하의 소자에서 그 사용 가능성을 인정받고 있다. 여기서, 구리가 소자 내로 확산이 매우 잘 일어나는 특성을 갖고 있기 때문에 확산을 막기 위해서 반도체 기판 상에 일반적으로 확산 장벽층을 증착하여 배선 공정을 실시하게 된다.Thus, in recent years, wiring materials have been replaced from aluminum to copper to reduce the resistance-capacitance delay (RC delay) due to the characteristics of lower resistivity compared to aluminum of copper, thereby enabling faster operation of integrated circuits. logic chip) and DRAM (DRAM) semiconductor performance could be improved. In addition, since copper has good electromigration resistance, the short circuit of the metal circuit in the device can be reduced, and the use of copper in the device of 0.18 μm or less is recognized in place of aluminum. In this case, since copper has a property of diffusion into the device very well, in order to prevent diffusion, a diffusion barrier layer is generally deposited on a semiconductor substrate to perform a wiring process.
구리를 이용한 배선 방법에는 여러 가지가 있으나, 비용적인 면이나 방법적인 면에서도 간단한 습식법으로서 무전해 도금액을 이용하는 무전해 도금 방법을 많이 사용하고 있는 데, 이러한 무전해 도금은 제이구리이온을 포함하는 용액에 환원제를 첨가하여 환원된 구리를 웨이퍼 표면에 증착시키는 방법이다. 이때, 구리 무전해 도금이 효과적으로 일어나기 위해서는 웨이퍼 표면에 환원제를 산화시키는 데 필요한 촉매가 존재해야 한다. 여기서, 웨이퍼 상에 증착된 확산 장벽층으로는 촉매 역할을 수행할 수가 없기 때문에 무전해 구리 도금을 실시하기 전에 표면을 활성화하는 표면 처리 과정이 요구되고 있다.Although there are many ways of wiring using copper, in terms of cost and method, many electroless plating methods using an electroless plating solution are used as a simple wet method. The electroless plating is a solution containing a cuprous ion. A method of depositing reduced copper on the wafer surface by adding a reducing agent to the wafer. At this time, in order for copper electroless plating to occur effectively, a catalyst necessary for oxidizing a reducing agent must be present on the wafer surface. Here, since the diffusion barrier layer deposited on the wafer cannot serve as a catalyst, a surface treatment process for activating a surface before electroless copper plating is required.
따라서, 본 발명이 이루고자 하는 기술적 과제는, 무전해 구리 도금을 이용해 반도체 배선을 형성하는 기판의 표면을 활성화시키는 기판 표면 처리 방법을 제공하는 데 있다.Accordingly, the present invention has been made in an effort to provide a substrate surface treatment method for activating a surface of a substrate for forming a semiconductor wiring by using electroless copper plating.
도 1은 본 발명에 따라 불산 용액에 침지된 시간의 변화에 따른 기판의 면저항 변화를 나타내는 그래프;1 is a graph showing a sheet resistance change of a substrate with a change in time immersed in a hydrofluoric acid solution according to the present invention;
도 2a 내지 도 2f는 본 발명에 따른 팔라듐 활성화 용액 내의 염화팔라듐의 최적 조성을 알아보기 위한 기판의 원자 탐침 현미경 사진들;2A-2F are atomic probe micrographs of a substrate for determining the optimal composition of palladium chloride in a palladium activated solution according to the present invention;
도 3은 본 발명에 따른 팔라듐 활성화 용액 내의 염화 팔라듐 농도의 변화에 따라 구리 무전해 도금에서의 잠복기간을 나타내는 그래프;3 is a graph showing the incubation period in copper electroless plating according to the change of the palladium chloride concentration in the palladium activation solution according to the present invention;
도 4는 본 발명에 있어서의 염화 팔라듐 농도의 변화에 따른 구리 무전해 도금한 기판 표면의 비저항을 나타내는 그래프; 및4 is a graph showing the specific resistance of the surface of a copper electroless plated substrate with a change in the palladium chloride concentration in the present invention; And
도 5는 본 발명에 있어서의 염화 팔라듐 농도의 변화에 따른 구리 무전해 도금한 기판 표면의 RMS 거칠기를 나타내는 그래프이다.5 is a graph showing the RMS roughness of the surface of the copper electroless plated substrate with the change of the palladium chloride concentration in the present invention.
상기 기술적 과제를 달성하기 위한 본 발명에 따른 환원제의 산화에 의해 발생하는 전자를 이용해 금속 이온을 환원시켜 반도체 기판에 도금하는 무전해 도금을 실시하기 전의 기판 표면 처리 방법은: 반도체 기판을 마련하는 단계와; 상기 반도체 기판의 표면에 형성된 자연 산화막을 식각하여 세정하는 단계와; 세정된 상기 반도체 기판을, 상기 환원제를 산화시키는 데 필요한 촉매로서의 염화팔라듐과 상기 기판의 표면을 활성화하는 활성화제로서의 불산과 상기 촉매의 금속 이온과 리간드를 형성하는 착화제로서의 염산으로 이루어지는 활성화 용액에, 침지시켜 상기 표면을 활성화하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above technical problem, a method of treating a substrate surface before performing electroless plating in which metal ions are reduced and plated onto a semiconductor substrate using electrons generated by oxidation of a reducing agent according to the present invention comprises the steps of: preparing a semiconductor substrate Wow; Etching and cleaning the native oxide film formed on the surface of the semiconductor substrate; The cleaned semiconductor substrate is placed in an activating solution consisting of palladium chloride as a catalyst necessary for oxidizing the reducing agent, hydrofluoric acid as a activator for activating the surface of the substrate and a complexing agent for forming a ligand with metal ions of the catalyst. It is characterized in that it comprises a step of activating the surface by dipping.
이때, 상기 촉매의 금속 이온은 팔라듐, 은, 금, 구리, 또는 백금으로 이루어진다.At this time, the metal ion of the catalyst is made of palladium, silver, gold, copper, or platinum.
이하에서, 본 발명의 바람직한 실시예를 첨부한 도면들을 참조하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.
반도체 금속 배선을 무전해 도금으로 형성 시에, 전처리 공정으로서 기판의 표면을 활성화시키는 본 발명에 따른 기판 표면 처리 방법에 있어서는, 먼저, 실리콘 웨이퍼 상에 150Å 두께의 티타늄을 형성한 후에 100Å 두께의 질화티타늄을 확산 장벽층으로 형성한 질화티타늄/티타늄/실리콘 구조의 기판을 마련한다. 이때, 본 발명에 따른 실시예에서는 질화티타늄(TiN)으로 확산 장벽층을 형성하였지만, 이에 한정되는 것은 아니어서, 확산 장벽층으로 질화탄탈륨(TaN) 또는 탄탈륨(Ta) 등이 사용되어도 좋다.In the substrate surface treatment method according to the present invention in which the surface of the substrate is activated as a pretreatment step when the semiconductor metal wiring is formed by electroless plating, first, 150 nm thick titanium is formed on a silicon wafer and then 100 nm thick nitride. A substrate having a titanium nitride / titanium / silicon structure in which titanium is formed as a diffusion barrier layer is prepared. In this embodiment, the diffusion barrier layer is formed of titanium nitride (TiN), but the present invention is not limited thereto. For example, tantalum nitride (TaN) or tantalum (Ta) may be used as the diffusion barrier layer.
다음에, 상기와 같이 마련된 기판의 질화티타늄 표면에 공기 중의 산소와 만나 자연 발생적으로 생성된 산화 티타늄막을 제거하기 위해, 불산 및 이온제거수(De-Ionized Water)로 이루어진 1%의 불산 용액에 10분간 침지시킨 후, 다시 이온제거수에서 침지한 다음에, 질소(N2) 기체로 기판 표면을 건조시킴으로써 질화티타늄 표면을 세정한다.Next, in order to remove the naturally occurring titanium oxide film by meeting oxygen in the air on the titanium nitride surface of the substrate prepared as described above, 10% in a 1% hydrofluoric acid solution composed of hydrofluoric acid and de-ionized water was added. After being immersed for a minute, it is again immersed in deionized water, and then the titanium nitride surface is cleaned by drying the substrate surface with nitrogen (N 2 ) gas.
도 1은 본 발명에 따라 불산 용액에 침지된 시간의 변화에 따른 기판의 면저항 변화를 나타내는 그래프이다.1 is a graph showing a change in sheet resistance of a substrate according to a change in time immersed in a hydrofluoric acid solution according to the present invention.
도 1을 참조하면, 침지된 시간이 5.7분 정도 지나자 면저항이 증가하기 시작하는 것을 볼 수 있는 데, 이것으로 산화티타늄막이 모두 식각되고 질화티타늄이 식각되기 시작하는 것을 알 수 있다. 이렇게 면저항을 측정하여, 불산 용액에 기판을 침지하는 시간을 정하게 된다. 이때, 산화티타늄막이 모두 식각되기 시작하는 침지 시간은 5.7분 정도에서지만, 본 발명의 실시 예에서의 침지 시간은 산화티타늄막을 100% 모두 식각 해야 하는 것을 고려하여 10분으로 정하였다.Referring to FIG. 1, when the immersion time passes about 5.7 minutes, the sheet resistance starts to increase, indicating that all of the titanium oxide film is etched and titanium nitride begins to be etched. Thus, sheet resistance is measured, and time to immerse a board | substrate in hydrofluoric acid solution is determined. At this time, the immersion time at which all of the titanium oxide film starts to be etched is about 5.7 minutes, but the immersion time in the embodiment of the present invention was set to 10 minutes in consideration of etching all of the titanium oxide film.
그 다음에, 염화팔라듐(PdCl2) 0.1g/L, 50%의 불산(HF) 5mL/L, 및 35%의 염산(HCl) 3mL/L가 혼합된 팔라듐 활성화 용액에 20초간 침지시킨 후에, 이온제거수에서 10초 동안 침지를 두 번 실시함으로써 질화티타늄 표면을 활성화한다.Then, 20 g of palladium chloride (PdCl 2 ), 5 mL / L of 50% hydrofluoric acid (HF), and 3 mL / L of 35% hydrochloric acid (HCl) were immersed in a mixed palladium activated solution for 20 seconds. The titanium nitride surface is activated by immersion twice in deionized water for 10 seconds.
이러한 팔라듐 활성화 용액에 질화티타늄으로 확산 장벽층을 형성한 상기 기판이 침지되면, 불산과 질화티타늄이 반응하여 화학식 1과 같이 활성화되게 된다. 이때, Ti0의 첨자 '0'은 티타늄 원자를 나타낸다.When the substrate having the diffusion barrier layer formed of titanium nitride is immersed in the palladium activating solution, the hydrofluoric acid and titanium nitride react to be activated as in Chemical Formula 1. At this time, the subscript '0' of Ti 0 represents a titanium atom.
(PdCl4)2-+ 2e-→Pd↓+ 4Cl- (PdCl 4) 2- + 2e - → Pd ↓ + 4Cl -
여기서, 염산은 상술한 화학식 1에서와 같이 팔라듐 이온과 리간드를 형성하는 착화제로서 사용되며, 팔라듐과 치환 반응을 통해 기판의 표면에 팔라듐이 증착되는 것이다. 이때, 기판 표면에 증착되는 금속으로 팔라듐을 이용하고 있는 데, 이에 한하지 않고, 은, 금, 구리, 또는 백금 등을 이용할 수 있다. 이렇게, 기판 표면을 세정하고 활성화시키는 전처리 과정을 거침으로써, 반도체 구리 배선의 질은 더욱 향상하게 된다.Here, hydrochloric acid is used as a complexing agent to form a ligand with palladium ions as in Formula 1 above, palladium is deposited on the surface of the substrate through a substitution reaction with palladium. At this time, palladium is used as the metal deposited on the surface of the substrate, but not limited thereto, and silver, gold, copper, platinum, or the like may be used. Thus, by going through a pretreatment process of cleaning and activating the substrate surface, the quality of the semiconductor copper wiring is further improved.
본 발명에 따른 본 실시예에서는 팔라듐 활성화 용액 내의 염화팔라듐의 농도를 0.1g/L로 하였지만, 0.01g/L∼0.5g/L범위에서 최적 염화팔라듐의 농도를 도면들을 참조하여 살펴본다.In the present embodiment according to the present invention, the concentration of palladium chloride in the palladium activating solution was 0.1 g / L, but the optimal concentration of palladium chloride in the range of 0.01 g / L to 0.5 g / L will be described with reference to the drawings.
도 2a 내지 도 2f는 본 발명에 따른 팔라듐 활성화 용액 내의 염화팔라듐의 최적 조성을 알아보기 위한 기판의 원자 탐침 현미경(atomic force microscopy, AFM) 사진들이다. 도 2a는 염화팔라듐의 농도가 0.01g/L인 경우이며, 도 2b는 염화팔라듐의 농도가 0.025g/L인 경우이고, 도 2c는 염화팔라듐의 농도가 0.05g/L인 경우이고, 도 2d는 염화팔라듐의 농도가 0.1g/L인 경우이고, 도 2e는 염화팔라듐의 농도가 0.2g/L인 경우이고, 도 2f는 염화팔라듐의 농도가 0.5g/L인 경우이다.2A to 2F are atomic force microscopy (AFM) photographs of a substrate for determining an optimal composition of palladium chloride in a palladium activated solution according to the present invention. FIG. 2A illustrates a case where the concentration of palladium chloride is 0.01 g / L, FIG. 2B illustrates a case where the concentration of palladium chloride is 0.025 g / L, FIG. 2C illustrates a case where the concentration of palladium chloride is 0.05 g / L, and FIG. 2D. Is the case where the concentration of palladium chloride is 0.1g / L, Figure 2e is the case when the concentration of palladium chloride is 0.2g / L, Figure 2f is the case when the concentration of palladium chloride is 0.5g / L.
도 2a 내지 도 2f를 참조하면, 염화팔라듐의 농도가 0.1g/L일 때부터, 도 2d에서 보는 것과 같이 기판 전(全)표면에 균일하게 팔라듐이 증착되는 것을 알 수 있었다.2A to 2F, it can be seen that palladium is uniformly deposited on the entire surface of the substrate, as shown in FIG. 2D, when the concentration of palladium chloride is 0.1 g / L.
또한, 팔라듐으로 활성화된 용액에서 활성화된 기판을 무전해 도금할 때에, 무전해 도금 용액에 기판을 담근 시간부터 무전해 도금이 일어나기까지의 시간차이를 잠복기간(incubation time)이라 한다. 무전해 도금에서 이러한 잠복기간이 발생하는 이유는 구리 무전해 도금을 예를 들면, 비저항이 높은 표면에서 도금이 일어날 때는 도금 속도가 느리다가 본격적으로 비저항이 낮은 구리 표면에서 구리 무전해 도금이 일어나면 도금 속도가 빨라져서 시간차가 생기기 때문이다. 여기서, 팔라듐이 기판 전(全)표면에 균일하게 증착되면, 도금 속도가 빨라져서 잠복기간은 줄어들게 되는 것이다.In addition, when electroless plating an activated substrate in a palladium-activated solution, the time difference from the time when the substrate is immersed in the electroless plating solution until the electroless plating occurs is called an incubation time. The reason for this incubation period in electroless plating is copper electroless plating, for example, when plating occurs on a high resistivity surface, the plating rate is slower, but when copper electroless plating occurs in earnest on a low resistivity copper surface. This is because the speed is faster and time difference occurs. Here, when palladium is uniformly deposited on the entire surface of the substrate, the plating speed is increased and the latency period is reduced.
도 3은 본 발명에 따른 팔라듐 활성화 용액 내의 염화 팔라듐 농도의 변화에 따라 구리 무전해 도금에서의 잠복기간을 나타내는 그래프이다.3 is a graph showing the incubation period in the copper electroless plating according to the change of the palladium chloride concentration in the palladium activation solution according to the present invention.
도 3을 참조하면, 염화팔라듐의 농도가 증가하면서 잠복기간이 점점 줄어들다가 염화 팔라듐의 농도가 0.1g/L일 때부터 잠복기간이 거의 일정해 지는 것을 볼수 있다. 그러므로, 염화 팔라듐의 농도가 0.1g/L일 때, 기판 전 표면에 팔라듐이 균일하게 증착되는 것을 알 수 있다.Referring to FIG. 3, the incubation period gradually decreases as the concentration of palladium chloride increases, and then the incubation period becomes substantially constant when the concentration of palladium chloride is 0.1 g / L. Therefore, when the concentration of palladium chloride is 0.1 g / L, it can be seen that palladium is uniformly deposited on the entire surface of the substrate.
도 4는 본 발명에 있어서의 염화 팔라듐 농도의 변화에 따른 구리 무전해 도금한 기판 표면의 비저항을 나타내는 그래프이다.4 is a graph showing the specific resistance of the surface of the copper electroless plated substrate according to the change in the palladium chloride concentration in the present invention.
도 4를 참조하면, 팔라듐 활성화 용액 내의 염화 팔라듐 농도의 변화시켜 기판 표면 처리를 실시한 후, 변화되는 각각의 구리 무전해 도금한 기판 표면의 비저항을 살펴볼 수 있다. 이때, 측정된 비저항 중에 염화 팔라듐의 농도가 0.1g/L 일 때 가장 낮은 비저항이 측정됨을 알 수 있다.Referring to FIG. 4, after the substrate surface treatment is performed by varying the palladium chloride concentration in the palladium activation solution, the resistivity of each of the copper electroless plated substrate surfaces to be changed may be examined. At this time, it can be seen that the lowest specific resistance is measured when the concentration of palladium chloride is 0.1g / L of the measured specific resistance.
도 5는 본 발명에 있어서의 염화 팔라듐 농도의 변화에 따른 구리 무전해 도금한 기판 표면의 RMS 거칠기를 나타내는 그래프이다.5 is a graph showing the RMS roughness of the surface of the copper electroless plated substrate with the change of the palladium chloride concentration in the present invention.
도 5를 참조하면, 팔라듐 활성화 용액 내의 염화 팔라듐 농도의 변화시켜 기판 표면 처리를 실시한 후, 각각 구리 무전해 도금한 기판 표면의 RMS 거칠기를 살펴볼 수 있다. 이때, 측정된 거칠기에서도 염화 팔라듐의 농도가 0.1g/L 일 때 가장 낮은 거칠기를 나타내는 것을 알 수 있다.Referring to FIG. 5, after the substrate surface treatment is performed by changing the palladium chloride concentration in the palladium activation solution, the RMS roughness of the copper electroless plated substrate surface may be examined. In this case, it can be seen that even the measured roughness exhibits the lowest roughness when the concentration of palladium chloride is 0.1 g / L.
이와 같이, 무전해 도금막의 비저항 또는 거칠기는 전처리 과정에서의 활성화 용액 내의 염화 팔라듐 농도, 즉 촉매의 농도에 따라서 달라질 수 있으며, 이러한 촉매의 최적 농도는 상술한 바와 같이 촉매의 금속이 기판 전(全)표면에 증착되는 최소 농도이면 바람직하다.As such, the specific resistance or roughness of the electroless plated film may vary depending on the concentration of palladium chloride in the activating solution during the pretreatment, that is, the concentration of the catalyst. The minimum concentration deposited on the surface is preferred.
상술한 바와 같이 본 발명에 의하면, 무전해 도금을 실시하는 반도체 배선 공정의 전처리 공정으로서 기판 표면 처리를 실시함으로써, 기판 표면에 균일한 촉매층을 형성하여 낮은 면저항을 갖는 것과 동시에 표면이 고른 무전해 도금막을 형성할 수 있어서 반도체의 질적 향상을 도모 할 수 있다.As described above, according to the present invention, by performing a substrate surface treatment as a pretreatment step of a semiconductor wiring process in which electroless plating is performed, a uniform catalyst layer is formed on the surface of the substrate to have a low sheet resistance and an even electroless plating. A film can be formed, and the quality of a semiconductor can be improved.
본 발명은 상기 실시예에만 한정되지 않으며, 본 발명의 기술적 사상 내에서 당 분야에서 통상의 지식을 가진 자에 의해 많은 변형이 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.
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| KR930024097A (en) * | 1992-05-15 | 1993-12-21 | 문정환 | Metal wiring method of semiconductor |
| KR19990057289A (en) * | 1997-12-29 | 1999-07-15 | 김영환 | Metal wiring layer formation method of MOS PET transistor |
| JP2000212754A (en) * | 1999-01-22 | 2000-08-02 | Sony Corp | Plating method, its device and plated structure |
| KR20030017694A (en) * | 2001-08-21 | 2003-03-04 | 삼성전자주식회사 | Method for forming metal interconnections using electroless plating |
| KR20030027445A (en) * | 2001-09-28 | 2003-04-07 | 학교법인 성균관대학 | Method for forming cu interconnection of semiconductor device using electroless plating |
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| KR930024097A (en) * | 1992-05-15 | 1993-12-21 | 문정환 | Metal wiring method of semiconductor |
| KR19990057289A (en) * | 1997-12-29 | 1999-07-15 | 김영환 | Metal wiring layer formation method of MOS PET transistor |
| JP2000212754A (en) * | 1999-01-22 | 2000-08-02 | Sony Corp | Plating method, its device and plated structure |
| KR20030017694A (en) * | 2001-08-21 | 2003-03-04 | 삼성전자주식회사 | Method for forming metal interconnections using electroless plating |
| KR20030027445A (en) * | 2001-09-28 | 2003-04-07 | 학교법인 성균관대학 | Method for forming cu interconnection of semiconductor device using electroless plating |
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