KR100443174B1 - Apparatus of iteration decoding limitation using saturation bit and Turbo Decoding System using the same - Google Patents

Abstract

The present invention relates to an iterative decoding limiter using a saturation bit value and a turbo decoding system using the same. In order to reduce the average number of iteration decoding by variably limiting the number of iteration decoding using the saturation bit value when an error is corrected, a map decoder First LLR processing means for counting the number of times the first decoding result LLRO is saturated to an arbitrary setting value to determine when the saturation bit number value no longer increases; Second LLR processing means for counting the number of times the second decoding result LLR1 of the map decoder is saturated to the predetermined setting value and determining when the saturation bit number value no longer increases; And repetitive decoding stop means for outputting a repetitive decoding stop signal for stopping repetitive decoding of the map decoder according to the determination result of the first and second LLR processing means.

Description

Apparatus of iteration decoding limitation using saturation bit and Turbo Decoding System using the same}

The present invention relates to an iterative decoding limiting apparatus using a saturation bit value and a turbo decoding system using the same. More specifically, the present invention relates to asynchronous communication based on next generation mobile communication networks such as International Mobile Telecommunication (IMT-2000) and Universal Mobile Telecommunications System (UMTS). Regarding the repeated decoding limiting device for reducing the average number of repeated decoding by variably limiting the number of repeated decoding using a saturation bit value in error correction in a mobile communication system (WCMS) and a turbo decoding system using the same will be.

As the mobile communication technology is developed, the turbo decoder which is advantageous in terms of power consumption due to miniaturization and light weight has been used for smooth portability of the mobile communication device.

At present, it is known that a turbo decoder can expect an improvement in decoding performance by repeatedly decoding during error correction. However, increasing the number of iterative decodings in a good channel environment does not improve the performance further. This is because, in the case of a good channel environment, since the decoding performance is generally excellent in the second or third time, it is no longer necessary to perform repeated decoding.

Nevertheless, the conventional turbo decoder has a problem of causing power waste by continuously performing repeated decoding as the maximum number of repeated decoding is set.

In addition, the 3.5th generation or 4th generation turbo decoder has to process the signal at high speed in order to provide a faster service to more subscribers, but there is a problem that the hardware complexity must be increased inevitably for such a high speed turbo decoder.

In addition, an unnecessary iterative decoding operation in a high speed operation has a problem of causing significant decoding delay.

Hereinafter, with reference to the accompanying drawings will be described in detail the problems of the prior art.

1 is a block diagram of a turbo decoding system according to the prior art.

Iterative code control method of turbo code plays an important role in performance improvement during iterative decoding Using the variance value for, and to obtain the respective variance value is shown in Equation 1 below.

Referring to a method of controlling repeated decoding of a turbo code, first, channel state information is estimated using received data. Using this value, the maximum number of repeated decodings is determined in advance, and the repeated decoding process is started.

Here, the first MAP (Decoder) and the second MAP decoder measure the variance of the external information values and define the difference of these values, that is, the increase of the external information values, as the delta variance. .

The maximum number of repeated decoding is made based on this variance, and the variance difference in the i-th iterative decoding is expressed by Equation 2 below.

According to the number of repeated decoding The value and each bit error rate As the value increases, the error rate decreases. That is, the decoding performance is improved.

However, when the dispersion difference value is exceeded, an error flow phenomenon occurs, and the threshold determination method is to stop the repeated decoding at the point where the maximum dispersion difference value appears. That is, according to the channel value Based on the maximum value of, the maximum number of repeated decoding is determined as the test table 110 in advance, and the repeated decoding is performed.

However, as shown in FIG. 1, the repetition frequency setting unit 107, the SNR estimator 108, the dispersion calculators 109 and 111, and the dispersion difference check table 110 are implemented in hardware. Use in a communication system can also present another problem. In other words, the size of the circuit composed of the variance arithmetic units 109 and 111, the corresponding SNR estimator 108, the variance difference check table 110, and the like increases considerably.

The conventional turbo decoder structure is decoded based on the surplus information obtained from the decoder # 1 102 and the decoder # 2 104. Decoding unit # 2 104 outputs new surplus information. The decoders # 1 102 and # 2 104 improve the respective decoding results by updating the surplus information. If there is no update of the surplus information between the decoder # 1 102 and the decoder # 2 104, each decoding result will not be different. In particular, there will be no change if the value of the LLR is saturated with a positive or negative value (see Type 1 below). Repeat decoding is stopped because no more repeated decoding becomes useless.

Therefore, in the present technical field, there is an urgent need for a method of reducing the average number of repeated decoding by variably limiting the number of repeated decoding using a saturation bit value in order to reduce the hardware circuit area of the turbo decoder.

The present invention has been proposed to meet the above requirements, and iterative decoding limiting apparatus for reducing the average number of repeated decoding by limiting the number of repeated decoding by using the saturation bit value in error correction and turbo using the same The purpose is to provide a decoding system.

1 is a block diagram of a turbo decoding system according to the prior art.

2 is a block diagram of an embodiment of a turbo decoding system for performing an iterative decoding limit function according to the present invention;

3 is a block diagram of an embodiment of an iterative decoding limiting apparatus according to the present invention;

* Explanation of symbols for the main parts of the drawings

301,302 Subtractor 303304 Comparator

305,306: Saturation bit counter 307: Second decoding LLR0 storage

308: second decoding LLR1 storage 309: first decoding LLR0 storage

310: first decoding LLR1 storage 311,312: comparator

313: AND gate

According to the present invention for achieving the above object, in the apparatus for limiting the number of repeated decoding of the turbo decoder, the number of saturated bit number value is further increased by counting the number of times the first decoding result (LLRO) value of the map decoder is saturated to an arbitrary setting value. First LLR processing means for determining a time point not abnormally increasing; Second LLR processing means for counting the number of times the second decoding result LLR1 of the map decoder is saturated to the predetermined setting value and determining when the saturation bit number value no longer increases; And repetitive decoding stop means for outputting a repetitive decoding stop signal for stopping repetitive decoding of the map decoder according to the determination result of the first and second LLR processing means.

In addition, the present invention provides a turbo decoding system comprising: input means for receiving a decoding symbol value; Decoding means for decoding the feedback decoding result (surplus information) and the input decoding symbol value; Address generating means for generating an interleaver or de-interleaver address; Storage means for storing a decoding result (LLR) of the decoding means for each interleaver or de-interleaver address generated by the address generating means; And repetitive decoding limiting means for stopping the repetitive decoding of the decoding means at a time when the decoding result (LLR) value of the decoding means is saturated to a maximum value and the saturation bit number value is no longer increased. It is characterized by.

The present invention uses the characteristic that the fixed bit number is saturated as the LLR (Log Likelihood Ratio) value is decoded in order to reduce the number of repeated decoding of the turbo decoder used for error correction. When there is no change by counting, the number of repeated decoding is reduced by stopping decoding.

To this end, the present invention can be easily implemented using the characteristic that the fixed number of bits of the LLR (Log Likelihood Ratio) value obtained in the two MAP operations of the turbo decoder is saturated, without obtaining the dispersion of the surplus information. Therefore, the number of repeated decoding can be effectively limited.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The implementation formula of the maximum decoder map turbo decoder obtained by taking a log with respect to the Pure-MAP equation is shown in Equation 3 below.

Here the subscript means:

k: sequence of received symbols

m: number of states (0-7)

i: Input symbol (0 or 1)

j: Input symbol (0 or 1) in the forward state (or reverse state) that is distinct from i

b: Backward

f: Forward

In Equation 3, the first equation is an equation for calculating a Log Likelihood Ratio (LLR) for step k. In this case, the E function is calculated by adding the forward state metric value, the metric value, and the reverse state metric value, so that the difference between the LLR value LLR1 when the input value is 1 and the LLR calculation LLR0 when the input value is 0 is calculated. Obtain Here, the hard decision is made to decode the result to 1 or 0 depending on whether the difference is positive or negative.

Here, the definition of the E function is as shown in Equation 4 below.

Where c = A / Lc, where A is the mean of the input distribution function and Lcp is the noise variance factor to be. The c value is a value that varies depending on the channel environment. The c value is divided into four types and a lookup table (LUT) is prepared and used.

In Equation 3, the second equation calculates a forward state metric value for step k. The calculation of the forward state metric value in each step (k) is obtained by taking the E function by adding the value obtained in the previous step (k-1) and the branch metric value in the current step. Here, the forward state metric value is always positive.

In Equation 3, the third equation calculates a reverse state metric value for step k. The calculation of the reverse state metric value in each step (k) is obtained by taking the E function by adding the value obtained in the next step (k + 1) and the branch metric value in the current step. Here, the reverse state metric value is always positive.

In Equation 3, the fourth equation calculates branch metric values for step k. here, Is a normalization constant, Is the sysmatic bit received as the input of the decoder. And the surplus information obtained from the decoding result ( ) Also, Is the received parity bit input and the turbo encoder output value Is multiplied by. Here, the branch metric value is always positive because of the normalization constant.

The forward state metric or reverse state metric calculations are incremented as the values accumulate as you move through each step.

In general, normalizing on a given number of bits saturates to the maximum number of bits. For example, in the case of 8 bits, if the calculation result exceeds 255, it is kept at the saturated 255 value.

In the first equation of Equation 3, the values need only be added until LLR1 and LLR0 are obtained. When two values are added together, all values above 255 will remain saturated at 255.

Branch metric values are always normalized positively by normalization constants.

The forward or reverse state metric value is also positive.

The turbo decoder feeds back the decoding result, i.e., the surplus information, and repeatedly decodes the same as the input buffer value. Here, the improved decoding result is output whenever the decoding is repeated by updating the surplus information. As a result of the improved decoding result, the LLR value is more reliable than the first decoding result.

If BPSK (Binary Phase Shift Keying) modulation is performed when the encoder input is 0 or 1, the decoder will update the LLR0 value to a larger value to process the decoding result for 0 normally. In order to process the decoding result for 1, the LLR1 value will be updated to a larger value. At this time, when the maximum value is fixed to 8 bits, the LLR0 value and the LLR1 value are saturated to 255.

In this case, as the number of times of repeated decoding of the turbo decoder increases, the characteristics appearing in the LLR value may be classified into the following three types.

Type 1: if the value of the LLR is saturated with a + or-value

Type 2: When the value of LLR alternates between + and -values around 0

Type 3: the value of the LLR hardly changes to a positive or negative value

Here, Type 1 is a typical type that is well decoded, and keeps its value once it reaches a saturated value.

On the other hand, although Type 2 is decoded, it sometimes affects different hard decisions.

On the other hand, type 3 is a case where decoding is not performed at all.

If the channel condition is good among the three types described above, Type 1 is most likely, and Type 2 and Type 3 occur in a very small number of cases.

Therefore, the present invention counts the number of saturated values of LLR0 and LLR1 to the maximum value using type 1, and stops the repeated decoding at the point when the saturation bit count value no longer increases.

2 is a block diagram of an embodiment of a turbo decoding system for performing an iterative decoding limit function according to the present invention. Here, the map decoder (Max Log-MAP) 204 uses the decoder # 1 102 and the decoder # 2 104 of FIG. 1 according to the selection of the input buffers 201 to 203 by the multiplexer. To serve.

As shown in FIG. 2, the turbo decoding system for performing an iterative decoding limit function according to the present invention includes an input buffer 201 to 203 for receiving a decoding symbol value, and a feedback result of a decoded result (surplus information). A map decoder 204 for decoding the decoding symbol value, an interleaver address generator 206 and a de-interleaver address generator 207 for generating an interleaver or de-interleaver address, and an interleaver address generator 206 And the LLR buffer 205 for storing the decoding result (LLR) of the map decoder 204 for each interleaver or de-interleaver address generated by the de-interleaver address generator 207, and the map decoder 204. The repeated decoding stop determination unit 208 for stopping the repeated decoding of the map decoder 204 when the number of decoded result (LLR) is saturated to the maximum value and the saturation bit number value no longer increases. It includes.

Here, the output of the map decoder 204 is stored in the LLR buffer 205 by subtracting the intrinsic information from the LLR value, and the interleaver address generator 206 or the de-interleaver address generator 207 is used. It is saved and output to the address created by. At this time, the value of the output LLR buffer 205 is fed back and again It is added with the value of the input buffer 201.

In addition, the iterative decoding stop determination unit 208 is for reducing the number of iterative decoding of the turbo decoding system, and using the characteristic that the fixed number of bits is saturated as the LLR value is decoded, the map decoding unit 204, that is, The number of saturated bits of the decoder # 1 102 and the decoder # 2 104 of FIG. 1 is counted to stop decoding when there is no change. Thus, the computation amount and delay can be efficiently reduced by reducing the average number of iteration decoding.

That is, the iterative decoding stop determination unit 208 transmits to the hard decision unit 209 when the LLR value of the decoder # 1 102 and the LLR value of the decoder # 2 104 of the map decoder 204 are not changed. By applying a signal, the hard decision unit 209 stores the hard decision result in the output buffer 210.

FIG. 3 is a block diagram of an iterative decoding limiter according to an embodiment of the present invention, and shows the iterative decoding stop determination unit 208 of FIG.

As shown in FIG. 3, the iterative decoding limiting apparatus according to the present invention counts the number of times that the first decoding result LLRO of the map decoding unit 204 is saturated to the maximum value so that the saturation bit count value is no longer present. The LLR0 processing unit for determining the time point that does not increase and the number of times the second decoding result LLR1 value of the map decoder 204 saturates to the maximum value are counted to determine the time point when the saturation bit count value no longer increases. And an AND gate 313 for outputting the iterative decoding stop signal 314 of the map decoding unit 204 in accordance with the determination result of the LLR0 processing unit and the LLR0 and LLR1 processing units.

Here, the LLR0 processing unit compares the LLR0 value with a predetermined value (arbitrary reference value), and counts the LLR0 saturation bit according to the comparison result of the comparator 303 and the comparator 303 for checking whether or not the saturation bit is saturated. 305, a second decoded LLR0 storage 307 for storing the counted LLR0 saturation bits, and a first decoded for storing the shifted LLR0 saturation bits, at the second decoded LLR0 storage 307; LLR0 saturation is compared with the LLR0 storage 309 and the number of LLR0 saturation bits stored in the second decoded LLR0 storage 307 and the number of LLR0 saturation bits stored in the first decoded LLR0 storage 309. And a comparator 311 for determining when the bit number value no longer increases.

Then, the LLR1 processing unit compares the LLR1 value with a predetermined value (arbitrary reference value), and counts the LLR1 saturation bit according to the comparison result of the comparator 304 and the comparator 304 for checking whether or not the saturation bit is saturated. 306, a second decoded LLR1 storage 308 for storing the counted LLR1 saturation bits, and a first decoded for storing the shifted LLR1 saturation bits, in the second decoded LLR1 storage 308. LLR1 saturation is compared with the LLR1 saturation bits stored in the second decoded LLR1 storage 308 and the LLR1 saturation bits stored in the first decoded LLR1 storage 310. And a comparator 312 for determining when the bit number value no longer increases. Here, the saturation bit number value stored in the first decoding LLR0 storage 309 and the first decoding LLR1 storage 310 is included. LLR0 saturation bits stored in the first decoded LLR0 store 309 for the For example, the turbo decoding system performs iterative decoding in order to improve decoding performance. After performing the first decoding process, the turbo decoding system converts the counted number of LLR0 saturation bit numbers into a second decoding LLR0 storage device. Thereafter, after performing two decoding processes, the turbo decoding system transfers the number of LLR0 saturation bit values previously stored in the second decoding LLR0 storage 307 to the first decoding LLR0 storage 309. After shifting and storing, the counted new LLR0 saturation bit number value is stored in the second decoded LLR0 storage unit 307. That is, the LLR0 saturation bit number value previously stored in the second decoding LLR0 storage unit 307 is deleted and the new LLR0 saturation bit number value is stored. After that, the comparator 311 performs the decoding once and counts the LLR0 saturation counted. Compares the number of bits (value stored in the first decoding LLR0 storage unit 309) with the number of LLR0 saturation bits counting (counting value stored in the second decoding LLR0 storage unit 307) counted after two times of decoding. It is determined when the LLR0 saturation bit count value is no longer increased.

The iterative decoding stop determination unit 208 receives the values of LLR1 and LLR0 every k steps. At this time, the input value is subtracted by the subtractors 301 and 302 and then compared with an arbitrary reference value by the comparators 303 and 304. That is, the subtractor 301 calculates the difference between the LLR0 value and the maximum value, and the subtractor 302 calculates the difference between the LLR1 value and the maximum value. In addition, the comparator 303 checks whether LLR0 is a saturation bit compared to an arbitrary reference value in the corresponding k step, and the comparator 304 checks whether LLR1 is a saturation bit compared to an arbitrary reference value in the corresponding k step.

At this time, the subtractors 301 and 302 transfer the result of subtracting the input value (hexadecimal or decimal) from the arbitrary setting value (for example, 255) to the comparators 303 and 304. Then, the comparators 303 and 304 compare the result values received from the subtractors 301 and 302 with an arbitrary reference value (for example, 0). Thereafter, the iterative decoding stop determination unit 208 performs the comparators 303 and 304. If the value is 0, the saturation bit counters 305 and 306 are incremented by one. Here, the condition of increasing the value of the saturation bit counters 305 and 306 by 1 may increase the value of the saturation bit counters 305 and 306 when the comparison result is zero or less than or greater than zero.

When the procedure is over for k, the saturation bit count is temporarily stored in the second decoded LLR0 store 307 and the second decoded LLR1 store 308.

Thereafter, the information of the second decoding LLR0 storage 307 is temporarily stored in the first decoding LLR0 storage 309, and the information of the second decoding LLR1 storage 308 is stored in the first decoding LLR1 storage 310. Save temporarily. At this time, a new number of saturation bits is stored in the second decoding LLR0 storage 307 and the first decoding LLR1 storage 308.

Next, the comparator 311 compares the LLR0 saturation bit coefficient value stored in the second decoding LLR0 storage 307 with the LLR0 saturation bit coefficient value stored in the first decoding LLR0 storage 309, and then compares the same. Outputs a flag signal.

Similarly, the comparator 312 compares the LLR1 saturation bit coefficient value stored in the second decoding LLR1 storage 308 with the LLR1 saturation bit coefficient value stored in the first decoding LLR1 storage 310, Outputs a flag signal.

Here, this process is simultaneously performed for LLR0 and LLR1.

Finally, an iterative decoding stop signal 314 is generated at the AND gate 313 by the flag signals for LLR0 and LLR1, and the repeated decoding stop signal 314 thus generated is a hard decision unit. 209, the hard decision unit 209 stores the result in the output buffer 210 and finishes decoding.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

As described above, the present invention utilizes a characteristic in which a fixed number of bits is saturated as decoding of a Log Likelihood Ratio (LLR) value proceeds in order to reduce the number of repeated decoding of the turbo decoder, thereby observing and changing the number of saturated bits in the decoder. When not present, the decoding is stopped to reduce the delay time of the decoding process, to prevent waste of power, and to reduce the complexity of the system.

Claims (6)

In the apparatus for limiting the number of iterative decoding of the turbo decoder, First LLR processing means for counting the number of times the first decoding result (LLRO) value of the map decoder is saturated to an arbitrary setting value and determining when the saturation bit number value no longer increases; Second LLR processing means for counting the number of times the second decoding result LLR1 of the map decoder is saturated to the predetermined setting value and determining when the saturation bit number value no longer increases; And Repetitive decoding stop means for outputting a repetitive decoding stop signal for stopping repetitive decoding of said map decoder according to the determination result of said first and second LLR processing means; An iterative decoding limiter using an iterative decoding saturation bit value comprising a. The method of claim 1, The decoding result (LLR) value is, An iterative decoding limiter using an iterative decoding saturation bit value, characterized in that it is saturated with respect to a fixed number of bits as it is repeatedly decoded. The method according to claim 1 or 2, The first and second LLR processing means, An iterative decoding limiter using an iterative decoding saturation bit value, characterized in that it is determined when a change in the number of saturation bits is zero by counting the number of saturation values of the decoding result (LLR) to the random set value. The method according to claim 1 or 2, The first and second LLR processing means, respectively Subtraction means for subtracting the LLR value from the arbitrary set value and delivering it to a first comparison means; The first comparison means for checking whether the result value subtracted by the subtraction means is a saturation bit by comparing with a reference value; A saturation bit counting means for counting LLR saturation bits according to a comparison result of the first comparison means; First storage means for storing the number of first LLR saturation bits counted by said saturation bit counting means; Second storage means for storing the number of second LLR saturation bits shifted in the first storage means; And Second comparing means for comparing the first and second LLR saturation bit numbers and determining a time point at which the LLR saturation bit number value is no longer increased. An iterative decoding limiter using an iterative decoding saturation bit value comprising a. In the turbo decoding system, Input means for receiving a decoding symbol value; Decoding means for decoding the feedback decoding result (surplus information) and the input decoding symbol value; Address generating means for generating an interleaver or de-interleaver address; Storage means for storing a decoding result (LLR) of the decoding means for each interleaver or de-interleaver address generated by the address generating means; And Repetitive decoding limiting means for stopping repetitive decoding of the decoding means at a time when the decoding result (LLR) value of the decoding means is saturated to a maximum value and the saturation bit number value no longer increases. Turbo decoding system comprising a. The method of claim 5, wherein The repeat decoding limit means, First LLR processing means for counting the number of times the first decoding result LLRO of said decoding means is saturated to a predetermined set value (maximum value) to determine when the saturation bit number value no longer increases; Second LLR processing means for counting the number of times the second decoding result LLR1 of said decoding means is saturated to said random set value (maximum value) to determine when the saturation bit number value no longer increases; And Repeat decoding stop means for outputting a repeat decoding stop signal of said decoding means in accordance with the determination result of said first and second LLR processing means; Turbo decoding system comprising a.