KR100440074B1 - Apparatus for generating key in algorithm of data encryption standard - Google Patents

Abstract

The present invention relates to a key generation device of a data encryption standard algorithm that optimizes a hardware implementation of a key generation unit by using a common point between encryption and decryption algorithms of the DES (Data Encryption Standard). When decoding, it is possible to optimize the area of hardware by implementing the shift in each direction jointly rather than in each direction.

Description

Apparatus for generating key in algorithm of data encryption standard}

The present invention relates to a device for generating a key of a data encryption standard algorithm. The present invention relates to data optimized for hardware implementation of a key generation unit by using a common point between encryption and decryption algorithms of the DES (Data Encryption Standard). A key generating device of an encryption standard algorithm.

1 shows a general encryption algorithm of DES, which is divided into a data encryption portion 10 on the left side and a key generation unit 20 on the right side.

The data encryption part 10 divides the input 64-bit general data into left and right 32 bits, wherein the 48-bit key (Ki, i = 1, ..., 16) generated by the key generator 20 and the f function and Repeat the operation 16 times using XOR (Exclusive-OR), and then encrypt by changing the left and right 32 bit values again.

The key generation unit 20 in this encryption algorithm will be described in detail below.

The user enters a 56-bit key, which includes an 8-bit parity bit and the initial key is 64-bit.

That is, the parity bit corresponds to every eighth bit of 64 bits, so that the parity bit is adjusted so that each byte has an odd number of '1's.

The 64-bit initial key is first operated on a Permuted Choice 1.

At this time, the parity bit is excluded and only 56 bits participate in the operation of the combination selection 1.

Table 1 below shows a bit array of the initial key according to the operation of the combination selection 1.

TABLE 1

57 49 41 33 25 17 9 One 58 50 42 34 26 18 10 2 59 51 43 35 27 19 11 3 60 52 44 36 63 55 47 39 31 23 15 7 62 54 46 38 30 22 14 6 61 53 45 37 29 21 13 5 28 20 12 4

That is, the first bit of the combination selection 1 result corresponds to the 57th bit of the initial key, and the second bit of the result value corresponds to the 49th bit of the initial key.

In this way, the array of bits is changed except for the parity bits of the initial key.

After that, the result of the combination selection 1 is separated again by 28 bits, and the first 28 bits are defined as C0, and the next 28 bits are defined as D0.

Then, using these separated C0 and D0, 16 keys for encryption will be generated.

First, C0 and D0 are shifted in sequence, i = 1,... , 16, it is shifted by following Table 2 according to C (i-1) and D (i-1).

TABLE 2

i One 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Shift size One One 2 2 2 2 2 2 One 2 2 2 2 2 2 One

That is, C0 and D0 are shifted by one bit to be C1 and D1, C1 and D1 are shifted by one bit to C2 and D2, and C2 and D2 are shifted by two bits to C3 and C4.

In this way, both Ci (i = 1,…, 16) and Di (i = 1,…, 16) can be obtained.

Then, in order to obtain a key (Ki) value for encryption, the operation of Permuted Choice 2 is performed on Ci (i = 1,…, 16) and Di (i = 1,…, 16). .

Table 3 shows the arrangement of bits according to the operation of the combination selection 2.

TABLE 3

14 17 11 24 One 5 3 28 15 6 21 10 23 19 12 4 26 8 16 7 27 20 13 2 41 52 31 37 47 55 30 40 51 45 33 48 44 49 39 56 34 53 46 42 50 36 29 32

The operation of the combination selection 2 is performed in the same manner as the combination selection 1, and the Ki of 48 bits is generated by changing the bit array of Ci and Di as shown in Table 3.

The keys, Ki (i = 1, ..., 16), thus generated, are applied to the data encryption portion 10 of the DES algorithm.

The above is a description of the encryption, on the contrary, when decrypting, the above process is repeated from C16 and D16 instead of C0 and D0. However, the shift is to the right at this time.

Figure 2 shows a comparison of the shift amount during encryption and decryption as described above. As shown, it can be seen that the amount of shift from C1 to C16 during encryption and the amount of shift from C16 to C1 at decryption are the same.

When implementing such a DES algorithm in hardware, since encryption and decryption are generally implemented as separate blocks, common parts of encryption and decryption tend to overlap each other, which causes a problem in that the size of hardware is relatively large.

An object of the present invention is to optimize the hardware implementation of the key generation unit of the DES algorithm that can be applied to all encryption systems.

Another object of the present invention is to simultaneously implement encryption and decryption in the DES algorithm.

Another object of the present invention is to use the shift direction of the key generation unit of the DES algorithm as one direction for simultaneous encryption and decryption.

1 is a flow diagram of a general encryption algorithm of DES.

FIG. 2 is a diagram comparing shift amounts at the time of encryption and decryption in the algorithm of FIG. 1. FIG.

3 is a block diagram of a key generation device according to an embodiment of the present invention.

4 is a block diagram of a key generation device according to another embodiment of the present invention.

To this end, a feature of the present invention, the key control unit for generating the upper data and lower data by performing the operation according to the encryption and decryption with the initial key value; A first shift unit for left shifting upper data; A second shift unit for left shifting lower data; And a key generation unit for performing a combination selection 2 operation of the data encryption standard algorithm with the respective data shifted in the first shift unit and the second shift unit to generate a key for encryption and decryption of the data encryption standard algorithm;

Each of the first shift portion and the second shift portion includes a register; A first multiplexer for selectively transferring any one of upper data and lower data and feedback data to a register; A first inverse array for inversely arranging data in the register; A second multiplexer for transferring data of a register in case of encryption and data of a first inverse array in case of decryption; A rotator configured to left shift the data transmitted from the second multiplexer in units of bits; A second reverse arranger for reverse arranging data of the rotator; And a third multiplexer which transmits data of the rotator as feedback data to the first multiplexer in case of encryption and delivers data of the second inverse array to the first multiplexer as feedback data in case of decryption. An apparatus for generating a key of an encryption standard algorithm is provided.

In addition, another aspect of the present invention, the key control unit for generating the upper data and lower data by performing the operation according to the encryption and decryption with the initial key value; A first shift unit for shifting higher order data; A second shift unit for shifting the lower data; and a combination selection 2 operation of the data encryption standard algorithm with each data shifted in the first shift unit and the second shift unit to perform encryption and decryption keys of the data encryption standard algorithm. A key generating unit for generating;

Each of the first shift portion and the second shift portion includes a register; A multiplexer for selectively transferring any one of upper data and lower data and feedback data to a register; And a rotator for shifting the register data bit by bit in accordance with encryption and decryption and transmitting the feedback data to the multiplexer as feedback data.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a hardware configuration diagram of a key generation device according to an embodiment of the present invention for implementing a shift of encryption and decryption together in a DES encryption algorithm, including three pairs of multiplexers 310 to 320 and one pair of rotators 326. 328, a pair of registers 322 and 324, and two pairs of inverse arrays 330 to 336, which are divided into a portion for calculating Ci and a portion for calculating Di.

This is done by dividing the number of bits, so that the calculation can be done more efficiently, and the hardware configuration is also reduced to reduce the load.

In addition, the key generation device according to the embodiment of the present invention receives an initial key K value and outputs C1 and D1 in case of encryption and C16 and D16 in case of decryption, and calculates a key controller 340. And a key generation unit 338 for generating a key by using Ci and Di.

The key control unit 340 performs a combination selection 1 operation on the initial key K in the case of encryption, separates it into C0 and D0, shifts it left by 1 bit, and outputs it as C1 and D1. After the combination selection 1 operation of K), it is separated into C0 and D0 and output as C16 and D16, respectively. The operation according to the encryption and decryption is determined by the encryption decryption determination signal A.

At this time, in the case of decoding, outputting C0 and D0 as C16 and D16 is as shown in FIG. 2. When C0 and D0 are shifted to generate C16 and D16, C0 and D0 are 28 bits and the shifted amount is 28 bits. This is because C0 and D0 become the same values as C16 and D16, respectively.

Meanwhile, the key generation unit 338 generates a key by performing a combination selection 2 operation using the calculated Ci and Di.

First, when an initial key (K) value for generating a key to be used for encryption and decryption is input to the key control unit 340, the key control unit 340 calculates Ci and Di (C1 and D1 in case of encryption, and decryption day). In the case of C16 and D16).

Then, the multiplexers 310 and 312 record Ci and Di transmitted from the key control unit 340 into the registers 322 and 324, respectively, and the registers 322 and 324 multiply the recorded Ci and Di into the multiplexer ( 314 and 316 and the inverse arrays 330 and 332, and the inverse arrays 330 and 332 transfer the Ci and Di arrays transferred from the registers 322 and 324 to the multiplexers 314 and 316. .

That is, the multiplexers 314 and 316 receive Ci and Di from the registers 322 and 324 and the inverse arrays 330 and 332, respectively, and the registers 322 and 324 and the inverse arrays 330 and 332 transmitted at this time. Ci and Di have different arrangements.

Accordingly, the multiplexers 314 and 316 determine whether to generate a key for encryption or a key for decryption according to the input encryption decryption determination signal A, and thus generate a key for encryption. Ci and Di are taken from the registers 322 and 324, and Ci and Di are taken from the reverse arrays 330 and 332 and transferred to the rotators 326 and 328 when a key for decryption is generated.

Here, the rotators 326 and 328 are shifted only to the left side, and the Ci and Di received from the multiplexers 314 and 316 are shifted to the left using an internal counter or an external counter (not shown). Most Significant Bit (MSB), which is the leftmost bit of 326 and 328, is rotated and input into the Least Significant Bit (LSB), which is the rightmost bit.

At this time, the rotators 326 and 328 adjust the shift amount according to the shift amount signal B input.

The shifted Ci and Di are transferred to the multiplexers 318 and 320 and the reverse arrays 334 and 336, and the reverse arrays 334 and 336 change the arrangement of Ci and Di transferred from the rotators 326 and 328. Pass to multiplexer 318,320.

That is, the multiplexers 318 and 320 receive Ci and Di from the rotators 326 and 328 and the reverse arrays 334 and 336, respectively, and the Ci of the rotators 326 and 328 and the reverse arrays 330 and 332 are transmitted. And Di differ in their arrangement.

Accordingly, the multiplexers 318 and 320 determine whether to generate a key for encryption or a key for decryption according to the input encryption decryption determination signal A, and generate a key for encryption. Ci and Di are taken from the rotators 326 and 328, and Ci and Di are taken from the reverse arrays 334 and 336 when the keys for decryption are generated and transmitted to the multiplexers 310 and 312.

Then, the multiplexers 310 and 312 record the Ci and Di values received in the registers 322 and 324, and repeat the above procedure to obtain C1, D1 to C16 and D16 in case of encryption and decryption in case of decryption. Obtain from C16, D16 to C1, D1.

During this process, the key generation unit 338 calculates Ki by performing a combination selection 2 operation using the values of Ci and Di recorded in the registers 322 and 324.

In summary, the multiplexers 314 to 320 take Ci and Di values from registers 322 and 324 or rotators 326 and 328 in the case of encryption according to the encryption decryption determination signal A. In the case of decryption, the data is classified according to encryption and decryption by obtaining Ci and Di values de-arranged in the reverse arrays 330 to 336, so that the rotators 326 and 328 only shift the amount regardless of encryption or decryption. The amount shifted from C1 and D1 to C16 and D16 and the amount shifted from C16 and D16 to C1 and D1 are the same as shown in FIG. 2, so that the rotators 326 and 328 are common regardless of encryption and decryption. Only the shift amount signal B used as is input.

Then, in order to use the left shift rotators 326 and 328 of encryption for decryption, the reverse arrayers 330 to 336 are used to input data in reverse order to shift left and output the data in reverse order. Make a shift effect.

In addition, the above-mentioned encryption decryption determination signal A and the shift amount signal B, which are necessary to apply the same hardware to encryption and decryption, are part of a signal generated to control the key generation device in the entire hardware implementation of the DES algorithm. Is implemented.

4 is a hardware configuration diagram of a key generation device according to another embodiment of the present invention, which includes a pair of multiplexers 410 and 420, a pair of registers 430 and 440, and a pair of rotators 450 and 460. As in the above-described embodiment of the present invention, it is divided into a part for calculating Ci and a part for calculating Di in order to reduce the load of efficient calculation and hardware configuration.

The key control unit 480 outputs C1 and D1 in case of encryption and C16 and D16 in case of encryption, and generates a key using the calculated Ci and Di. A key generation unit 470 is further provided.

The key control unit 480 performs a combination selection 1 operation on the initial key K in the case of encryption, separates it into C0 and D0, shifts it left by 1 bit, and outputs it as C1 and D1. After the combination selection 1 operation of K), it is separated into C0 and D0 and output as C16 and D16, respectively. The operation according to the encryption and decryption is determined by the encryption decryption determination signal A.

At this time, in the case of decoding, outputting C0 and D0 as C16 and D16 is as shown in FIG. 2. When C0 and D0 are shifted to generate C16 and D16, C0 and D0 are 28 bits and the shifted amount is 28 bits. This is because C0 and D0 become the same values as C16 and D16, respectively.

Meanwhile, the key generation unit 470 generates a key by performing a combination selection 2 operation using the calculated Ci and Di.

First, if an initial key (K) value for generating a key to be used for encryption and decryption is input to the key control unit 480, the key control unit 480 performs Ci and Di (C1 and D1 in case of encryption, and decryption date) through an operation. In the case of C16 and D16).

Then, the multiplexers 410 and 420 record the received Ci and Di in the registers 430 and 440, respectively, and the rotators 450 and 460 bring the Ci and Di recorded in the registers 430 and 440, respectively. .

The rotators 450 and 460 shift Ci and Di to the left in the case of encryption and to the right in the case of decryption. In this case, the MSB and LSB are rotated and input to the LSB and the MSB, respectively.

That is, the rotators 450 and 460 here can be bidirectionally shifted on both the left and right sides, and their directions are determined and used according to the case of encryption and decryption.

The determination of the encryption and decryption of the rotators 450 and 460 and the shift amount thereof are part of a signal generated to control the key generation device when the entire hardware implementation of the DES algorithm is implemented, and the encryption decryption determination signal A and the shift amount signal. Implement and use (B)

In other words, the rotators 450 and 460 determine the direction of the shift according to the encryption decryption determination signal A, and determine the number of bits to be shifted according to the shift amount signal B and received from the registers 430 and 440. Ci and Di are shifted in the corresponding direction using an internal counter or an external counter (not shown).

The shifted value is inputted to the multiplexers 410 and 420 again and the above process is repeated to obtain C1, D1 to C16 and D16 for encryption, and C16 and D16 to C1 and D1 for decryption. Obtain

During this process, the key generation unit 470 calculates Ki by performing a combination selection 2 operation using Ci and Di recorded in the registers 430 and 440.

As described above, the present invention extracts the common point that is shifted in the encryption / decryption algorithm of DES, and optimizes the area of hardware by jointly using one-way or two-way shifts without implementing shifts in each direction according to directions. It is effective.

Claims (8)

A key controller configured to generate upper data and lower data by performing an operation according to encryption and decryption with an initial key value; A first shift unit which shifts the upper data to the left; A second shift unit which shifts the lower data to the left; And A key for generating a key for encryption and decryption of the data encryption standard algorithm by performing a Permuted Choice 2 operation of the data encryption standard algorithm on each of the data shifted in the first shift unit and the second shift unit. A generating unit; Each of the first shift portion and the second shift portion, register; A first multiplexer for selectively transferring any one of the upper data and the lower data and feedback data to the register; A first inverse array for inversely arranging data in the register; A second multiplexer transferring data of the register in case of encryption and data of the first inverse array in case of decryption; A rotator for left-shifting data transmitted from the second multiplexer in units of bits; A second inverse array for inversely arranging data of the rotator; And In the case of encryption, the data of the rotator is transmitted to the first multiplexer as the feedback data, and in the case of decryption, a third multiplexer is provided to transmit the data of the second inverse array to the first multiplexer as the feedback data. Key generation device of the data encryption standard algorithm, characterized in that. The method of claim 1, In the case of encryption, the key control unit performs a permuted choice 1 operation of the data encryption standard algorithm with the initial key value, divides the upper initial data and the lower initial data, and shifts each bit by one bit to the upper key. Generating data and the lower data, and in case of decryption, generating the upper initial data and the lower initial data as the upper data and the lower data. The method of claim 1, The key controller, the second multiplexer, and the third multiplexer determine the encryption and decryption based on a control signal for determining encryption and decryption of the data encryption standard algorithm. Device. The method of claim 1, The rotator uses any one of an internal counter and an external counter, and determines and processes the shift amount by a control signal for determining the shift amount of the data encryption standard algorithm. . A key controller configured to generate upper data and lower data by performing an operation according to encryption and decryption with an initial key value; A first shift unit which shifts the upper data; A second shift unit which shifts the lower data; And A key generation unit configured to generate a key for encryption and decryption of the data encryption standard algorithm by performing a combination selection 2 operation of a data encryption standard algorithm on each of the data shifted in the first shift unit and the second shift unit; Each of the first shift portion and the second shift portion, register; A multiplexer for selectively transferring any one of the upper data and the lower data and feedback data to the register; And And a rotator for shifting the register data bit by bit in accordance with encryption and decryption, and transmitting the data as the feedback data to the multiplexer. The method of claim 5, wherein In the case of encryption, the key control unit performs a combination selection 1 operation of the data encryption standard algorithm with the initial key value, divides the upper initial data and the lower initial data into left bits, and shifts the upper data and the lower data by one bit. And generating the upper initial data and the lower initial data as the upper data and the lower data in case of decryption. The method of claim 5, wherein The rotator uses either one of an internal counter and an external counter, determines the amount of the shift by a control signal that determines the amount of shift of the data encryption standard algorithm, performs a left shift in case of encryption, and in case of decryption. The key generation device of the data encryption standard algorithm, characterized in that the right shift. The method of claim 5, wherein And the key control unit and the rotator determine the encryption and decryption based on a control signal for determining encryption and decryption of the data encryption standard algorithm.