KR100434062B1 - Method for give priority of bus right of use to pci device - Google Patents

Abstract

The present invention relates to a bus usage priority designation method of a PC-I device, and the prior art bus usage priority designation method of a PC-I device is set equally to the license priority of all devices using a PC-I bus, or the most frequently used one. By giving priority to the license of the device and setting the license of the other devices to be equivalent, there is a problem that the quality of service felt by the user is deteriorated because the task of important data continuity is not smoothly performed. In view of the above problems, the present invention provides a priority setting step of setting the priority of the PCI bus usage of the CPU and the CPU connected to the PCI bus in consideration of the importance and frequency of continuous processing of data; According to the set priority, the PCI bus is allowed to be used by the device having the highest priority, the waiting number of the device which is allowed to be used is initialized, and the waiting number of devices that do not use the remaining bus is increased, Each device is configured with a bus usage step of repeating the process of permitting the PCI bus to use the same device with the maximum number of waits specified in the following cycle, so that the continuous processing of data among the devices connected to the PCI bus is important. By being able to variably set the bus usage priority, there is an effect of improving the quality of service that a user feels.

Description

How to Specify Priority for Bus Usage of PCI Device {METHOD FOR GIVE PRIORITY OF BUS RIGHT OF USE TO PCI DEVICE}

The present invention relates to a bus priority setting method of a PC device. In particular, the user can change the priority of each PC device connected to the PC bus so that the user can change the priority of the PC device. It is about how to specify bus priority.

The PC devices connected to the PC bus are connected with a network card, a sound card, and a central processing unit. When a plurality of PC devices operate according to a user's work, a license for the PC bus is applied. The data of the licensed device can be inputted and outputted through the PCI bus. In particular, priority is given to major devices such as the central processing unit (CPU) so that when a request is made from a plurality of PC devices, the priority device is determined to use the PC I bus first. In the related art, such rules for granting priority and use rights are programmed in a central program such as a fixed program, which does not allow a user to change them. When described in detail with reference to the drawings as follows.

1 is a configuration diagram of a general PC system, as shown in FIG. 1, a CPU and a plurality of PC devices D1 to D4 connected to a PCI bus; And an arbiter for granting the right to use the PCI buses of the CPU and the plurality of PC devices D1 to D4.

A user may use a network card that connects to the Internet or a network using a computer, if necessary, or may use a sound card for listening to music. In the case of using each card individually in this way, there is no problem of priority and bus usage rights, but two or more PCs such as listening to music on the Internet or listening to music on the Internet at the same time. In the case of using the I-device, problems of the license and priority of each PC-I and the CPU are generated.

Conventionally, a method of not giving priority to the right of use of the PCI bus or giving priority to only one device has been used, which will be described in more detail.

FIG. 2 is a schematic diagram of a rotation method that does not give priority to the right of use of the conventional PC-I bus. As shown in FIG. 2, priority is given to each of the CPU and the plurality of PC-I devices D1 to D4. It is a method of adding a license by judging whether there is a request for the request of the PCI BUS license of each device (CPU, D1 to D4) for a predetermined time.

That is, if there is a license request from all the devices (CPU, D1 ~ D4), the ARBITER grants the CPU to use the PCI bus for a certain period of time. A license is granted to the PC devices D1 in order to enable the PC devices D1 to use the PC BUS, and in this manner, the PC devices D2 to D4 are sequentially used. After the license is granted, the use of the bus of the last PC device D4 in the cycle is completed, and the license is again granted to the CPU.

Of course, if one PC device is not used in the rotation and there is no request for a license, the PC device is excluded from the rotation.

The rotation method assumes that the bus usage rights of all devices are equal, thereby circulating the usage rights of the central processing unit (CPU) where the bus is most frequently used, resulting in a problem that smooth processing is not performed.

3 is a schematic diagram of the PAIR rotation method, which is a method for compensating the problem of the rotation method. In this method, priority is given to a device which is most frequently used, such as a central processing unit (CPU). About (D1-D4), the said rotation method is applied.

For example, priority is given to the central processing unit (CPU), and when there is a request for a bus license from all PC devices (D1 to D4), the license is given to the central processing unit (CPU) once given priority. When the bus of the central processing unit (CPU) is finished, a license is granted to the PC eye D1.

Then, when the use of the bus of the PCI device D1 is completed, the bus right to use is given to the CPU which is given priority again.

Then, when the use of the second bus is completed within one period of the CPU, the next PSI device D2 is given a bus use right.

As described above, priority is given to the most frequently used devices and the bus usage periods of the CPUs are arranged between the bus usage periods of the PC devices D2, thereby providing the bus usage periods of the most frequent devices. Be able to accommodate your needs.

However, as the period of use of the bus for each of the PC devices D1 to D4 becomes substantially longer, the quality of the work that the user feels may be degraded.

For example, if the user is watching a movie while downloading a file through the Internet, the user can use the pair rotation method or the network card permission to download the file and the video for watching the movie when the rotation method is used. And the right of use of the sound card is the same, but from the point of view of the user, the quality of the work is greatly deteriorated when the movie breaks in the middle rather than the download speed is slowed down. If this happens at the same time, the license of the video and sound cards should be given a higher priority than the license of the network card. This is a matter related to the quality of service (QoS), and in the related art, each of the PC devices D1 to D4 gives an equal priority without this consideration, thereby causing a problem that the quality of service is degraded.

As described above, the conventional method of designating the bus usage priority of the PCI device sets the license priority of all devices using the PCI bus equally, or gives priority to the license to one device that is most frequently used. By setting the usage rights of the devices to be equivalent, there is a problem that the quality of service felt by the user is deteriorated because a task in which continuity of data transmission is important is not smoothly performed.

In view of the above problems, the present invention sets the priority of bus usage of each PC device according to the importance of the continuity of data transmission, and also changes the application of the priority as necessary, thereby improving the quality of service felt by the user. The purpose of the present invention is to provide a method of designating a priority for using a bus of a PC device, which can be improved.

1 is a block diagram of a general PC system.

Figure 2 is a schematic diagram of a rotation (ROTATION) method that does not give priority to the use right of the conventional PC-I bus.

Fig. 3 is a schematic diagram of a pair rotation method in which only one device is given priority to a conventional PC-I bus.

4 is a block diagram of an arbiter for implementing the present invention.

Figure 5 is an embodiment of setting bus usage priority of the present invention.

Fig. 6 is another embodiment of bus usage priority setting of the present invention.

** Description of symbols for the main parts of the drawing **

1: deserializer 2: priority setting unit

3: arbiter

The above object is set in the priority setting step of setting the priority of the PCI bus use of the central processing unit and the PCI bus connected to the PCI bus in consideration of the importance and frequency of continuous processing of data; According to the set priority, the PCI bus is allowed to be used by the device having the highest priority, the waiting number of the device which is allowed to be used is initialized, and the waiting number of devices that do not use the remaining bus is increased, The maximum number of waits specified for each device is achieved by configuring the same device as a bus usage permitting step of repeating the process of permitting the use of the PCI bus in the following cycle, which will be described in detail with reference to the accompanying drawings. Is as follows.

4 is a schematic diagram of an arbiter for realizing the present invention. As shown therein, a serializer for receiving and serializing serial data for priority setting from a central processing unit (CPU) (DE-SERIALIZER) is shown. 1); A priority setting unit (PRIORITY CONTROL LOGIC) 2 for receiving a data of the deserializer 1 and outputting a setting signal for setting priority; Receives a request signal REQn from each PC device D1 to D4 and adds a bus right to use each of the PC devices D1 to D4 according to the priority given by the setting of the priority setting unit 2. It consists of an arbiter part (ARBITRATION LOGIC, 3).

Hereinafter, the operation of the arbiter for the configuration of the present invention configured as described above.

First, the CPU determines which PC device is important for continuous data transmission and transmits it to the ARBITER through serial communication.

In this case, the importance of the continuous transmission of data is given priority to the PCI device performing a task that can be clearly felt by the user, and the device may be one or more devices.

The data supplied from the CPU includes a standby maximum value REQ_STACK_MAX of a bus use request for each device and an initial request wait value REQ_STACK_INIT.

The standby maximum value REQ_STACK_MAX of the use request is not processed by being pushed by the priority of the PCI device or the CPU having different priorities of the CPUs D1 to D4 and the CPU. The maximum number of cycles to wait for. If the maximum number of waiting cycles (REQ_STACK_MAX) of the request and the current request are pushed backwards and the accumulated wait times become equal, the device is given priority in the next cycle. In the next cycle, the PCI devices (D1 to D4) or the central processing unit using the bus are given a priority and the rank is lowered even if the bus request is used.

In addition, the initial use request waiting value REQ_STACK_INIT is a value for specifying a priority in the first operation, and the PCI device D1 to D4 or the central processing unit to give the bus use authority of the highest priority in the first operation period. The use request wait initial value (REQ_STACK_INIT) of the (CPU) has the same value as the use request wait maximum value (REQ_STACK_MAX) of the device.

In this way, if the maximum request wait request value (REQ_STACK_MAX) and initial request wait request value (REQ_STACK_INIT) are specified for each device, the use of the PCI bus from the first PC devices D1 to D4 and the CPU is performed. If there is a request, the arbiter unit 3 in the arbiter (ARBITER) has a request request maximum value (REQ_STACK_MAX) and use request wait initial value (REQ_STACK_INIT) of the PC devices D1 to D4 and the CPU. Priority is given to the same device, allowing the same device to use the PCI bus in the first period whose usage request wait maximum value (REQ_STACK_MAX) and usage request wait initial value (REQ_STACK_INIT) are the same.

At the same time, the standby value of the remaining devices that do not use the PCI bus are increased by one.

As a result, the initially set use request wait initial value REQ_STACK_INIT is increased by 1, and the use request value of the device using the PCI bus is initialized to 0 in the first period.

Next, in the cycle, the maximum value of the request-request wait value REQ_STACK_MAX is compared with the number of waits of each device, and priority is given to devices having the same value, and the number of waits is increased by one to the other devices.

Through this process, the priority of each device's bus usage can be determined at every cycle, and the priority of each device can be automatically determined through the user's control or the system monitor of the central processing unit. In particular, the priorities can be set to all devices in contrast to giving priority to only one device and giving equal priority to the rest of the devices as in the prior art, and by changing the setting contents according to the user's work contents, It can provide the best working environment for the user.

When a user downloads a file while watching a movie, the video and sound card can be given priority over the network card to download the file, thereby ensuring the continuity of the data. In this case, the network card gives priority to the use of the bus compared to the video and sound cards so that smooth work can be achieved.

The above process will be described in more detail with reference to two embodiments.

FIG. 5 is a diagram showing an embodiment of implementing the conventional pair rotation method in applying the present invention, in which priority is given to the central processing unit (CPU) and equal priority is assigned to the remaining PC devices D1 to D4. .

First, the deserializer 1 of the arbiter ARBITER, which has received serial data from the CPU, parallelizes the data, and the priority setting unit 2 receives the data to set the priority.

At this time, the priority is in the CPU, and the maximum value of the request for waiting (REQ_STACK_MAX) is less than that of other PC devices D1 to D4, and the initial value of the request for waiting (REQ_STACK_INIT) is the maximum value of the waiting for use ( REQ_STACK_MAX).

As can be seen in FIG. 5, the maximum value of the request for use request (REQ_STACK_MAX) and the use request wait initial value (REQ_STACK_INIT) of the CPU are set to 1, and in the case of the PCI device D1, use request wait. The maximum value (REQ_STACK_MAX) and initial request wait request value (REQ_STACK_INIT) are set to 7, 6, respectively, 9 and 6 for PC device D2, 11 and 6 for PC eye device D3, and Device D4 is set to 13 and 6.

In the first period PHASE1 in this state, the CPU request priority is the same as the request request maximum value REQ_STACK_MAX and the request request wait initial value REQ_STACK_INIT. (CPU), the data of the central processing unit (CPU) is transmitted over the bus.

After such a process, the request wait initial value (REQ_STACK_INIT) of the CPU is initialized to 0, and the use request wait initial value (REQ_STACK_INIT) of each PC device D1 to D4 is added to 1 to use. The request wait values REQ_STACK are set to seven, respectively.

Next, in the period PHASE2, since the use request wait value REQ_STACK of the CPU is 0 and the use request wait maximum value is 1, the priority is not in the CPU and the PCI device D1. Since the use request waiting value REQ_STACK is 7 and the use request waiting value is 7, the use right of the bus is owned by the PCI device D1.

When the PCI device D1 uses the PCI bus, the request waiting value (REQ_STACK) of the PCI device is initialized to 0, and the request request waiting value (REQ_STACK) of the CPU and other PCI devices is initialized to zero. Increases by 1.

Next, in the cycle PHASE3, the CPU uses the bus because the CPU request value is the same as the request request maximum value REQ_STACK_MAX and the request request value REQ_STACK. The wait for use request of the devices D1 to D4 is increased by one.

In the next period PHASE4, the request wait value of the CPU is 0 and the request request wait values REQ_STACK of the PC devices D1 to D4 are 1, 9, 9, and 9, respectively. The PC eye device D2 having the same use request wait maximum value REQ_STACK_MAX and use request waiting value REQ_STACK equal to 9 will use the bus.

This method is repeated, the priority is placed in the central processing unit (CPU), the remaining PC-eye devices (D1 ~ D4) can implement an even pair rotation method.

If priority is given to improving a service quality to a specific device, the priority may be set as shown in FIG. 6 below.

FIG. 6 is a table illustrating an operation flow of another embodiment to which the present invention is applied. As shown in FIG. 6, the maximum value of the request wait maximum value REQ_STACK_MAX is set to 2 in the central processing unit, and the PC I devices D1 to D4, respectively. Set to 2, 8, 11, 14.

Then, the use request wait initial value REQ_STACK_INIT of the CPU is set to 2, and the use request wait initial value REQ_STACK_INIT of each of the PC devices D1 to D4 is set to 1, 6, 6, and 6.

By the above-described setting, in the first period PHASE1, the central processing unit (CPU) using the PCI bus having the same use request wait maximum value (REQ_STACK_MAX) and use request wait initial value (REQ_STACK_INIT) as 2 is used.

In addition, the use request wait value REQ_STACK of the CPU is initialized to 0, and the use request wait value REQ_STACK of the remaining PC devices D1 to D4 is increased by 1, 2, 7, and 7 respectively. , 7

In a subsequent period PHASE2, the PCI device D1 having the same use request wait maximum value REQ_STACK_MAX and use request wait value REQ_STACK equal to 2 has priority to use the PCI bus. The use request wait value (REQ_STACK) of (D1) is initialized to 0, the use request wait value (REQ_STACK) of the CPU is increased to 1, and the use request wait of the remaining PCI devices D2 to D4 is waited. The value REQ_STACK is also increased by 1 and all have a value of 8.

In the next cycle PHASE3, the PC device D2 has priority to use the bus. In the next cycle PHASE4, the CPU is again in the next cycle PHASE5. The device D1 has priority, and the PC eye device D3 uses the bus in a subsequent period PHASE6.

As described above, the central processing unit (CPU) and the PC-eye device (D1) are given priority to use the bus, and the remaining PC-eye devices (D2 to D4) have equal rights to use.

In this way, a priority is given to a plurality of devices so that the user or the system itself can give priority to a device in which continuous processing of data is important, thereby improving the efficiency of the work felt by the user.

As described above, the present invention can variably set the bus use priority of a device connected to the PCI bus, in which continuous processing of data is important, thereby improving the quality of service felt by the user.

Claims (6)

A priority setting step of setting the priority of the PCI bus usage of the CPU and the CPU connected to the PCI bus in consideration of the importance and frequency of continuous processing of data; By using the PCI bus of the device having the highest priority according to the set priority, the waiting time of the device which is allowed to be used is initialized, and the waiting time of the devices which have not used the remaining PCI bus is increased, A bus usage priority designating method comprising a bus usage permitting step of repeating a process of allowing a PCI bus to be used in a next cycle for a device having the same number of times and the maximum number of waiting times specified for each device. delete The method of claim 1, wherein the priority setting step comprises setting data by applying data to the arbiter from a central processing unit that monitors user setting or system usage. The method of claim 1, wherein the priority setting step specifies the maximum number of waits of the device to which priority is given to be the lowest within a positive integer range, and sets the maximum number of waits to the same value as the maximum number of waits. Bus priority setting method of a PC device. The method of claim 1, wherein the priority setting step sets the same value of the maximum number of waits of a device having a plurality of priorities within the range of positive integers in order to set a plurality of prioritized devices. Setting the initial value of the waiting number of one of the devices to the same value as the maximum waiting number, and setting the initial value of the waiting number of the device having the remaining priority to be sequentially decreased by one from the maximum waiting number. How to specify bus priority for child devices. The method of claim 1, wherein the bus usage permitting step initializes the wait count value to 0 for a device that allows the use of the PCI bus, increases the wait count of devices that do not use the PCI bus by 1, and A method of designating a bus usage priority of a PC-I device, characterized by granting a usage right of the PC-I bus to a device having the same waiting number as the maximum value set in the cycle.