KR100431975B1 - 분기에의한중단이없는파이프라인방식의마이크로프로세서를위한다중명령디스패치시스템 - Google Patents

분기에의한중단이없는파이프라인방식의마이크로프로세서를위한다중명령디스패치시스템

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Publication number
KR100431975B1
KR100431975B1 KR1019960061584A KR19960061584A KR100431975B1 KR 100431975 B1 KR100431975 B1 KR 100431975B1 KR 1019960061584 A KR1019960061584 A KR 1019960061584A KR 19960061584 A KR19960061584 A KR 19960061584A KR 100431975 B1 KR100431975 B1 KR 100431975B1
Authority
KR
South Korea
Prior art keywords
instruction
instructions
branch
functional units
predicted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
KR1019960061584A
Other languages
English (en)
Korean (ko)
Other versions
KR970049478A (ko
Inventor
융 로버트
Original Assignee
선 마이크로시스템즈 인코퍼레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 선 마이크로시스템즈 인코퍼레이티드 filed Critical 선 마이크로시스템즈 인코퍼레이티드
Publication of KR970049478A publication Critical patent/KR970049478A/ko
Application granted granted Critical
Publication of KR100431975B1 publication Critical patent/KR100431975B1/ko
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3865—Recovery, e.g. branch miss-prediction, exception handling using deferred exception handling, e.g. exception flags
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G06F9/38585—Result writeback, i.e. updating the architectural state or memory with result invalidation, e.g. nullification

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
KR1019960061584A 1995-12-07 1996-12-04 분기에의한중단이없는파이프라인방식의마이크로프로세서를위한다중명령디스패치시스템 Expired - Lifetime KR100431975B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/569,725 US5809324A (en) 1995-12-07 1995-12-07 Multiple instruction dispatch system for pipelined microprocessor without branch breaks
US08/569,725 1995-12-07
US08/581,115 1995-12-29

Publications (2)

Publication Number Publication Date
KR970049478A KR970049478A (ko) 1997-07-29
KR100431975B1 true KR100431975B1 (ko) 2004-10-28

Family

ID=24276603

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960061584A Expired - Lifetime KR100431975B1 (ko) 1995-12-07 1996-12-04 분기에의한중단이없는파이프라인방식의마이크로프로세서를위한다중명령디스패치시스템

Country Status (5)

Country Link
US (1) US5809324A (https=)
EP (1) EP0778519B1 (https=)
JP (1) JP3779012B2 (https=)
KR (1) KR100431975B1 (https=)
DE (1) DE69626263T2 (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6289437B1 (en) 1997-08-27 2001-09-11 International Business Machines Corporation Data processing system and method for implementing an efficient out-of-order issue mechanism
US6289442B1 (en) * 1998-10-05 2001-09-11 Advanced Micro Devices, Inc. Circuit and method for tagging and invalidating speculatively executed instructions
US6910123B1 (en) * 2000-01-13 2005-06-21 Texas Instruments Incorporated Processor with conditional instruction execution based upon state of corresponding annul bit of annul code
US6976150B1 (en) * 2000-04-06 2005-12-13 The Board Of Governors For Higher Education, State Of Rhode Island And Providence Plantations Resource flow computing device
US7072998B2 (en) * 2003-05-13 2006-07-04 Via Technologies, Inc. Method and system for optimized FIFO full conduction control
US7636837B2 (en) 2003-05-28 2009-12-22 Fujitsu Limited Apparatus and method for controlling instructions at time of failure of branch prediction
US7949861B2 (en) * 2005-06-10 2011-05-24 Qualcomm Incorporated Method and apparatus for managing instruction flushing in a microprocessor's instruction pipeline
US8127115B2 (en) * 2009-04-03 2012-02-28 International Business Machines Corporation Group formation with multiple taken branches per group
KR20130066402A (ko) * 2011-12-12 2013-06-20 삼성전자주식회사 트레이스 데이터 저장 장치 및 방법
US9122424B1 (en) * 2013-07-18 2015-09-01 Western Digital Technologies, Inc. FIFO buffer clean-up

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4833599A (en) * 1987-04-20 1989-05-23 Multiflow Computer, Inc. Hierarchical priority branch handling for parallel execution in a parallel processor
JP2845646B2 (ja) * 1990-09-05 1999-01-13 株式会社東芝 並列演算処理装置
US5493669A (en) * 1993-03-03 1996-02-20 Motorola, Inc. Data processor for simultaneously searching two fields of the rename buffer having first and second most recently allogated bits
US5644779A (en) * 1994-04-15 1997-07-01 International Business Machines Corporation Processing system and method of operation for concurrent processing of branch instructions with cancelling of processing of a branch instruction
US5598546A (en) * 1994-08-31 1997-01-28 Exponential Technology, Inc. Dual-architecture super-scalar pipeline
US5542109A (en) * 1994-08-31 1996-07-30 Exponential Technology, Inc. Address tracking and branch resolution in a processor with multiple execution pipelines and instruction stream discontinuities

Also Published As

Publication number Publication date
DE69626263D1 (de) 2003-03-27
KR970049478A (ko) 1997-07-29
EP0778519A2 (en) 1997-06-11
EP0778519A3 (en) 1998-06-10
JPH09274565A (ja) 1997-10-21
US5809324A (en) 1998-09-15
EP0778519B1 (en) 2003-02-19
DE69626263T2 (de) 2004-02-05
JP3779012B2 (ja) 2006-05-24

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