KR100431702B1 - Cell Based Ethernet Switch System - Google Patents

Abstract

The present invention relates to a cell-based Ethernet switch system to operate a single Ethernet switch in units of frames and to connect a plurality of the single Ethernet switches to configure a switch system in a cell unit.

The present invention is to perform the local switching in the frame unit and to transfer information through the respective bus protocol, and when connecting a plurality of switches to configure the switch system by performing the connection between the switches by cell unit, It can improve the performance of the switch and be easy to expand when configuring the system.

Description

Cell Based Ethernet Switch System

The present invention relates to a cell-based Ethernet switch system, and in particular, to operate a single Ethernet switch in units of frames and to connect a plurality of the single Ethernet switches to configure a switch system, a cell in which connections between switches operate in units of cells. An Ethernet switch system is based.

In general, an Ethernet switch is a device for switching a Layer 2 Ethernet frame, and most switches can be largely composed of four modules.

Here, the module includes a module for transmitting and receiving data to and from the PHY chip through MII or RMII, a module for determining forwarding by referring to an address table and a VLAN table, and storing and scheduling a frame in a buffer according to the forwarding information. It may be composed of a module for switching and a module responsible for transmitting and receiving with other switches.

In addition, the system may be configured as a central switch that is responsible for switching between the Ethernet switch.

Then, the Ethernet switch reads a frame by accessing the PHY terminal through MII or RMII as described in 'IEEE 802.3', analyzes the header of the frame, and then extracts the forwarding information. It can be switched or transferred to another Ethernet switch and sent back to the PHY via MII or RMII.

However, since the Ethernet switch as described above operates the frame as a basic unit, it is difficult to use the buffer efficiently, and when the system is configured through the central switch, the configuration of the central switch is difficult to expand the capacity. .

In order to solve the problems as described above, the present invention is to operate a single Ethernet switch for switching a layer 2 frame frame-by-frame and to connect a plurality of the single Ethernet switch to configure the switch system when configuring a switch system It is intended to be suitable for a large capacity Ethernet switch system by operating on a cell basis.

In addition, the present invention improves the performance of the switch and system configuration by performing switching in the local unit of frame, transfer information through each bus protocol, and perform the connection between the switches in the unit of cell, The purpose is to make it easy to expand the city.

1 is a block diagram illustrating a cell-based Ethernet switch system according to an embodiment of the present invention.

FIG. 2 is a detailed block diagram illustrating a Fast Ethernet Switching Block (FESB) in FIG. 1. FIG.

3 is a detailed block diagram showing a global switching block (GSB) in FIG.

FIG. 4 is a block diagram for explaining H-BUS in FIG. 2. FIG.

FIG. 5 is a diagram illustrating a signal configuration and signal timing of an H-BUS in FIG. 2; FIG.

FIG. 6 is a diagram illustrating a structure of address resolution information (ARI) in FIG. 5; FIG.

FIG. 7 is a block diagram for explaining an M-BUS in FIG. 2. FIG.

FIG. 8 is a diagram illustrating a signal configuration and signal timing of an M-BUS in FIG. 2.

FIG. 9 is a diagram showing a structure of control information in FIG. 8; FIG.

FIG. 10 is a block diagram illustrating a T-BUS in FIG. 2. FIG.

FIG. 11 is a view showing a signal configuration and signal timing of a T-BUS in FIG. 2; FIG.

FIG. 12 is a diagram showing the structure of control information in FIG. 11; FIG.

FIG. 13 is a block diagram illustrating a U-BUS in FIG. 2; FIG.

FIG. 14 is a diagram showing a signal configuration and signal timing of a U-BUS in FIG. 2; FIG.

FIG. 15 is a diagram illustrating a header format of a U-cell in FIG. 14.

Explanation of symbols on the main parts of the drawings

100: ECM (Ethernet Control Module) 200: FESB

300: GSM (Global Switch Module) 400: Main CPU

500: PCI (Program Controlled Interrupt) Bridge

600: Memory 700: Peripherals

800: GSB Port # 1 ~ Port # 16: Port

PHY # 1 ~ PHY # 16: PHY (Physical Layer Protocol) Chip

210: MCB (Media Control Block)

211: Receive MII (Media Independent Interface)

212: Transmit MII 213: MAC (Media Access Control)

216: Switch Access Control Unit

217: H-Interface Slave Block (HISB)

218: M-Interface Slave Block (MISB)

219TISB (T-Interface Slave Block)

220: Address Resolution Block (ARB)

221: Ingress Control Unit

222: Address Look-up Unit

223 Forwarding Decision Unit

224: Table Control Unit

225: HI-Interface Master Block (HIMB)

230: CPU 240: CPU Interface

250: ICB (Interdevice Control Block)

251: U-Down Link Receive Interface

252: U-Up Link Transmit Interface

260: Data Buffer 270: LSB (Local Switching Block)

271: schedule unit

272: Egress Control Unit

273 U-Cell Control Unit

274: Buffer Control Unit

275: MI-Interface Master Block (MIMB)

276: T-Interface Master Block (TIMB)

280, 830: finite state machine control unit

290 Registers 291 Address Table

292 virtual local area network (VLAN) tables

214, 215, 293, 294, 820, 840, 860, 870: Buffer

810: CIB (CPU Interface Block)

811: Packet Reassembly Unit

812: PCI Interface

813: Packet Segmentation Unit

850: Crossbar Switch Block (CSB)

880: Interdevice Control Block (ICB)

881: U-Up Link Receive Interface

882: U-Down Link Transmit Interface

Cell-based Ethernet switch system according to an embodiment of the present invention for achieving the above object to perform the local switching in the frame unit, transfer information through each bus protocol, and connect a plurality of switches When configuring a switch system, it is characterized in that the connection between the switches is performed in units of cells.

Preferably, the switch system is a chip set capable of switching Fast Ethernet without blocking, and includes a plurality of Local Ethernet Switch (LES) chips for switching Fast Ethernet ports, and a GAS connected to the plurality of LES chips to switch links. (Global ATM Switch) It is characterized in that it comprises a chip.

The LES chip may include a plurality of media control blocks (MCBs) for transmitting and receiving data to and from each physical layer protocol (PHY) chip through a media independent interface (MII); An address resolution block (ARB) for determining forwarding by referring to an address table and a virtual local area network (VLAN) table; A local switching block (LSB) for storing and scheduling a frame in a data buffer according to the forwarding information; Characterized in that it comprises an ICB (Interdevice Control Block) responsible for transmitting and receiving with other LES chip through the GAS chip.

Also preferably, the switch system comprises: an H-interface which transmits a header of a frame received from each MCB to the ARB and transmits information based on an address lookup from the ARB to each MCB; An M-interface for transmitting a header of a frame received from the ARB to the LSB in each MCB; A tie-interface for transmitting the transmission frame scheduled in the LSB to the respective MCBs; And a u-interface for performing data transmission and reception between the plurality of LES chips and the GAS chip.

Further preferably, the GAS chip has one Program Controlled Interrupt (PCI) interface to be connected to the main CPU separately, and controls communication with the main CPU to control the reassembly of the packet, the PCI interface and the separation of the packet. A CPU interface block (CIB) that plays a role; A crossbar switch block (CSB) for performing ATM switching to perform crossbar switches, virtual output queuing, and throughput; It characterized in that it comprises a plurality of ICB for transmitting and receiving data with the plurality of LES chips. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

A cell-based Ethernet switch system according to an embodiment of the present invention, that is, a Fast Ethernet Switch (FES) Chip Set is a chip set capable of switching 100 (Mbps) Fast Ethernet without blocking. , LES (Local Ethernet Switch) chip to switch 100 (Mbps) Fast Ethernet port, and GAS (Global ATM Switch) chip to switch 4 (Gbps) Link, as shown in Figure 1, The LES chip corresponds to the ECM 100 and the GAS chip corresponds to the GSM 200.

In addition, the cell-based Ethernet switch system according to an embodiment of the present invention for the four system interfaces (ie, H-interface, M (M) -interface, T-T-) for communication between each component block Interface and U-interface).

Here, the capacity of the entire system is determined according to the number of links connected to the ECM 100, and the capacity of the GSM 200 is determined according to the number of ports. Hereinafter, the ECM 100 is configured as 16 ports (Port # 1 to Port # 16) so that the present invention can be more easily understood, and the corresponding GSM 200 is described as being composed of four links.

In addition, the four ECM 100 and the GSM 200 are matched to each other through the U-BUS, each of the ECM 100 is connected to a plurality of terminals (LAN) of the LAN A port (Port # 1 to Port # 16), a plurality of PHY chips (PHY # 1 to PHY # 16), and an FESB 200, and the corresponding GSM 300 includes a main CPU 400, PCI bridge 500, memory 600, peripheral device 700, and GSB 800. Here, the U-BUS is made by a U-interface defining the transmission between the four ECM 100 and the GSM (200).

The LES16 chip, i.e., the FESB 200 in each ECM 100, is largely composed of four modules, as shown in FIG. 2, through the RMII and the respective PHY chips (PHY # 1 to PHY # 16). A plurality of MCBs 210 for transmitting and receiving data, an ARB 220 for determining forwarding with reference to the address table 291 and a VLAN table 292, and a frame are stored in the data buffer 260 according to the forwarding information. LSB 270 for scheduling and ICB 250 for transmitting and receiving with other ECM 100 through the GSM (200). The FESB 200 may include a CPU 230, a CPU interface 240, a data buffer 260, an FSM controller 280, a plurality of registers 290, an address table 291, It further comprises a VLAN table 292, a plurality of receive buffers 293, and a plurality of transmit buffers 294.

Each MCB 210 exchanges header information and forwarding information with the ARB 220 through RMII, MAC, Framing, H-BUS, and M-BUS. Forwarding information and transmission of the frame to the LSB 270, reception of the transmission frame via the T-BUS from the LSB 270, and the like, including a reception MII 211 and a transmission MII. 212, MAC 213, receive buffer 214, transmit buffer 215, switch access control unit 216, HISB 217, MISB 218, and TISB 219. It is made to include. Here, the H-BUS is made by H-Interface, which is a bidirectional interface protocol for exchanging header information and forwarding information between each MCB 210 and the ARB 220, and the M-bus. (M_BUS) is made by the M-interface for sending data and forwarding information from each MCB (210) to the LSB (270), the corresponding T-BUS (T-BUS) from the LSB (270) to scheduling By a tie-interface for transmitting a frame to each MCB (210).

The ARB 220 performs ingress control, address lookup, forwarding decision, and the like, and includes an ingress control unit 221, an address lookup unit 222, a forwarding determination unit 223, and a table control unit. 224, and HIMB 225.

The ICB 250 includes a U-downlink reception interface 251 that plays a 2 (Gbps) reception matching role and a U-uplink transmission interface 252 that performs a 2 (Gbps) transmission matching role. It is done by

The LSB 270 performs scheduling, egress control, cell separation and reassembly, buffer control, and the like. The scheduler 271, the egress controller 272, and the U-cell controller ( 273, a buffer control unit 274, a MIMB 275, and a MIMB 276.

The GAS4 chip, that is, the GSM 200 may be connected to the four ECMs 100 and includes one PCI interface 812 and is separately connected to the main CPU 400. As shown in FIG. 3, the GSB 800 therein includes a CIB 810 for controlling communication with the main CPU 400, a CSB 850 for performing ATM switching, and the four ECMs 100. It includes a plurality of ICB (880) for transmitting and receiving data with. In addition, the GSB 800 includes a CIB side transmit buffer 820, an FSM controller 830, a CIB side receive buffer 840, a plurality of ICB side receive buffers 860, and a plurality of ICB side transmit buffers. 870 is further included.

In addition, the CIB 810 performs a role of packet reassembly, PCI interface, packet separation, etc., and includes a packet reassembly unit 811, a PCI interface 812, and a packet separator 813. It is done by

The CSB 850 plays a role of a 5 × 5 cross-bar switch, virtual output queuing, 20 (Gbps) throughput, and the like.

Each of the ICBs 880 includes a U-uplink receiving interface 881 serving as a 2 (Gbps) matching match, and a U-downlink transmitting interface 882 serving as a 2 (Gbps) transmitting matching. It is made to include.

Operation of the cell-based Ethernet switch system according to an embodiment of the present invention will be described for each interface as follows.

First, in the case of H-interface, each MCB 210 transmits a header of a frame received from the ARB 220 and transmits information based on the address lookup from the corresponding ARB 220 to each MCB 210. I use it to do it.

As shown in FIG. 4, the H-interface has H-BUS, which is a bi-directional data bus of 64 (Bits), and in the HIMB 225 provided in the ARB 220, the H-bus (H_BUS) controls the use of the HISB 217 provided in each MCB (210) writes or reads data on the H-BUS (H_BUS) according to the control signal applied from the HIMB (225) Do it.

And, the signal configuration and operation timing of the H-BUS (H_BUS) is shown in Figure 5, the signal of the H-BUS (H_BUS) is the AR (Address (AR) from the respective MCB (210) to the ARB 220 Resolution) Request signal (AddrResol_Request #), the data bus write permission signal (HeaderWrite_Enable) from the ARB 220 to the MCB 210 requesting the AR, and the ARB 220 to the MCB 210 requesting the AR. A data bus read permission signal InformRead_Enable, a selection address Addr [3: 0] of each MCB 210 in the ARB 220, and a data bus between the ARB 220 and the MCB 210. There is a signal Data [63: 0].

The data transmitted by the H-interface includes received frame header information transmitted when each MCB 210 requests an AR to the ARB 220, and the ARB 220 requests the corresponding AR after the AR is terminated. There are two types of ARIs that are sent to the MCB 210.

Here, the received frame header information is information from the first byte to the eighteenth byte of the frame received in the input FIFO of the MCB 210. Among the Ethernet frame formats, DA (Destination Address) and SA (Source Address) are included. And the maximum length from which the value of the VLAN ID (VID) can be obtained. In order to transmit the received frame header information, the MCB 210 receives the data bus write permission signal (HeaderWrite_Enable) from the ARB 220 and then sequentially receives the received frame header information three times from the next clock. Will be recorded on At this time, the structure of the data recorded on the data bus depends on the type of the received Ethernet frame.

The ARI is information transmitted from the control information read from the address table 291 by the address lookup in the ARB 220 to the MCB 210 until the frame is output to the output port. It has a structure as shown in the figure, which includes a multicast (M), an output device number (ODN), an output port number (OPN), and a priority. ), VLAN ID index (VIDx), VLAN device mapping (VDM), and VLAN port mapping (VPM).

The H-interface performs operations in the following order after system initialization.

First, when a system reset signal (/ Sys_Reset) is applied, the HIMB 225 and the HISB 217 initialize all the variables, and then each HISB 217 receives the first 64 bytes of the frame. Assert an AR request signal (AddrResol_Request #) to the.

Accordingly, the HIMB 225 selects one of the asserted AR request signals AddrResol_Request # by a round robin method, and transmits the address of the HISB 217 that sends the selected signal to the address bus. Write and assert data bus write permission signal (HeaderWrite_Enable), and ignore the AR request signal (AddrResol_Request #) that is applied after this.

Accordingly, the HISB 217 receiving the asserted data bus write permission signal (HeaderWrite_Enable) records the first 24 (Byte) of the frame as the header of the frame and writes the data bus three times in succession (8 bytes). The remaining HISB 217 continues to perform the AR request signal assertion operation as described above.

Then, after reading the header, the HIMB 225 analyzes the header by the above-described Ethernet frame analysis method, and then writes the address analysis information by the address lookup to the data bus and the data bus read permission signal (InformRead_Enable). Assemble

Secondly, in the case of the M-interface, the MCB 210 is used to transmit the header of the frame received from the ARB 220 to the LSB 270.

As shown in FIG. 7, the M-interface has an M-bus (M_BUS), which is a unidirectional data bus of 64 (Bits). In the MIMB 275 provided in the LSB 270, the M-bus (M_BUS) controls the use of the MISB 218 provided in each MCB (210) to write data on the corresponding M-BUS (M_BUS) in accordance with the control signal applied from the corresponding MIMB (275). .

And, the signal configuration and operation timing of the M-BUS (M_BUS) is shown in Figure 8, the signal of the M-BUS (M_BUS) to the transmission request signal from the respective MCB (210) to the LSB (270) (Transfer_Request #), the transmission permission signal (Transfer_Enable) from the LSB 270 to the MCB 210 that requested the transmission, and the selection address (Addr [3: 0) of each MCB 210 in the LSB 270. ) And a data bus signal Data [63: 0] from each MCB 210 to the LSB 270.

Each MCB 210 records the control information necessary for processing the corresponding frame in the LSB 270 together with the received frame data on a data bus. The frame data is transmitted in units of 64 (Byte), and the corresponding control information. As shown in Fig. 9, the frame type (Frame Type) (FT), frame state (FS), multicast (M), output device number (ODN), and output port are shown in FIG. Number (OPN), priority, VLAN ID index (VIDx), VLAN device mapping (VDM), and VLAN port mapping (VPM).

The M-interface performs operations in the following order after system initialization.

First, when a system reset signal (/ Sys_Reset) is applied, the MIMB 275 and the MISB 218 initialize all the variables, and then each MISB 218 sets the H-interface from the ARB 220. In case ARI is known through, it asserts a transfer request signal (Transfer_Request #).

Accordingly, the MIMB 275 selects one of the asserted transmission request signals Transfer_Request # by a round robin method, and writes an address of the MISB 218 to which the selected signal is sent to an address bus and transmits a transmission permission signal. Assert (Transfer_Enable), and ignore the transfer request signals (Transfer_Request #) that are applied afterwards.

Accordingly, the MISB 218 receiving the asserted transfer permission signal Transfer_Enable sequentially records the switching control information and the frame data on the data bus.

Thirdly, in the case of a tie-interface, a transmission frame scheduled in the LSB 270 is used to transmit to each MCB 210.

The T-interface has a T-BUS, which is a unidirectional data bus of 64 (Bits), as shown in FIG. 10. In the TIMB 276 provided in the LSB 270, the T-bus (T_BUS) is controlled, and the TISB 219 provided in each MCB 210 reads data on the corresponding T-BUS according to a control signal applied from the corresponding TIMB 276. .

And, the signal configuration and operation timing of the T-BUS (T_BUS) is shown in Figure 11, the signal of the T-BUS (T_BUS) is a signal capable of receiving from the respective MCB (210) to the LSB (270) (Transfer_Avail #), the transmission start signal (Transfer_Enable) from the LSB 270 to the receivable MCB 210, and the selection address (Addr [3: 0]) of each MCB 210 in the LSB 270. ) And a data bus signal Data [63: 0] from the LSB 270 to each MCB 210.

The LSB 270 records the control information necessary for processing the corresponding frame in each MCB 210 together with the transmission frame data on the data bus, and the frame data is transmitted in units of 64 (Byte), As shown in Fig. 12, the structure includes a frame type FT, a frame state FS, and an available byte length ABL.

The tie-interface performs an operation in the following order after system initialization.

First, when a system reset signal (/ Sys_Reset) is applied, all the variables are initialized in the TIMB 276 and the TISB 219, and then each TISB 219 can be received when the frame becomes transmittable. Assert the signal (Transfer_Avail #).

Accordingly, the TIMB 276 selects one of the asserted receivable signals Transfer_Avail # according to a scheduling policy, writes the address of the TISB 219 which has sent the selected signal to the address bus, and transmits the transmission start signal ( Transfer_Enable), and transfer control information and frame data are sequentially recorded on the data bus. After this, the receiveable signals Transfer_Avail # applied are ignored.

Accordingly, the TISB 219 receiving the asserted transmission start signal Transfer_Enable reads the transmission control information and the frame data sequentially onto the data bus.

Fourthly, in the case of a U-interface, as shown in FIG. 13, a connection protocol for data transmission and reception between four ESMs 100 and GSM 300 is shown.

Each of the ESMs 100 is performed in units of frames in the case of internal switching, and in units of ATM cells in the case of switching with other ESMs 100, thereby providing FESB ( LSB 270 of 200) separates the frames that need to be transmitted to the outside and makes 53 (Byte) ATM cells and applies them to the ICB 250 of the corresponding FESB 200, which is in charge of the U-interface, and vice versa. The cell received by the ICB 250 is reassembled into a frame.

The U-interface has the same signal configuration as UTOPIA (Universal Test Operations PHY Interface for ATM), and transmits and receives at ICB 880 of GSB 800 that operates point-to-point and is provided in GSM 300. Has control of the bus. In addition, since the data bus is 16 (Bit), each link maintains a clock speed of 125 (MHz) to achieve a speed of 2 (Gbps).

And, the signal configuration and operation timing of the U-BUS (U_BUS) is shown in Figure 14, the signal of the receiving side U-BUS (U_BUS) 125 (MHz (MHz) from the GSM 300 to the ESM 100 (MHz) ) A transmission clock (UrxClk), a signal (/ UrxClav) indicating that there is a cell to be transmitted by the ESM (100), a transmission start signal (/ UrxEnb) from the GSM (300) to the ESM (100), There is a data bus signal (UrxData [15: 0]) from the ESM 100 to the GSM 300, and the signal of the transmitting U-BUS (U_BUS) is 125 from the GSM 300 to the ESM 100. (MHz) a transmission clock (UtxClk), a signal (/ UtxClav) to indicate that there is a cell to be sent from the ESM 100, and a transmission start signal (/ UtxEnb) from the GSM (300) to the ESM (100) And a data bus signal UtxData [15: 0] from the GSM 300 to the ESM 100.

The U-interface data is defined as a cell having a certain size. Here, the U-interface data has a structure similar to an ATM cell including a header of 5 bytes and a payload of 48 bytes, but the present invention is not limited thereto. It should be well understood that it is not necessary to have the same structure as an ATM cell.

In particular, in the present invention, the format of the header has a different structure from that of a standard ATM cell. A cell having such a header is called a u-cell, and the header format of the corresponding u-cell is a destination device number (Destination Device) as shown in FIG. 15. Number (DDN), Source Device Number (SDN), Destination Port Number (DPN), Cell Type (CT), Multicast (M), And a VLAN ID index (VIDx) and an end (E).

The U-interface operates according to the UTOPIA-1 protocol because the operating frequency and the width of the bus follow the protocol of UTOPIA-3, and the configuration is connected to the point-to-point.

As described above, according to the present invention, local switching is performed in units of frames, information is transmitted through respective bus protocols, and when a plurality of switches are connected to each other, a switch system is connected between switches. By doing so, it is possible to improve the performance of the switch and to easily expand the system configuration.

Claims (8)

Local switching is performed frame-by-frame, each bus protocol transmits information, and when a switch system is configured by connecting multiple switches, the connection between the switches is performed by cell unit. Cell-Based Ethernet Switch System. The method of claim 1, The switch system is a chip set capable of switching Fast Ethernet without blocking, and includes a plurality of LES (Local Ethernet Switch) chips for switching Fast Ethernet ports, and a GAS (Global ATM) for connecting links in connection with the plurality of LES chips. Switch) Cell-based Ethernet switch system comprising a chip. The method of claim 2, The LES chip includes a plurality of media control blocks (MCBs) for transmitting and receiving data with each physical layer protocol (PHY) chip through a media independent interface (MII); An address resolution block (ARB) for determining forwarding by referring to an address table and a virtual local area network (VLAN) table; A local switching block (LSB) for storing and scheduling a frame in a data buffer according to the forwarding information; Cell-based Ethernet switch system characterized in that it comprises an ICB (Interdevice Control Block) in charge of transmission and reception with other LES chip through the GAS chip. The method of claim 3, The switch system includes: an H-interface for transmitting a header of a frame received from the respective MCBs to the ARB and transmitting information based on an address lookup from the ARB to the respective MCBs; An M-interface for transmitting a header of a frame received from the ARB to the LSB in each MCB; A tie-interface for transmitting the transmission frame scheduled in the LSB to the respective MCBs; Cell-based Ethernet switch system comprising a u-interface for performing data transmission and reception between the plurality of LES chip and the GAS chip. The method of claim 4, wherein The MCB exchanges header information and forwarding information with the ARB through MII, Media Access Control (MAC), framing, and H-interface, forwarding information through an M-interface, and transfer of frames and the LSB to the LSB and through a T-interface. The cell-based Ethernet switch system, characterized in that the role of the reception of the transmission frame from the LSB. The method of claim 4, wherein The ARB performs a role of ingress control, address lookup and forwarding decision. The method of claim 4, wherein The LSB performs a role of scheduling, egress control, cell separation and reassembly, and buffer control. The method of claim 2, The GAS chip has a single Program Controlled Interrupt (PCI) interface to be connected to the main CPU separately. A CPU Interface Block (CIB) for controlling communication with the main CPU to perform reassembly of packets, PCI interface and packet separation; A crossbar switch block (CSB) that performs ATM switching to perform crossbar switches, virtual output queuing, and throughput; Cell-based Ethernet switch system comprising a plurality of ICBs for transmitting and receiving data with the plurality of LES chips.