KR100431316B1 - DRAM PACKAGE FOR FORMING 1Mx16 I/O DRAM AND 2Mx8 I/O DRAM BY USING ONLY ONE PACKAGE, ADDRESS LINE THEREOF, AND METHOD FOR CHANGING WIDTHS OF ADDRESS LINE AND DATA LINE - Google Patents

Abstract

PURPOSE: A DRAM package is provided to achieve a 1Mx16 I/O DRAM and a 2Mx 8 I/O DRAM by installing an address line and data line width control unit in a 1Mx16 I/O DRAM package. CONSTITUTION: A DRAM package includes a control signal input pin, address pins of n number, and data lines of q number. An address line and data line width control unit enables the address pins of n-1 number or enables the address pins of n number and the data pins of q/2 number according to a signal inputted into the control signal input pin. The address line and data line width control unit includes a data line controller(C1) for enabling the data pins of q/2 number or the data pines of q number and an address line controller(C2) for enabling the address lines of n-1 number or the address lines of n number.

Description

DRAM package and its address line and data line width changing method.

The present invention relates to a DRAM package and a method of changing its address line and data line width, and more particularly, to a DRAM package capable of using 1 mega x 16 I / O and 2 mega x 8 I / O and a change of its address line and data line width. It is about a method.

In the case of a 1 mega x l6 I / O DRAM, there are 10 address lines and 16 data lines. In the case of a 2 mega x 8 I / O DRAM, 11 address lines and 8 data lines are required.

The DRAM is composed of a small outline J-lead package according to the Joint Electron Device Engineering Council (JEDEC) standard. There are 16 data pins, and 12 of the 28 pins and 8 data pins of 2 pins for 2 mega x 8 I / O.

As described above, in the case of a 1 mega x 16 I / O DRAM, 10 address lines, 16 data lines, and in the case of a 2 mega x 8 I / O DRAM, 11 address lines, a data line Is based on the condition of 8, implementing 2 mega x 8 I / O in a 1 mega x 16 I / O DRAM package, so that 1 mega x 16 I / O DRAM and 2 mega x 8 I / O in one package It is an object of the present invention to provide a DRAM package and a method of changing an address line and a data line thereof.

1 is a block diagram for explaining an embodiment according to the present invention.

2 is a detailed circuit diagram for explaining an embodiment according to the present invention.

Explanation of symbols on the main parts of the drawings

Cl: data line control unit C2: address line control unit

TDI to TD8: PMOS transistor

TA1: NMOS Transistor

In order to achieve the above object, the present invention provides a DRAM package including one control signal input pin, n address pins, and q data pins, wherein the address pin n is based on a signal input to the control signal input pin. -A DRAM package and its address including internally address and data line width control means for enabling one and q data pins or for enabling n address pins and q / 2 data pins Provides a method for changing lines and data lines.

EXAMPLE

Hereinafter, the present invention will be described in more detail with reference to the drawings.

1 is a block diagram for explaining the present embodiment.

The address and data line width control means as shown in FIG. 1 performs an operation as shown in Table 1.

TABLE 1

That is, according to the present embodiment, the width of the address line and the width of the data line are changed to 10 and 16, or 11 and 8, respectively, according to the logic level of the control signal, thereby changing the type of DRAM to 1M x l6I /. Determined by O or 2M x 8I / O.

2 is a detailed circuit diagram of the address and data line width control means according to the present embodiment.

In FIG. 2, C1 represents a data line controller and C2 represents an address line controller.

In this embodiment as shown in Fig. 2, the control signal input terminal is an A11 pin, which is one of two dummy address pins of 1 Mega x 16 I / O. However, in another embodiment, the control signal input terminal may be another dummy address pin A10.

The A10, which is the other one of the dummy address pins, is enabled or disabled by using only one input of the address line control unit C2 operated by the control signal, and the address line width of the DRAM package is set to 10 or 11 pieces. Change. However, in another embodiment, the input terminal of the address line controller C2 may be another A11 pin, which is another dummy address pin.

In addition, an even (hereinafter referred to as even) data pin is used as an input terminal of the data line controller C1 to change the data line width to eight or sixteen in accordance with the control signal from A11. However, in another embodiment, an odd odd data pin may be an input terminal of the data line controller C1.

In the present embodiment, as shown in FIG. 2, the data line controller C1 includes eight PMOS transistors TD1 to TD8 having respective gates connected to the A11 pins and even data pins connected to the sources. .

In addition, the address line controller C2 includes an NMOS transistor electrically connected to the data line controller C1 having a gate connected to an A11 pin and a source thereof connected to an A10 pin.

Therefore, the circuit shown in FIG. 2 performs the operation as shown in Table 2.

TABLE 2

The operation shown in Table 2 includes a PMOS in the data line controller C1 and an NMOS electrically complementary to the address line controller. However, in another embodiment, the NMOS and the PMOS are respectively provided in the controller C1 and C2. In addition, the DRAM package for performing the operations as shown in Table 3 may be implemented.

TABLE 3

As described above, according to the present invention, by providing the address and data line width control means as described above in a 1 mega x 16 I / O DRAM package, one mega x l6 I / O DRAM and 2 mega x 8 I in one package. / O DRAM can be implemented.

Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (8)

In a DRAM package including one control signal input pin, n address pins, and q data pins, Address and data line width control means for enabling the address pins n-1 and q data pins or the address pins and q / 2 data pins according to the signal input to the control signal input pin DRAM package comprising a inside. The data line control unit of claim 1, wherein the address and data line control unit uses an input terminal as the q data pins and enables q / 2 or q of the q data pins according to the control signal. ; And And an address line controller configured to input the n terminal pins according to the control signal, and to enable n-1 or n of the n address pins. 3. The data line control unit of claim 2, wherein the data line control unit uses the q data pins as input terminals. Each source is connected to q / 2 data pins of the q data pins, and includes q / 2 transistors having respective gates connected to the control signal input pins. Each connected to q / 2 data lines in the DRAM package, The remaining q / 2 data pins of the q data pins are connected to q / 2 data lines in the DRAM package. The method of claim 2, wherein the address line control means uses the n address pins as input terminals, A source is connected to one address pin of the n address pins, and includes one transistor having a gate connected to the control signal input pin, and the drain of the one transistor is connected to one address line in the DRAM package. It is The remaining n-1 address pins of the n address pins are connected to n-1 address lines in the DRAM package. The DRAM package according to claim 3 or 4, wherein the transistor of the data line control means and the transistor of the address line control means are electrically complementary to each other. 6. The DRAM package of claim 5, wherein the transistor of the data line control means is an NMOS and the transistor of the address line control means is a PMOS. 6. The DRAM package of claim 5, wherein the transistor of the data line control means is a PMOS and the transistor of the address line control means is an NMOS. A method of changing an address line and a data line of a DRAM package including n + 1 address pins and q data pins, and including two dummy pins among the address pins. One of the dummy pins is used as a control signal input terminal, The other one of the dummy pins is used as an address line input terminal enabled or disabled according to a signal applied to the control signal input terminal. Q / 2 or q data pins are enabled according to the signal applied to the control signal input terminal, and address lines and data line widths are n-1 and q, respectively, according to the signal applied to the control signal input terminal. A method of changing the address line and data line width of a DRAM package enabling n or q / 2, respectively.

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