KR100431296B1 - A temperature detection circuit for a semiconductor device - Google Patents

Abstract

According to the present invention, a temperature detection circuit includes a first delay path including a plurality of inverters, a plurality of inverters, and some inverters have a gate connected to an output terminal and a drain connected to an input terminal. And a detection unit for determining which of a second delay path having a signal and a signal passing through the first delay path and a signal passing through the second delay path have reached first. Input terminals of the first delay path and the second delay path are connected to each other. According to such a configuration, there is an advantage that unnecessary current consumption in the semiconductor device can be reduced by appropriately adjusting the refresh period by detecting the temperature in the semiconductor device including the semiconductor memory device or the like.

Description

Temperature detection circuit for semiconductor devices {A TEMPERATURE DETECTION CIRCUIT FOR A SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to temperature sensing circuits for semiconductor devices, and more particularly to temperature sensing circuits for semiconductor devices that can be used to adjust refresh cycles with temperature for the purpose of reducing current consumption in DRAMs.

Data storage in DRAM is achieved by the accumulation of charge in the capacitor. At this time, since there is a leakage current of the PN junction capacitor itself of the MOS transistor, the amount of initial charge stored is lost, and thus data is lost. Therefore, before the data is lost, the data of the memory cell must be read and recharged to the initial charge amount in accordance with the read information. This operation must be repeated periodically to keep the data stored. This period is closely related to the process and structure of the capacitor and usually has a value of 128 ㎳ to 256 따라 depending on the capacity of the DRAM. This process of recharging the cell charge is called a refresh operation.

However, leakage current generally increases with increasing temperature. Therefore, the refresh cycle of DRAM is determined based on current consumption at high temperature. In this case, however, the same refresh cycle is used even at low temperatures, resulting in unnecessary current consumption.

Accordingly, an object of the present invention is to provide a temperature detection circuit for a semiconductor device that can be effectively used to adjust the refresh cycle according to temperature for the purpose of reducing unnecessary current consumption in a semiconductor memory device.

1 is a block diagram of a temperature detection circuit for a semiconductor device according to the present invention.

2 is a circuit diagram of a pulse generator that is a component of a temperature detection circuit according to the present invention.

3 is a circuit diagram of a comparator, which is a component of a temperature detection circuit according to the present invention;

4 is a circuit diagram of a detection unit that is a component of the temperature detection circuit according to the present invention.

5 is a signal waveform diagram in the circuit shown in FIGS.

6 is a diagram showing a result of a simulation of a temperature detection circuit for a semiconductor device according to the present invention;

In order to achieve this object, there is provided a temperature detection circuit for a semiconductor device of a novel configuration. According to the present invention, a temperature detection circuit includes a first delay path including a plurality of inverters, a plurality of inverters, and some inverters have a gate connected to an output terminal and a drain connected to an input terminal. A second delay path having a second delay path (wherein, the first delay path and the second delay path are connected to each other), and the signal via the first delay path and the second delay path. And a detection unit for determining which of the signals has reached first.

The MOS transistor is a PMOS transistor whose source is connected to a power supply terminal, or an NMOS transistor whose source is grounded. It is preferable for the stable operation to further include a pulse generator for widening the pulse width of the signal applied to the input terminal of the temperature detection circuit and applying it to the input terminals of the first and second delay paths. Preferably, the control unit further includes a control signal generator for delaying a signal output from an output terminal of the first or second delay path to generate a detector control signal having a predetermined pulse width, wherein the detector latches the determination result according to the detector control signal. do.

According to the configuration of the present invention as described above, unnecessary current consumption in the semiconductor element can be reduced by appropriately adjusting the refresh period by detecting the temperature in the semiconductor element including the semiconductor memory device or the like. In addition, the layout area can be reduced and the current consumption can be reduced compared to the temperature detection circuit using the current detection.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention; In the drawings, the same reference numerals are used to refer to the same or similar components and signals for the sake of consistency of description.

1 is a block diagram of a temperature detection circuit for a semiconductor device according to the present invention. As shown in FIG. 1, the temperature detection circuit according to the present invention includes a pulse generator 101, a comparison unit 103, and a detection unit 105. In FIG. 1, srefreq is a self refresh request signal, active is an output signal of the pulse generator 101, act and actb are control signals for the detector 103 generated by the comparator 103, in1. And in2 denote delay signals generated by the comparator 103 and temp_det indicate the temperature detection signals generated by the detector 105, respectively.

2 is a circuit diagram of a pulse generator that is a component of the temperature detection circuit according to the present invention. As shown in FIG. 2, the pulse generator 200 includes a first path 201 having no additional time delay, and a second path 203 having an additional time delay due to the plurality of inverters IV3 to IV10. ) And a NOR gate NR for performing a NOR operation on a signal via the first path 201 and the second path 203, respectively. In FIG. 2, srefreq is a self refresh request signal as in FIG. 1, and active is an output signal of the pulse generator 200. Since the self refresh request signal srefreq is a short pulse of 3 ms, the self-refresh request signal srefreq is used to generate a signal having a pulse width suitable for use by the comparator 103 using the pulse generator 200.

Referring to the detailed operation of the pulse generator 200 of FIG. 2, first, when the self-refresh request signal srefreq is at a low level for some time, the low level is applied to the two input terminals N1 and N2 of the NOR gate NR. Since the signal of is applied, the pulse generator output signal (active) has a low level. When the self refresh request signal changes from a low level to a high level as the self refresh period is reached, a high level signal via the inverters IV1 and IV2 is simultaneously applied to the first path 201 and the second path 203. Since the first path 201 has almost no additional time delay, the corresponding input terminal N1 of the NOR gate NR immediately changes to a high level. However, since the second path 203 delays a predetermined time with respect to the applied high level signal, the NOR gate corresponding to the second path 203 only passes a predetermined time after the node N1 changes to a high level. (NR) Input stage N2 changes to high level. The output signal active is high during a time interval in which only node N1 is high level and node N2 is still low level. Since the time delayed by the second path 203 is changed to the high level to the node N2, the two inputs of the NOR gate NR are at the high level so that the output signal active remains at the high level. When the time corresponding to the pulse width of the self refresh request signal srefreq has elapsed since the high level signal is applied to the node N1, the node N1 changes to the low level, but the node N2 still remains at the high level. The output signal is active at a high level because it is maintained. When the time obtained by adding the time delayed by the second path 203 and the time corresponding to the pulse width of the self-refresh request signal srefreq after the high level signal is applied to the node N1 has elapsed, the node N2 also has As it changes to the low level, the output signal active changes to the low level. In this way, the output signal active of the pulse generator 200 has a wider pulse width by the time delayed by the second path 203 than the self refresh request signal srefreq.

3 is a circuit diagram of a comparator, which is a component of the temperature detection circuit according to the present invention. As shown in FIG. 3, the comparator 300 according to the present invention includes a control signal generation circuit 301, a first delay path 303, and a second delay path 305. The first delay path 303 and the second delay path 305 are configured to have the same delay at a predetermined temperature (hereinafter referred to as "reference temperature"). In FIG. 3, active is an output signal of the pulse generator 200 as shown in FIG. 1, act and actb are detector control signals, and in1 is an output signal of the active signal via the first delay path 303. in2 is a signal in which the active signal is output via the second delay path 305.

First, as shown in FIG. 3, the control signal generation circuit 301 uses the output signal active of the pulse generator as it is as an input signal of the NAND gate ND1. The output signal in1 of one delay path 303 is used. The in1 signal is a signal whose active signal is delayed by the plurality of inverters IV13 to IV22. Therefore, there is a slight time difference between the change in the signal level at node N3, which is one input terminal of NAND gate ND1, and the change in the signal level at node N4, which is another input terminal of NAND gate ND1. When the node N3 changes from the low level to the high level, the node N4 is still at the low level, so the act signal is at the low level and actb is at the high level. When some time elapses from the time when the node N3 changes to the high level, the node N4 also changes from the low level to the high level, so the act signal changes to the high level and actb changes to the low level. When the active signal changes back to the low level, the act signal changes to the low level and actb changes to the high level despite the node N4 level.

There is a time difference between when the in1 signal changes to the high level and when the act and actb signals change. This is because the act and actb signals change only when the in1 signal passes through the inverters IV23 and IV24 and the NAND gate ND1. In comparison, there is only a slight time difference between the time when the active signal goes low and the time when the act and actb signals go low. This is because the act and actb signals change when the active signal passes through the NAND gate ND1 only. In this manner, after the in1 signal is changed from the low level to the high level and there is a time difference between the time at which the act and actb signals are changed, the change in in1 and in2 signals is sufficiently transmitted from the detector 105, and then act and actb This is to control the detector 105 by the signal so that the levels of the in1 and in2 signals are latched in the detector 105.

As shown in FIG. 3, the first delay path 303 is composed of a plurality of inverters IV13 to IV22, and the active signal applied to the input terminal of the first delay path 303 is delayed to some extent for the first time. It serves to be output from the output terminal of the delay path (303). In this case, the signal in1 output after passing through the first delay path 303 is greatly influenced by temperature, and thus the change of delay according to temperature is large. This is because the first delay path 303 is a gate delay using a normal transistor, so the current change according to temperature is large.

The second delay path 305 is not merely formed by the plurality of inverters IV26-IV37 like the first delay path 303, but a part of the plurality of inverters IV26-IV37 (IV28-IV36) is formed of the inverter. A MOS transistor having a gate connected to the output terminal and a drain connected to the input terminal of the inverter is further provided. In the case of inverters IV28, IV30, IV32, IV34, and IV36, NMOS transistors N0, N1, N2, N3, and N4 having a grounded source are connected to each other. In contrast, in the inverters IV29, IV31, IV33, and IV35, PMOS transistors P0, P1, P2, and P3 having a source connected to a power supply terminal are connected to each other. The first delay path 303 and the second delay path 305 are configured to have the same time delay at the reference temperature as described above.

The signal in2 output through the second delay path 305 does not have a large change in delay according to temperature compared to the output signal in1 of the first delay path 303. The reason for this is that the nodes nd0-nd8 have a small change with temperature due to the transistors NO-N4 and P0-P3.

4 is a circuit diagram of a detection unit that is a component of the temperature detection circuit according to the present invention. As shown in Fig. 4, the detection unit 400 according to the present invention includes the determination circuit 401, the switch circuit 403, and the latch circuit 405 as main components. In FIG. 4, in1 denotes an output signal of the first delay path 303, in2 denotes an output signal of the second delay path 305, det_sig denotes an output signal of the determination circuit 401, and act and actb denote a switch circuit ( The signal controlling 403, pwrupb indicates a signal indicating whether power is applied to the semiconductor element, and temp_det indicates an output signal by the detection unit 400 of FIG.

First, the determination circuit 401 is composed of two NAND gates ND2 and ND3 to which each output signal is fed back to the input terminal of the other as shown in FIG. The switch circuit 403 is composed of two PMOS transistors P4 and P5 and two NMOS transistors N5 and N6 and according to two control signals act and actb generated by the control signal generation circuit 301. The node N5 is provided with a signal that is enabled and inverts the det_sig signal. Since the pwrupb signal changes from a low level to a high level when power is applied to the semiconductor device and is maintained at a high level until power down, the node N5 maintains a high level before power is applied. Since the transistor P6 is turned off, the node N5 is disconnected from the power supply terminal. The latch circuit 405 consists of two inverters IV38 and IN39 whose output signals from the others are used as their input signals.

The configuration and operation of FIG. 4 will be described in detail with reference to FIG. 5. Initially, the int and in2 signals are at the low level, so the det_sig signal is at the high level. In this case, as shown in FIG. 5, when the in2 signal changes to a high level sooner than the in1 signal, the NAND gate ND3 outputs a low level and applies it to the input terminal of the NAND gate ND2. Then, a low level input signal is applied to the two input terminals of the NAND gate ND2, but the output signal det_sig of the NAND gate ND2 maintains a high level. The act signal changes from low level to high level with some time delay compared to the in1 and in2 signals, and the actb signal changes from high level to low level. As a result, the PMOS transistor P4 and the NMOS transistor N6 are turned on. Since the current det_sig signal is at a high level, the NMOS transistor N5 is turned on so that the node N5 has a low level. The low level signal is latched to the detection unit 400 by the latch circuit 405. The signal latched at 405 is output as a high level signal as shown in FIG. 5 via inverters IN38, IN40, IN41.

If both the in1 and in2 signals are at the low level and the in1 signal first goes to the high level as opposed to the previous case, the det_sig signal changes from the high level to the low level. Then, when the levels of the control signals act and actb are changed and the MOS transistors P4 and N6 are turned on, the PMOS transistor P5 is turned on and the node N5 has a high level. The high level signal at the node N5 is latched by the latch circuit 405 and output as a low level signal via the inverters IV38, IV40, IN41.

6 is a diagram showing a result of a simulation of a temperature detection circuit for a semiconductor device according to the present invention. In the temperature detection circuit according to the present invention, the reference temperature was 42 ° C. That is, the first delay path 303 and the second delay path 305 are configured to have the same delay amount at 42 ° C. The first delay path 303 delays the signal passing more than the second delay path 305 at higher than 42 ° C., for example at 46 ° C. and 44 ° C. Therefore, since the change of the in2 signal reaches the detection unit 400 faster than the in1 signal, temp_det outputs a high level signal. On the other hand, at less than 42 ° C., for example, 40 ° C., 38 ° C., and 36 ° C., since the change of the in1 signal reaches the detection unit 400 more quickly, temp_det outputs a low level signal.

The foregoing description is mainly related to an embodiment of the present invention, which has been mentioned in relation to the refresh cycle of the DRAM, but may be widely applied to any semiconductor device requiring temperature detection. The embodiments described herein are merely intended to enable those skilled in the art to easily understand and practice the present invention, and are not intended to limit the scope of the present invention. Therefore, those skilled in the art should note that various modifications or changes are possible within the scope of the present invention. The scope of the invention is defined in principle by the claims that follow.

According to the configuration of the present invention as described above, there is an advantage that unnecessary current consumption in the semiconductor element can be reduced by appropriately adjusting the refresh period by detecting the temperature in the semiconductor element including the semiconductor memory device or the like. In addition, the layout area can be reduced and the current consumption can be reduced as compared with a configuration using a conventional resistor and capacitor.

Claims (5)

In the temperature detection circuit for semiconductor elements, A first delay path composed of a plurality of inverters, A plurality of inverters, some inverters having a second delay path having a MOS transistor whose gate is connected to the output terminal and whose drain is connected to the input terminal, wherein the first delay path and the second delay The path is connected to the input of each other-- And a detector configured to determine which of the signals passing through the first delay path and the signal passing through the second delay path has arrived first. The MOS transistors are PMOS transistors whose source is connected to a power supply terminal, and NMOS transistors whose source is grounded. The first delay path has a large change in current according to temperature due to a gate delay using a normal transistor, and the second delay path has a small change in current according to temperature due to the PMOS transistor and the NMOS transistor. Temperature detection circuit. delete delete The method of claim 1, And a pulse generator for widening the pulse width of the signal applied to the input terminal of the temperature detection circuit and applying the input signal to the input terminals of the first and second delay paths. The method of claim 1, And a control signal generator for delaying a signal output from an output terminal of the first or second delay path to generate a detector control signal having a predetermined pulse width. And the detection unit latches a determination result in accordance with the detection unit control signal.