KR100431173B1 - Audio differential bus receiver for audio/video interconnection - Google Patents

Abstract

The audio bus receiver has a base electrode coupled to each bus receiver input terminal (1, 2) through each input resistor (R1, R2), an emitter electrode diode coupled to each current source (16, 20) and each load resistor (R7). And a pair of bipolar transistors Q1 and Q2 each having a collector electrode coupled to the reference precursor via R8). The emitters are coupled to each other via a gain control resistor R9 and the collector is coupled to the output terminal 28 through a differential amplifier 30. Preferably the receiver prevents signal input to the bus under power down conditions that do not require the use of a redundant power supply. In addition, high common mode rejection is achieved without requiring accurate matching of the device, only a single supply voltage is required for operation.

Description

AUDIO DIFFERENTIAL BUS RECEIVER FOR AUDIO / VIDEO INTERCONNECTION}

The present invention relates to an audio / video interconnect system, and more particularly to an audio differential bus receiver suitable for use in such a system.

Bus oriented bidirectional audio / video interconnect systems are known and are used to interconnect component audio / video devices such as, for example, video tape recorders, video disk players, television tuners, video cameras, video monitors, and the like. In a typical system, a common bus containing control, audio and video signals is "daisy chained" between the various devices, so that the bus can be "common" by all connected audio / video units. It is driven by a tri-state driver. Such a system is disclosed, for example, in US Pat. No. 4,581,645, registered April 8, 1986, the inventor being Bayer Junior, Jr., and entitled "DISTRIBUTED SWITCHED COMPONENT AUDIO / VIDEO SYSTEM".

Recently, the American Electronics Industry Association (EIA) has been reviewing the standards for interconnection for audio, video, and control for television devices. One of the standards proposed by this consideration is the interconnection of audio and video using twisted pair cables operated by tri-state balanced line drivers. The device is connected to the bus in a "daisy chain" manner, with the bus terminated with a 120 Ohm load on the first and last devices, and the intermediate device connected to an intermediate device with a relatively high impedance input connected for bridging operation. Terminated. One example of such a system is described in U.S. Application No. 08 / 294,146, filed Aug. 8, 1994, the inventor of White et al., Entitled TRI-STATE VIDEO DIFFERENTIAL DRIVER.

Important parameters for the audio bus receiver section of the proposed standard are: (i) bus audio differential signal level of 2.0 V RMS (± 20%), (ii) bus receiver common mode range of 5.0 V (± 2.0 V DC), and (iii) Minimum input impedance (with respect to receiver device on or off), DC-20 kHz and 1.5 K Ohms common mode, and (iv) common mode rejection ratio (CMRR) of 60 dB .

To provide redundant power or precision attenuation networks (to provide desired bus isolation under power down conditions) to meet these requirements, to meet gain and common mode requirements, and to provide single-ended conversion to differential Use of conventional techniques, such as selecting a feedback controlled op amp, may be considered. However, the combination of these conventional techniques can result in an overall receiver design that is overly expensive and complex to use in mass produced consumer products such as VCR receivers or television receivers.

There is a need for a simplified bus receiver that does not require the use of redundant power supplies, precision attenuation networks or feedback controlled op amps. The present invention is designed to meet the above requirements.

Embodiments of the invention, which are distinguished from single-ended audio bus receiver devices, each have a base coupled to each bus receiver input terminal via a resistor, each having an emitter coupled to a current source, each having a reference voltage through a load resistor. It has a bipolar transistor pair having a collector coupled to a member. The emitters are coupled to each other via a gain control resistor and the collectors are coupled to the output terminals through differential amplifiers.

1 illustrates in detail a differential audio bus receiver embodying the present invention.

2 shows a variant of the differential audio bus receiver of FIG.

* Description of the symbols for the main parts of the drawings *

1,2: input terminal

16,20: current source

28: output terminal

200: current mirror amplifier

30: differential amplifier

The foregoing and additional features of the invention are set forth in the accompanying drawings, in which like elements are designated by like reference numerals.

The bus receiver of FIG. 1 includes first and second PNP transistors Q1 and Q2. The first and second input resistors R1 and R2 are connected between the first and second signal input terminals 1 and 2 and the base electrodes of the first and second PNP transistors, respectively. The first and second constant current sources (parts 16 and 20 surrounded by dotted lines) are connected to emitter electrodes of the first and second PNP transistors Q1 and Q2 through respective first and second PN diodes CR1 and CR2. It is provided to have each output 18, 22 coupled respectively. The first and second collector load resistors R7 and R8 are coupled between each collector electrode of the first and second PNP transistors Q1 and Q2 and a reference potential power supply 14 connected to ground as shown. Emitter load resistor R9 is coupled between emitter electrodes of first and second transistors Q1 and Q2.

Differential amplifiers (dotted section 30) are first and second connected to respective collector electrodes of the first and second transistors Q1 and Q2 to provide a single ended output signal to the differential amplifier output terminal 28. It is provided to have inputs (24, 26 respectively).

For a differential amplifier of the type having a relatively low input offset voltage, the collector load resistors R7 and R8 of the input transistors Q1 and Q2 are substantially the same and the collector load path of the input transistors Q1 and Q2. It is chosen so that no offset voltage needs to be derived.

Certain differential amplifiers shown for use, such as amplifier 30, include a single bipolar transistor Q7 and require an input voltage offset. The DC offset is provided by the connection of two PN diodes CR3 and CR4 connected in series with the load resistor R7 of the input transistor Q1. Resistor R7 is also selected to provide a slightly less resistance value than collector load resistor R8. This adjustment compensates for the input offset of the differential amplifier 30 utilizing a single NPN transistor to provide differential to single ended (ie no differential) conversion.

In particular, it should be noted that the differential amplifier 30 ensures unconditional stability because it does not include any full feedback path. As mentioned above, to use a single transistor (eg Q7) as a differential / single-ended converter, a DC offset is added to the collector load at the input. In this embodiment of the invention, the DC offset is provided by diodes CR3 and CR4 connected in series with the Q1 collector load. Thus, the base of the input transistor Q7 of the amplifier 30 is connected to the collector of transistor Q1 (with a larger positive inactive load voltage), and the emitter is connected to the collector of input transistor Q2 ( Less positive load voltage).

The remaining elements of the differential amplifier 30 are coupled to the emitter follower output stage [PNP transistor Q9] and the base common amplifier stage [PNP] to couple the collector electrode of the differential amplifier input transistor Q7 to the input of the emitter follower output stage. Transistor Q8].

The base common stage comprises a PNP transistor Q8, whose base electrode is connected to a positive reference voltage source provided by a voltage divider comprising resistors R12 and R13 coupled between supply terminal 12 and ground. do. The reference voltage is filtered and smoothed by a capacitor C1 coupled between the resistor junction and the supply terminal at a common junction of the two resistors R12 and R13 and applied to the base of the transistor Q8. The emitter of the bait common connection transistor Q8 is connected to the collector of the differential amplifier input transistor Q7 and supplied by the resistor R10 (connected between the input of the base common stage and the supply terminal 12). The operating current for the transistor is used to regulate the collector voltage of the input transistor at a constant value. Thus, the collector voltage of transistor Q7 being regulated by base common stage Q2 is equal to the output of the potential divider smaller than the base emitter voltage drop of base common stage Q8.

The base common stage output voltage appears across the load resistor (R14) coupled between the collector of Q8 and ground. Capacitor C2 in parallel with the base common stage load resistor R14 functions as a low pass filter and has a time constant of about 1 kHz for the device value shown, thus limiting the high frequency response at about 160 kHz. The frequency is higher than the audio band but low enough to reduce high frequency video crosstalk and noise into the audio channel.

The overall gain for the differential input stages Q1 and Q2 and the differential amplifier 30 is determined by the value of the emitter load resistor R9 of the differential input stage and the collector load resistor R14 of the differential output stage. The net gain is approximately equal to the ratio of R14 / R9.

Base common stage Q8 as used in the present invention as it performs the function of what is commonly referred to as a "current mirror amplifier" to "reflect" or "reflect" the collector current of transistor Q7 from the positive supply rail. , R10 and base bias networks R11-R13 and C1) may be considered. In other words, the current mirror amplifier in this particular application is a suitable alternative to the illustrated base common amplifier stage. As shown in Fig. 2, the base common stage (by removing the transistor Q8 and its associated base bias network, connecting the " mirror " input to the collector of transistor Q7 and the mirror output to the load resistor R14). Q8) may be replaced by the current mirror amplifier 200.

In FIG. 2, the current mirror amplifier 200 (the portion enclosed by the dotted lines) includes a diode CR5 and a PNP transistor Q10. The anode of the diode is connected to the supply terminal 12 and the cathode is connected to the collector of transistor Q7 and the base of transistor Q10. The emitter and collector of transistor Q10 are connected to supply terminal 12 and load resistor R14, respectively. In operation, diode CR5 biases transistor Q10 to supply a collector output current to load resistor R14 that is proportional to the collector current supplied from transistor Q7 to the current mirror input. Except for this change, the overall operation is as described above for the base common stage.

In considering the emitter follower output stage of the differential amplifier 30, the stage is coupled to the base of the output of the base common stage (collector of Q8) and to the collector of reference reference 14 (i.e., ground). And an emitter coupled to supply terminal 12 through emitter load resistor R15 and a PNP transistor Q9 coupled to differential amplifier output terminal 28.

Current source 16 is a constant current source that uses two PNP transistors Q3 and Q5 to achieve accurate regulation that is essentially independent of voltage displacement at regulator output terminal 18. In particular, in current source 16, supply terminal 12 is directly coupled to the emitter of transistor Q5 and, via resistor R3, to the base of transistor Q5 and the emitter of transistor Q3. The base of transistor Q3 and the collector of transistor Q5 are both coupled to ground 14 via resistor R5, and the output current appearing at the collector of transistor Q3 is supplied to output terminal 18. The output current is approximately equal to Vbe of transistor Q5 divided by the value of resistor R3 and is about 1 mA for the exemplary value shown. Resistor R5 samples the collector current of transistor Q5, and generates a feedback voltage for transistor Q3 that turns off transistor Q3 when the current through R3 increases for a nominal value of 1 mA. Conversely, if the current through R3 decreases below its nominal value, the reduced voltage across resistor R5 changes the output current delivered to terminal 18 by driving transistor 93 to conduct more current. Prevent any tendency to Since the current source 20 is the same as the current source 16 (the resistors R4 and R6 and the transistors Q6 and Q4 are connected as the corresponding elements R3, R5, Q5 and Q3), the description is not repeated.

In operation, the differential bus receiver of FIGS. 1 and 2 is turned off (ie, terminal 12 voltage is zero) when the supply voltage is turned off due to the nature of the collector / base junction of Q1 and Q2 and the operation of diodes CR1 and CR2. When decremented, " off state " isolation from the bus connected to inputs 1 and 2 is achieved. In the case of "+ V" at ground or low potential and a positive common mode voltage at inputs 1 and 2, diodes CR1 and CR2 are reverse biased and do not conduct, separating the bus from ground. If Q1 and Q2 have no emitter current and the common-mode voltage is negative, neither the base nor the collector of Q1 and Q2 will conduct. Thus there is no loading of the input signal under the power off state. For power on, the input impedance is approximately R9 multiple of beta of transistors Q1 and Q2 and is a very high value. Since the input resistors (R1, R2) are much smaller than the product of R9 and beta, they contribute very little to the actual input impedance, but provide protection for the amplifier input.

If the maximum amplitude of the common mode voltage is lower than the breakdown voltage of the base-to-emitter of transistors Q1 and Q2, diodes CR1 and CR2 are not required and can be eliminated and the operation of the diodes be transistors Q1 and Q2 The same is done by base / emitter bonding. Also, if the maximum differential voltage across input terminals 1 and 2 is greater than the base to emitter breakdown voltages of Q1 and Q2, resistor R9 should be moved to the anode instead of the shown cathodes of diodes CR1 and CR2. However, emitters of transistors Q1 and Q2 are preferred for maximum circuit linearity of the junction of resistor R9 to cathode.

Specific considerations for the values of the collector load impedances R7, CR3, CR4 and R8 of the transistors Q1 and Q2 and the characteristics of the amplifier 30 ensure that the minimum voltage is resisted to ground to maintain the common mode region of the circuit. It is intended to be produced at both ends of (R7, R8). As an alternative, this is not necessary since a collector load can be returned to a negative supply if a negative supply is used and a conventional operational amplifier can be used as the differential amplifier 30. However, as mentioned above, for mass-produced consumer goods such as television receivers or VCR receivers, a single-supply operation is preferred over a split-supply operation.

Considering the effect of DC offset diodes CR3 and CR4, the differential current gain for the collector loads of transistors Q1 and Q2 is determined by the net resistive impedance of Q1 loads (i.e., CR3, CR4 and R7). It can be made substantially the same by selecting substantially the same as the value of the resistor R8). Diodes CR3 and CR4 are included to properly DC bias (offset) the differential amplifier transistor Q7. One of the diodes operates to approximately cancel Vbe of transistor Q7. The other diode acts as a DC " battery " to bias transistor 97 so that its potential added to the DC voltage across resistor R7 sets the voltage at the emitter of transistor Q7. This use of a diode operating as a DC battery is preferable to using a bias resistor from the positive power supply 12 to the base of the transistor Q7, which is on the output which tends to reduce the power removal rate of the entire bus receiver. This is because it does not induce power related dependencies. Although a slight shift in the DC output is caused within the operating temperature range due to Vbe not canceled for the diode, this is not important because the output will be AC coupled in an audio bus receiver application.

As described above, the base common amplifier transistor Q8 functions as a "current mirror amplifier" to reflect the signal current from the collector of the input transistor Q7 to ground through the load resistor R14. As explained, the alternative is to use a current mirror amplifier. In both cases, the purpose of the second stage of the differential amplifier is to cause a voltage across the load resistor R14 (and capacitor C2) related to ground. This is desirable to avoid supply voltage dependence on the output and thus maintain good power down. The AC voltage gain at the collector of transistor Q8 is approximately equal to the ratio of resistances R14 / R9. Capacitor C2 is provided to intentionally create some low pass function to reduce the susceptibility of subsequent circuits to small amounts of RF and video that may be picked up on the bus.

Transistor Q9 is only needed to provide a relatively low output impedance. Transistor Q9 and resistor R9 can be removed if the load impedance is relatively high so that the setting by resistor R14 and capacitor C2 does not affect gain or response, and the output is resistor R14. Can be obtained at both ends. It is desirable to take the output of transistor Q8 (FIG. 1) or transistor Q10 (FIG. 2) as the signal current, and resistor R14 by dropping R14 and C2 for the purpose of reducing the internal ground potential problem in certain applications. It should also be noted that there may be several applications for remotely sensing the output voltage across capacitor C2.

Provide a redundant power supply or precision attenuation network (provide the desired bus isolation under power down conditions) to meet the standard of the audio bus receiver section, and to meet gain and common mode requirements and to convert single-ended to differential The use of conventional techniques, such as selecting a feedback controlled operational amplifier to provide for this may be considered. However, this combination of prior art, which results in an overall receiver design, is excessively expensive and complex to use for mass-produced consumer products such as VCR receivers or television receivers.

The present invention thus provides a simplified bus receiver that meets the above standards and does not require the use of redundant power supplies, precision attenuation networks or feedback controlled operational amplifiers.

Claims (5)

A differential / single-ended converted audio bus receiver device, A base electrode coupled to each bus receiver input terminal (1, 2) through each input resistor (R1, R2), an emitter electrode diode-coupled to each current source (16, 20), and each load resistor (R7, R8). It includes a pair of transistors (Q1, Q2) each having a collector electrode coupled to the reference front panel through, The emitter electrodes are coupled to each other via a gain control resistor R9 and the collector electrodes are coupled to the output terminal 28 via a differential amplifier 30 having a single ended output stage. Bus receiver unit. 2. A device as claimed in claim 1, wherein at least one DC offset means (CR3, CR4) is coupled to one of the collector load resistors (R7, R8). 3. The differential amplifier (30) according to claim 2, wherein the differential amplifier (30) has an emitter and a base electrode connected to each of the collector electrodes of the pair of transistors (Q1, Q2) and has a collector electrode for generating a single ended output signal. A differential / single-ended converted audio bus receiver device comprising three transistors (97). 4. The apparatus of claim 3, wherein the differential amplifier (30) further comprises a current mirror amplifier coupling the single ended output signal to the output terminal (28). 4. The apparatus of claim 3 wherein the differential amplifier (30) further comprises a base common amplifier coupling the single ended output signal to the output terminal.