KR100418720B1 - Circuit for generating a erase voltage of flash memory cell - Google Patents

Abstract

An erase voltage control circuit of a flash memory cell according to the present invention includes first amplification means for amplifying a reference voltage to generate a first erase voltage of positive potential, and a second amplification for amplifying the reference voltage to generate a second erase voltage of negative potential. Means, a variable resistance means connected in series between the output terminal of the first amplifying means and the ground unit price, and a first resistor, and generating a first feedback voltage in accordance with the resistance ratio of the variable resistance means and the first resistor to generate the first amplification. A first amplification control means for controlling the amplification factor of the means, a second and third resistors connected in series between the output terminal of the second amplifying means and the ground unit cost, and according to the resistance ratio of the second and third resistors. A second amplification control means for generating a second feedback voltage to control the amplification rate of the second amplifying means, and a plurality of voltage drop means connected in series between the output terminals of the first and second amplifying means. A voltage divider for generating a predetermined divided voltage, a third amplifying means for amplifying the divided voltage, and storing data for adjusting a resistance value of the variable resistor means in accordance with an output voltage of the third amplifying means, Variable resistance control means for controlling the resistance value of the means.

Description

Circuit for generating a erase voltage of flash memory cell

The present invention relates to an erase voltage adjusting circuit of a flash memory cell, and more particularly, to an erase voltage adjusting circuit of a flash memory cell capable of stably generating an erase voltage of a constant flash memory device regardless of a change in a power supply voltage.

A general method of erasing a flash memory cell is as follows.

1 is a cross-sectional view of a typical flash memory cell.

Referring to FIG. 1, a typical flash memory cell includes a floating gate 12, a control gate 13, and source / drain 14a and 14b. A tunnel oxide film is formed between the floating gate 12 and the semiconductor substrate 11, and a dielectric film is formed between the floating gate 12 and the control gate 13 to electrically insulate.

In general, during the erase operation, after floating the source and drain 14a and 14b terminals, a first erase voltage of about 8 V is applied to the semiconductor substrate 11, and a voltage of about −8 V is applied to the control gate 13. 2 An erase voltage is applied.

When a voltage is applied under the above conditions, a strong magnetic field is formed between the control gate 13 and the semiconductor substrate 11, and the charges 15 stored in the floating gate 12 are discharged by FN-Nordheim Tunneling. The semiconductor substrate 11 is moved through the tunnel oxide film.

The threshold voltage (eg, about 2V) of the cell on which the erase operation is performed is lower than the threshold voltage (eg, about 5V) of the programmed cell. Since the threshold voltage of the cell is lowered by the erase operation, when a predetermined voltage (for example, about 5 V) is applied to the control gate 13 to read data stored in the cell, the semiconductor under the floating gate 12 is lowered. Channels are formed on the surface of the substrate 11 so that current flows from the drain 14b to the source 14a. This state is a state where 1 is stored in the cell. On the contrary, in the cell in which the program operation is performed, even if a predetermined voltage (for example, about 5V) is applied to the control gate 13, the channel is not formed by the high threshold voltage (5V) of the cell. No current flows through the source 14a. This state is a state where the data of the cell 0 is stored.

At this time, when the erase voltage of the flash memory cell changes, the erase speed of the cell changes as the erase voltage is high and low. That is, when the erase voltage is applied high, the erase speed of each cell becomes faster and the entire cell is over-erased.

In addition, the threshold voltage of the cell in which the erase operation is performed is not uniformly distributed due to the thin tunnel oxide film and various process factors. Thus, the threshold voltage distribution characteristic of the erase cell is relatively poor compared to the program cells. When the threshold voltage distribution of the erased cells is not uniform, a leakage current is generated by some over erased cells among the cells sharing the same bit line while reading data stored in the cell or programming the cell, thereby causing malfunction. .

Hereinafter, an erase voltage generation circuit for generating an erase voltage will be described. 2 is a conventional erase voltage generation circuit.

As shown in FIG. 2, the erasing voltage generating circuit includes a reference voltage generating means 110 for generating a reference voltage Vref, a positive high voltage generating means 120 for generating a positive high voltage, and a negative high voltage generation for generating a negative high voltage. The first means 130, the first amplifying means 140 for receiving a positive high voltage to amplify the reference voltage (Vref) to generate a first erase voltage (V _PP ) of a positive potential, the reference voltage (Vref) To adjust the amplification rate of the first amplifying means 140, comprising a second amplifying means 150 and first and second resistors R11 and R12 that amplify the negative voltage to generate a second erase voltage V _EE . The first feedback circuit 160 and the third and fourth resistors (R13 and R14) is composed of a second feedback circuit 170 for adjusting the amplification rate of the second amplifying means 150.

The first and second amplifying means 140 and 150 use an OP AMP (Operation Amplifier). The first amplifying means 140 receives a positive high voltage as a driving voltage to amplify the reference voltage Vref to generate a first erasing voltage V _PP of positive potential to be applied to the semiconductor substrate of the cell C11 during the erasing operation. do. In addition to the means for amplifying the reference voltage Vref, the first amplifying means 140 feeds back an output signal to adjust the first erase voltage V _PP to a stable voltage. In addition, the second amplifying means 150 receives a negative high voltage as a driving voltage to amplify the reference voltage Vref, so that the second erasing voltage V _EE of the negative potential to be applied to the control gate of the flash memory cell C11 during the erase operation. ) Similarly, the second amplifying means 150 feeds an output signal in addition to the means for amplifying the reference voltage Vref to adjust the second erase voltage V _EE to a stable voltage.

However, due to the process change occurring in the process of manufacturing the elements constituting the circuit (particularly, the resistor and the transistor), the first and second erase voltages V _PP and V as shown in Equations 1 and 2 below. _EE ) is changed to change the gain value (Gain Value) with respect to the reference voltage (Vref).

In Equation 1, V _P0 is a target voltage of the first erase voltage V _PP , and ΔV _PP is an amount of change in voltage.

In Equation 2, V _E0 is a target voltage of the second erase voltage V _EE , and ΔV _EE is an amount of change in voltage.

Therefore, the erase voltage difference between the semiconductor substrate and the control gate is V _P0 + DELTA V _PP + V _E0 + DELTA V _EE , and the change amount of the erase voltage difference is DELTA V _PP + DELTA V _EE .

As described above, when the erase voltage changes, the erase time of the flash memory cell also changes. In other words, when the erase voltage is applied low, a large amount of time is required to erase the cell or the erase is not completely performed. On the contrary, when the erase voltage is applied high, since the erase operation of the cell is completed in a short time, the over erase of the cell may occur.

As a result, when the erase voltage is applied high or low and the cell is abnormally erased, the uniformity of the threshold voltage distribution decreases, thereby causing an error in the program operation or the read operation and the reliability of the circuit operation.

Accordingly, in order to solve the above problem, the present invention measures the erase voltage through the pin in the test mode, and then adjusts the amplification ratio of the amplifying means for generating the erase voltage to be applied to the control gate and the semiconductor substrate of the flash memory cell. And maintaining the potential difference between the positive erase voltages to provide an erase voltage control circuit of a flash memory cell in which a normal erase operation can be performed regardless of a change in power supply voltage or a change in characteristics of a circuit component by a manufacturing process. There is this.

1 is a cross-sectional view of a typical flash memory cell.

2 is a conventional erase voltage generation circuit.

3 is an erase voltage adjusting circuit of a flash memory cell according to the present invention;

<Explanation of symbols for the main parts of the drawings>

11 semiconductor substrate 12 floating gate

13: control gate 14a: source

14b: drain 15: charge

110, 210: reference voltage generating means 120, 220: positive pumping means

130, 230: negative pumping means 140, 240: first amplifying means

150, 250: second amplifying means 160, 241: first feedback circuit

170, 251: second feedback circuit 242: variable resistance means

260 voltage distribution means 270 third amplification means

280: variable resistance control means

An erase voltage control circuit of a flash memory cell according to the present invention includes first amplification means for amplifying a reference voltage to generate a first erase voltage of positive potential, and a second amplification for amplifying the reference voltage to generate a second erase voltage of negative potential. Means, a variable resistance means connected in series between the output terminal of the first amplifying means and the ground unit price, and a first resistor, and generating a first feedback voltage in accordance with the resistance ratio of the variable resistance means and the first resistor to generate the first amplification. A first amplification control means for controlling the amplification factor of the means, a second and third resistors connected in series between the output terminal of the second amplifying means and the ground unit cost, and according to the resistance ratio of the second and third resistors. A second amplification control means for generating a second feedback voltage to control the amplification rate of the second amplifying means, and a plurality of voltage drop means connected in series between the output terminals of the first and second amplifying means. A voltage divider for generating a predetermined divided voltage, a third amplifying means for amplifying the divided voltage, and storing data for adjusting a resistance value of the variable resistor means in accordance with an output voltage of the third amplifying means, And variable resistance control means for controlling the resistance value of the means.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

3 is a block diagram illustrating the operation of the erase voltage adjusting circuit of the flash memory cell according to the present invention.

The erase voltage control circuit of the flash memory cell includes a reference voltage generator 210 for generating a reference voltage Vref, a positive high voltage generator 220 for generating a positive high voltage, and a negative high voltage generator 230 for generating a negative high voltage. In addition, the first amplification means 240 and the negative high voltage are supplied to the driving voltage and amplify the reference voltage Vref applied to the first input terminal to generate a first erase voltage V _PP of positive potential. Outputs of the second amplifying means 250 and the first amplifying means 240 which amplify the reference voltage Vref supplied to the driving voltage and applied to the first input terminal to generate a second erase voltage V _EE of negative potential. A first amplification control means connected to the terminal and generating a first feedback voltage Vf1 for adjusting the amplification rate of the first amplifying means 240 and applying it to the second input terminal of the first amplifying means 240 ( 241 ) Is connected to an output terminal of the second amplifying means 250 and generates a second feedback voltage Vf2 for adjusting the amplification rate of the second amplifying means 250, thereby generating a second of the second amplifying means 250. Voltage distribution means 260, which is connected between the second amplification control means 251 applied to the input terminal, the output terminals of the first and second amplification means 240 and 250, and generates a predetermined distribution voltage Vd, Variable resistance control means 280 for adjusting the voltage drop degree of the first amplification control means 241 according to the third amplifying means 270 for amplifying the voltage Vd and the output potential of the third amplifying means 270. It consists of.

In the above, the first amplification control means 241 is composed of a variable resistance means 242 and a first resistor R21 connected in series between the output terminal and the ground terminal of the first amplification means 240, and the variable resistance means. The voltage dropped by 242 is applied to the second input terminal of the first amplifying means 240 as the first feedback voltage Vf1.

The variable resistance means 242 is connected in parallel with the plurality of resistors R22 to R25 and the plurality of resistors R22 to R25 connected in series between the output terminal of the first amplifying means 240 and the first resistor R21. And a plurality of transfer gates T21 to T23 operated according to the output signal of the variable resistance control means 280.

The second amplification control means 251 is composed of a sixth resistor R26 and a seventh resistor R27 connected in series between the output terminal and the ground terminal of the second amplifying means 250, and the seventh resistor R27. The voltage dropped by is applied to the second input terminal of the second amplifying means 250 as the second feedback voltage Vf2.

The erase voltage adjusting circuit of the flash memory cell having the above configuration measures the first and second erase voltages V _PP and V _EE generated by the first and second amplifying means 240 and 250, and then adds the result to the result value. Corresponding data is stored in the variable resistance control means 280. The variable resistance control means 280 is composed of a plurality of latch circuits or flash memory cells to store data, and is connected to an output terminal of the first amplifying means 240 according to the stored data. The resistance value of the variable resistance means 242 is adjusted. The first feedback voltage Vf1 applied to the second input terminal of the first amplifying means 240 is adjusted according to the resistance ratio of the variable resistance means 242 and the first resistor R21, thereby adjusting the first amplifying means. The amplification factor of 240 is adjusted. Controlling the amplification rate of the first amplifying means 240 means that the generation potential of the first erase voltage V _PP is controlled.

When the first erase voltage V _PP is generated low due to a change in power supply voltage or a change in process resistance, the voltage difference with the second erase voltage V _EE decreases and thus the erase operation is not completely performed. On the contrary, when the first erase voltage V _PP is generated to be high, the voltage difference with the second erase voltage V _EE is increased to over erase.

Therefore, the erase voltage adjusting circuit of the flash memory cell according to the present invention measures the first erase voltage V _PP through the voltage divider 260 and the third amplifying means 270, and then measures the first erase voltage V _PP. ) Is generated low and the difference between the first and second erase voltages is lowered, the first erase voltage (V) is increased by adjusting the resistance value of the variable resistor means 242 to increase the amplification ratio of the first amplification means 240. _PP ) is raised to allow the first and second erase voltages V _PP and V _EE to maintain a constant voltage difference. On the contrary, when the first erase voltage V _PP is generated to be high and the difference between the first and second erase voltages is increased, the amplification ratio of the first amplifying means 240 is adjusted by adjusting the resistance value of the variable resistance means 242. By reducing the first erase voltage V _PP , the first and second erase voltages V _PP and V _EE can maintain a constant voltage difference.

The configuration and operation of the erase voltage adjusting circuit of the flash memory cell according to the present invention will be described in more detail as follows.

The reference voltage generator 210 generates a reference voltage Vref, the positive pumping means 220 pumps a power supply voltage to generate a positive high voltage, and the negative pumping means 230 generates a negative high voltage. The first amplification means 240 is applied with a positive high voltage as a driving voltage, and amplifies the reference voltage Vref applied to the first input terminal to generate a first erase voltage V _PP . The second amplifying means 250 applies a negative high voltage as a driving voltage, and amplifies the reference voltage Vref applied to the first input terminal to generate a second erase voltage V _EE .

The first and second amplifying means 240 and 250 are constituted by an operational amplifier (OP-AMP). Typically, amplification control means for generating a feedback voltage is connected to the output terminal of the operational amplifier. In general, the amplification control means is composed of resistors connected in series and drops the output voltage to generate a feedback voltage. This circuit is called a feedback circuit. The feedback voltage is adjusted according to the resistance ratio of these resistors, the feedback voltage is applied back to the operational amplifier, and eventually the amplification ratio of the operational amplifier is determined according to the resistance ratio.

Initially, the resistance ratios of the resistors constituting the first and second amplification control means 241 and 251 are appropriately set to generate predetermined first and second erase voltages V _PP and V _EE .

The voltage distribution means 260 is connected between the output terminals of the first and second amplification means 240 and 250. The voltage dividing means 260 is composed of a plurality of diodes D ₂₁ to D _2n , which are voltage drop means, connected in series between the output terminals of the first and second amplifying means 240 and 250. The number of diodes can be adjusted appropriately. For example, if 10 diodes are connected in series with the first erase voltage V _PP and +8 V and the second erase voltage V _EE is -8 V, each diode is connected with 16 V according to the voltage division law. A voltage of 1.6 V is applied, corresponding to one tenth of. The output terminal of the voltage distribution means 260 is set to any one of a diode and a node to which the diode is connected. For example, as shown in the drawing, when the node N21 to which the second diode D ₂₂ and the third diode D ₂₃ are connected is determined as an output terminal, the voltage divider means 260 performs a first erase voltage. At + 8V, which is (V _PP ), a voltage of 4.8V is generated as the distribution voltage (Vd) by dropping the voltage of 3.2V by two diodes (D ₂₁ and D ₂₂ ). The third amplifying means 270 amplifies the distribution voltage Vd to a predetermined voltage suitable for measuring to generate the output voltage Vo. The output voltage Vo generated as described above is measured to determine whether the potential difference between the first and second erase voltages V _PP and V _EE matches the target value.

If the first and second erase voltages V _PP and V _EE are generated higher than the target voltage at +9 V and -9 V, respectively, each diode has a first and second erase voltages V _PP and V _EE . A voltage of 1.8V, corresponding to one-tenth of a voltage difference of 18V, is applied. Accordingly, the voltage dividing means 260 divides the voltage of 5.4V, the voltage of 3.6V being dropped by the two diodes D ₂₁ and D ₂₂ at + 9V, which is the first erase voltage V _PP . To occur. The third amplifying means 270 amplifies the divided voltage Vd to a predetermined voltage suitable for measuring to generate the output voltage Vo, and measures the divided voltage Vd to determine the first and second erase voltages V _PP and V _EE . It is determined that the potential difference does not match the target value.

As described above, as the potential difference between the first and second erase voltages V _PP and V _EE increases, the output voltage Vo is generated as a voltage higher than a target value, and the first and second erase voltages V _PP and The smaller the potential difference of V _EE ), the output voltage Vo is generated at a voltage lower than the target value. In addition, the larger the number of diodes constituting the voltage distribution means 260, the more accurate the measurement can be.

In the above description, the measured output voltage Vo is higher than the target value because the potential difference between the first and second erase voltages V _PP and V _EE , that is, the voltage applied to the control gate of the flash memory cell C21 and the semiconductor substrate. This means that the potential difference of is high, which causes transient erasure. Therefore, the amplification ratio of the first amplifying means 240 is reduced by adjusting the resistance value of the variable resistance means 242 of the first amplifying control means 241 connected to the output terminal of the first amplifying means 240. When the amplification ratio of the first amplifying means 240 is reduced, the first erase voltage V _PP is generated at a potential lower than the target voltage, thereby reducing the potential difference between the first and second erase voltages V _PP and V _EE . Can match the value.

Hereinafter, an operation of adjusting the potential difference between the first and second erase voltages V _PP and V _EE by adjusting the amplification rate of the first amplifying means 240 will be described in detail.

In the present invention, the amplification ratio of the first amplifying means 240 is adjusted by using the variable resistance control means 280 and the first variable resistance means 242 of the amplification control means 241.

The variable resistance means 242 is connected in parallel with the plurality of resistors R22 to R25 and the plurality of resistors R22 to R25 connected in series between the output terminal of the first amplifying means 240 and the first resistor R21. And a plurality of transfer gates T21 to T23 operated according to the output signal of the variable resistance control means 280. Each of the transfer gates T21 to T23 is operated according to an output signal of data stored in the variable resistance control means 280, and the operated transfer gate connects both terminals of the corresponding resistors in parallel to adjust the resistance value to zero. do.

For example, when the resistance values of the second to fifth resistors R22 to R25 are 10 kΩ, respectively, the overall resistance of the variable resistance means 242 is 40 kΩ. At this time, when the first transfer gate T21 is operated, the resistance value is adjusted to 0 by connecting both terminals of the second resistor R22, so that the resistance value of the variable resistance means 242 is adjusted to 30 kW. When all of the first to third transfer gates T21 to T23 are operated, the resistance value of the variable resistance means 242 is 10 kΩ.

Since the amplification ratio of the first amplifying means 240 is determined according to the resistance ratio of the first resistor R21 and the variable resistance means 242, the potential of the first erase voltage VPP is adjusted according to the resistance ratio. The first erase voltage V _PP is generated according to the relational expression of Equation 3 below.

Referring to Equation 3, since the first resistor 21 is a device having a fixed resistance value, the potential of the first erase voltage V _PP is determined according to the resistance value of the variable resistance means 242.

In this case, the amplification ratio of the second amplifying means 250 is determined according to the resistance ratios of the sixth and seventh resistors R26 and R27 constituting the second amplifying control means 251. Since R26 and R27 are elements having a fixed resistance value, the amplification ratio of the second amplifying means 250 is constant. The second erase voltage V _EE generated by the second amplifying means 250 is generated according to the relational expression of Equation 4 below.

As described above, the semiconductor of the first erase voltage first erase voltage by controlling the (V _PP) (V _PP) and the second erasing voltage (V _EE) When the potential difference is adjusted to a target value, each of the flash memory cell (C21) of The normal erase operation is applied to the substrate and the control gate.

In the above description, as the number of resistors constituting the variable resistance means 242 increases, the overall resistance value of the variable resistance means 242 can be finely adjusted, thereby finely adjusting the amplification rate of the first amplifying means 240. The first erase voltage V _PP of the target voltage may be adjusted. As the number of resistors increases, the number of transfer gates increases accordingly, and the number of latch circuits or flash memory cells that are components of the variable resistance control means 280 must also increase.

In addition, the second amplification control means 242 is also configured to include the variable resistance means in the same manner as the first amplification control means 241, and then the first and second amplification means 240 and 250 through the variable resistance control means 280. You can also control the amplification factor of) simultaneously. When the second variable resistance means (not shown) is included in the second amplification control means 251 of the second amplifying means 250, the second erase voltage V _EE is generated according to the equation (5).

When as described above, the second erasing voltage (V _EE) is a first erase voltage (V _PP) and at the same time adjusted to the target voltage with a potential difference of the first erase voltage (V _PP) and the second erasing voltage (V _EE) Fig. Adjusted. At this time, even if the second variable resistance means is included in the second amplification control means 251, it is not necessary to increase the number of latch circuits or memory cells constituting the variable resistance control means 280. Since the second variable resistance means has the same configuration as the first variable resistance means 242, the output signal of the variable resistance control means 280 applied to the first variable resistance means 242 is also the same for the second variable resistance means. It only needs to be authorized. However, since the amplification ratios of the first and second amplifying means 240 and 250 are simultaneously controlled by the first and second variable resistance means, the amplification rate may be adjusted by adjusting the resistance value or the number of resistors constituting the variable resistance means. Fine control is possible.

As described above, the present invention controls the amplification ratio of the amplifying means by adjusting the resistance ratio of the feedback circuit which is an amplifying control means connected to the output terminal of the amplifying means for generating the erase voltage, thereby controlling the control gate and the semiconductor substrate of the flash memory cell. By maintaining the potential difference between the negative and positive erase voltage applied to the circuit, the normal erase operation can be performed irrespective of the change of the power supply voltage or the characteristic change of the circuit components by the manufacturing process, thereby improving the reliability and electrical characteristics of the circuit operation. It works.

Claims (22)

First amplifying means for amplifying the reference voltage to generate a first erase voltage of positive potential, Second amplifying means for amplifying the reference voltage to generate a second erase voltage of negative potential; The first resistor comprises a variable resistor means and a first resistor connected in series between the output terminal of the first amplifying means and the ground unit price, and generates a first feedback voltage according to a resistance ratio between the variable resistor means and the first resistor. First amplifying control means for controlling an amplification rate of the amplifying means, The second amplifying means comprises a second and third resistor connected in series between the output terminal of the second amplifying means and the ground unit price, and generates a second feedback voltage in accordance with the resistance ratio of the second and third resistors. Second amplification control means for controlling the amplification rate of the A voltage distribution means composed of a plurality of voltage drop means connected in series between the output terminals of the first and second amplification means, for generating a predetermined divided voltage; Third amplifying means for amplifying the divided voltage; And a variable resistance control means for storing data for adjusting the resistance value of the variable resistance means according to the output voltage of the third amplification means, and for controlling the resistance value of the variable resistance means. Eliminating voltage regulation circuit. The method of claim 1, And the first amplifying means comprises an operational amplifier, and the reference voltage is applied to a first input terminal and the first feedback voltage is applied to a second input terminal. The method of claim 1, And the second amplifying means comprises an operational amplifier, and the reference voltage is applied to a first input terminal and the second feedback voltage is applied to a second input terminal. The method of claim 1, The variable resistance means includes a plurality of resistors connected in series between the output terminal of the first amplifying means and the first resistor and a plurality of resistors connected in parallel to the plurality of resistors and operated according to the output signal of the variable resistance control means. An erase voltage adjusting circuit of a flash memory cell, characterized in that it is composed of a transfer gate. The method of claim 4, wherein The transfer gate is operated according to an output signal of data stored in the variable resistance control means, and the transfer gate operated is connected to both terminals of a resistor corresponding to a parallel connection to adjust a resistance value. Voltage regulation circuit. The method of claim 1, And said voltage drop means is a diode. The method of claim 1, And said variable resistance means comprises a plurality of latch circuits corresponding to the number of said transfer gates, and operates said transfer gate in accordance with data stored in said latch circuit. The method of claim 1, The variable resistance control means comprises a plurality of flash memory cells corresponding to the number of transfer gates of the variable resistance means, and erases the flash memory cell according to claim 1, wherein the transfer gate is operated according to data stored in the flash memory cell. Voltage regulation circuit. The method according to claim 7 or 8, And said data is data for determining the operation of said transfer gate to adjust the resistance value of said variable resistance means in accordance with the output signal of said third amplifying means. The method of claim 1, And the first erase voltage is calculated by Equation 6 below. First amplifying means for amplifying the reference voltage to generate a first erase voltage of positive potential, Second amplifying means for amplifying the reference voltage to generate a second erase voltage of negative potential; And a first variable resistance means and a first resistor connected in series between the output terminal of the first amplification means and the ground unit price, and generate a first feedback voltage according to the resistance ratio of the first variable resistance means and the first resistor. First amplification control means for controlling the amplification rate of the first amplification means, And a second variable resistance means and a second resistor connected in series between the output terminal of the second amplifying means and the ground unit price, and generating a second feedback voltage according to the resistance ratio of the second variable resistance means and the second resistor. Second amplification control means for controlling the amplification rate of the second amplification means, A voltage distribution means composed of a plurality of voltage drop means connected in series between the output terminals of the first and second amplification means, for generating a predetermined divided voltage; Third amplifying means for amplifying the divided voltage; And variable resistance control means for storing data for adjusting the resistance value of the variable resistance means according to the output voltage of the third amplification means, and controlling the resistance values of the first and second variable resistance means. An erase voltage adjusting circuit of a flash memory cell. The method of claim 11, And the first amplifying means comprises an operational amplifier, and the reference voltage is applied to a first input terminal and the first feedback voltage is applied to a second input terminal. The method of claim 11, And the second amplifying means comprises an operational amplifier, and the reference voltage is applied to a first input terminal and the second feedback voltage is applied to a second input terminal. The method of claim 11, The first variable resistance means is connected in parallel with the plurality of resistors connected in series between the output terminal of the first amplifying means and the first resistor and the plurality of resistors are operated in accordance with the output signal of the variable resistance control means. An erase voltage regulating circuit of a flash memory cell, comprising a plurality of transfer gates. The method of claim 11, The second variable resistance means is connected in parallel with the plurality of resistors connected in series between the output terminal of the second amplifying means and the second resistor and the plurality of resistors are operated in accordance with the output signal of the variable resistance control means. An erase voltage regulating circuit of a flash memory cell, comprising a plurality of transfer gates. The method according to any one of claims 14 and 15, The plurality of transfer gates of the first and second variable resistance means operate in the same manner according to the output signal of the data stored in the variable resistance control means, and the operated transfer gates connect both terminals of the corresponding resistors in parallel connection. An erase voltage control circuit of a flash memory cell, characterized in that the resistance value is adjusted. The method of claim 11, And said voltage drop means is a diode. The method of claim 11, The variable resistance control means includes a plurality of latch circuits corresponding to the number of transfer gates of the first or second variable resistance means, and operates the transfer gate according to data stored in the latch circuit. The erase voltage regulation circuit of the memory cell. The method of claim 11, The variable resistance means comprises a plurality of flash memory cells corresponding to the number of transfer gates of the first or second variable resistance means, and operates the transfer gate according to data stored in the flash memory cell. The erase voltage regulation circuit of the memory cell. The method of claim 18 or 19, And the data is data for determining an operation of the transfer gate to adjust resistance values of the first and second variable resistance means according to the output signal of the third amplifying means. Voltage regulation circuit. The method of claim 11, And the first erase voltage is calculated by Equation 7 below. The method of claim 11, And the second erase voltage is calculated by Equation 8 below.