KR100417006B1 - Multi-output DC-DC converter - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC-DC converter capable of multi-level voltage output, wherein a predetermined voltage is supplied through an inductor in which a plurality of output taps are formed at predetermined intervals, and is provided by switching means operated according to a plurality of control signals. A multi-output DC-DC converter configured to selectively output voltages having different levels from an output tap is provided.

Description

Multi-output DC-DC converters

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching mode DC-DC converter, and more particularly, to a multi-output direct current capable of selectively outputting multilevel voltages by stepping up or down the input DC voltage. It relates to a direct current converter.

Recently, in the application industry, there is a need to convert a predetermined direct current (“DC”) voltage source into a variable DC voltage source, which is applied to a DC chopper for directly converting a DC voltage source to a DC voltage source. Research is actively being conducted.

DC choppers are commonly referred to as DC-DC converters (hereinafter referred to as "DC-DC converters"), which are equivalent to alternating current ("AC") transformers that can continuously change the turn ratio. Can be thought of as a DC voltage source. Choppers are widely used to step up or step down DC voltage sources. In particular, it is widely used for electric motor control of electric cars, trolley cars, marine hoists, forklift trucks, and mine towing tanks. In addition, the chopper has characteristics of smooth acceleration control, high efficiency, and fast dynamic response, which is used for regenerative braking of a DC motor to return energy to a power source. It is bringing effect.

The DC chopper is used as a switching mode regulator for converting an unregulated DC voltage into a regulated DC output voltage. The output voltage adjustment is performed by a pulse width modulation having a fixed frequency. Typically, a power BJT or MOSFET is used. The basic circuit type of the switching mode DC-DC converter is divided into a boost type DC-DC converter for boosting an input DC voltage source and a buck type DC-DC converter for stepping down an input DC voltage source.

The boost type DC-DC converter can boost the output voltage without a transformer, and as shown in FIG. 1, an inductor L1, a switching element S1, a rectifier D1, a capacitor C1, and a load resistor (not shown). Not configured).

The inductor L1 is connected between the input terminal and the node N1 to accumulate energy or transfer energy to the output terminal according to the switching element S1. The switching element S1 is connected between the node N1 and the ground Vss, and controls the flow of the inductor current I _L1 . The rectifier D1 is connected between the node N1 and the output terminal to control the transfer of the inductor current I _L1 to the output terminal according to the switching element S1. The capacitor C1 is connected in parallel with the output terminal and operates as a load together with the load resistor.

Driving characteristics of the boost-type DC-DC converter configured as described above will be described with reference to FIGS. 2A, 2B, and 3.

2A and 2B, the boost-type DC-DC converter is operated in the first mode MODE 1 and the second mode MODE 2 according to the state of the switching device S1. As shown in FIG. 3, the first mode MODE 1 is a mode that starts when the switching element S1 is turned on at 't = 0', and the input current increases. It flows through the inductor L1 and the switching element S1 from the input terminal. The second mode MODE 2 is a mode that is started when the switching device S1 is turned off at 't = kT', and the switching device S1 is turned on in the first mode MODE 1. The input current flowing through the inductor L1, the rectifier D1 and the capacitor C1 flows.

Since the inductor current I _L1 cannot change instantaneously due to its characteristics, the voltage between both ends of the inductor L1 becomes positive when the input current increases, and negative when the input current decreases. It becomes a state. That is, in the first mode MODE 1, the current of the inductor L1 increases from 'I ₁ ' to 'I ₂ ' due to the input voltage Vin, and energy is accumulated in the inductor L1. Accordingly, the inductor L1 maintains a positive voltage at both ends thereof based on the input terminal.

Meanwhile, the energy accumulated in the inductor L1 in the second mode MODE 2 is transferred to the output terminal through the rectifier D1, and the inductor current I _L1 starts to decrease from 'I ₂ ' to 'I ₁ '. do. For this reason, when the voltage between both ends of the inductor L1 is maintained in the negative (−) state and the output terminal Vout is a reference value, the combined voltage of the input voltage Vin and the voltage between both ends of the inductor L1 is reduced. Therefore, the input voltage Vin is increased by the voltage between both ends of the inductor L1. Therefore, it can be expressed as 'average output voltage Va = input voltage Vin / (1-k)'. Where k is the application rate.

In addition, the inductor current I _L1 , which is a factor for determining the output voltage Vout, is controlled by the switching element S1, and the switching element S1 controls the flow of the inductor current I _L1 . . For example, when the output voltage Vout is higher than the predetermined level, the switching element S1 is turned off to reduce the inductor current I _L1 , and when the output voltage Vout is higher than the predetermined level, the switching element S1 is turned on and the inductor current is turned on. Increase (I _L1 ). Accordingly, the voltage between both ends of the inductor L1 increases or decreases according to the switching time of the switching element S1, thereby reducing the ON / OFF time of the switching element S1 and the inductance value of the inductor L1. By adjusting it, you can boost the input voltage (Vin) as easily as you want.

In the buck type DC-DC converter, the output voltage is lower than the input voltage, and as shown in FIG. 4, the switching element S11, the rectifier D11, the inductor L11, the capacitor C11, and the load resistor (shown in FIG. 4). Not used).

The switching means S11 is connected between the input terminal and the node N11 to control the flow of current input from the input terminal to the node N11. The rectifier D11 is connected between the node N11 and the ground Vss to prevent the input current from flowing to the ground when the switch means S11 is turned on. The inductor L11 is connected between the node N11 and the output terminal to accumulate energy or transfer energy to the output terminal according to the switching element S11. The capacitor C11 is connected in parallel with the output terminal and operates as a load with the load resistor.

Driving characteristics of the buck-type DC-DC converter configured as described above will be described with reference to FIGS. 5A, 5B, and 6.

5A and 5B, the buck-type DC-DC converter is operated in the first mode MODE 1 and the second mode MODE 2 according to the state of the switching device S11. As shown in FIG. 6, the first mode MODE 1 is a mode that starts when the switching element S11 is turned on at 't = 0', wherein the input current is increased and the inductor L11 from the input terminal is increased. ), The capacitor C11 and the load resistance. The second mode MODE 2 is a mode started when the switching element S11 is turned off at 't = kT', and a closed circuit is formed through the rectifier D11, the inductor L11, and the capacitor C11. .

In the first mode MODE 1, the rectifier D11 is cut off and the input voltage Vin is applied to the inductor _L11 , thereby increasing the inductor current I _L11 from 'I ₁ ' to 'I ₂ '. As a result, energy is accumulated in the inductor L11 and the energy is transferred to the output terminal, thereby increasing the output voltage Vout. In the second mode MODE 2, the rectifier D11 is conducted by the energy accumulated in the inductor L11, and the inductor current I _L11 connects the inductor L11, the capacitor C11, and the rectifier D11. It continues to flow through. At this time, the inductor current I _L11 is continuously reduced until the switching element S11 is turned on in the next period, thereby reducing the output voltage Vout. Therefore, the average output voltage Va may be expressed as the product of the ratio k and the input voltage Vin.

FIG. 7 is a block diagram of a general multi-output boost type DC-DC converter using the boost type DC-DC converter shown in FIG. 1, and includes a main control unit 10, a switching unit 20, and an inductor unit. It consists of 30.

The main controller 10 generates a plurality of control signals for controlling the switching unit 20. The switching unit 20 is composed of a synchronous rectified switch and a boost switch, and predetermined among boosting voltages output from the inductor unit 30 according to a control signal of the main controller 10. Select the boosting voltage and deliver it to the output. The inductor unit 30 includes a plurality of inductors L1 to LN having different inductances to boost the input voltage Vin to a predetermined potential.

The general multi-output boost type DC-DC converter configured as described above can be seen as a form of a plurality of boosting DC-DC converters shown in FIG. 1, and the driving characteristics thereof are similar to those of a single boost DC-DC converter. similar. That is, in the conventional multi-output boost type DC-DC converter, a plurality of inductors having different inductances are connected in parallel to the input terminal in order to receive one input voltage Vin and output the multi-level multi-voltage Vout. A plurality of switches are connected to each other to transfer the multi-level boosting voltages output through the plurality of inductors to an output terminal, and a main controller for generating a plurality of control signals to control the switches.

However, in the conventional multi-output boost type DC-DC converter, a plurality of inductors having different inductances must be configured to receive one input voltage and output a multi-level voltage, and a plurality of boosting voltages output from the plurality of inductors. Multiple switches are needed to deliver the output to the output stage. Therefore, the number of inductors required by the number of output voltages increases not only unnecessary power consumption but also increases the size of the multi-output boost type DC-DC converter. In addition, one large size switching unit has many disadvantages in terms of re-use and flexibility.

Accordingly, the present invention has been made to solve the above problems, and provides a multi-output DC-DC converter capable of multi-level voltage output by using one built-in inductor having a plurality of output taps. Its purpose is to.

1 is a detailed circuit diagram of a general boost type DC-DC converter.

2A and 2B are circuit diagrams for explaining the operation of the boost-type DC-DC converter shown in FIG.

3 is a waveform diagram for explaining the operation of the boost-type DC-DC converter shown in FIG.

4 is a detailed circuit diagram of a typical buck DC-DC converter.

5A and 5B are circuit diagrams for explaining the operation of the buck DC-DC converter shown in FIG.

FIG. 6 is a waveform diagram for describing an operation of a buck DC-DC converter shown in FIG. 4. FIG.

7 is a block diagram of a conventional boosted multi-output DC-DC converter.

8 is a block diagram of a boost type multi-output DC-DC converter according to a first embodiment of the present invention.

9 is a detailed circuit diagram of the boosted multi-output DC-DC converter shown in FIG.

10 is a block diagram of a buck type multi-output DC-DC converter according to a second embodiment of the present invention.

FIG. 11 is a detailed circuit diagram of the buck multi-output DC-DC converter shown in FIG. 10.

12 is a waveform diagram for explaining the operation of the multi-output DC-DC converter shown in FIGS. 9 and 11;

<Explanation of symbols for the main parts of the drawings>

10, 100, 400: main control unit 20, 200, 500: switching unit

30, 300, 600: inductor 210, 510: synchronous rectification switching unit

220, 520: boost switching unit 230, 530: inductor control switching unit

The present invention provides a plurality of output tabs are formed at predetermined intervals, the inductor unit to which the input voltage is supplied; And a switching unit configured to selectively connect the respective output taps to output terminals according to a plurality of control signals to output voltages of different levels through the output terminals.

In addition, the present invention includes a plurality of output tabs are formed at predetermined intervals inductor unit connected to the output terminal; And a switching unit for selectively connecting the respective output taps to input terminals according to a plurality of control signals to output voltages of different levels through the output terminals.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

8 is a block diagram of a boost type multi-output DC-DC converter according to a first embodiment of the present invention. FIG. 9 is a detailed circuit diagram of the boost type multi-output DC-DC converter shown in FIG. 8 and shows a four-step boost type DC-DC converter.

8 and 9, the boost type multi-output DC-DC converter includes a main controller 100, a switching unit 200, and an inductor unit 300. The main controller 100 generates control signals for controlling the switching unit 200. The switching unit 200 is composed of a synchronous rectification switching unit 210, the boost switching unit 220 and the inductor control switching unit 230 is controlled by a control signal output from the main control unit 100. The inductor 300 includes one inductor having first to fourth output taps Lt1 to Lt4, and boosts an input voltage Vin according to the inductor control switching unit 230 to an output terminal. Output

The main controller 100 controls the synchronous rectification control signal SRSC for controlling the synchronous rectification switching unit 210 and the first to fourth boosting control signals for controlling the boost switching unit 220. (MBSC1 to MBSC4) and the first inductor control signal to the fourth inductor control signal (ICSC1 to ICSC4) for controlling the inductor control switching unit 230 is generated.

The switching unit 200 includes a synchronous rectification switching unit 210, a boost switching unit 220 and an inductor control switching unit 230.

The synchronous rectification switching unit 210 includes a first PMOS transistor P1, which is connected between an output terminal and a node B to be driven according to the synchronous rectification control signal SRSC. do.

The boost switching unit 220 is connected between the node B and the ground Vss and driven according to the first boosting control signal MBSC1, and the node B and the ground ( A second NMOS transistor N2 connected between Vss and driven according to a second boosting control signal MBSC2, and connected between the node B and ground Vss to a third boosting control signal MBSC3. The third NMOS transistor N3 is driven along with the fourth NMOS transistor N4 connected between the node B and the ground Vss and driven according to the fourth boosting control signal MBSC4. That is, the first to fourth NMOS transistors N1 to N4 are connected in parallel with each other between the node B and the ground Vss.

The inductor control switching unit 230 is connected between the node B and the first output tap Lt1 to be driven according to the first inductor control signal ISC1 and the fifth NMOS transistor N5 and the node ( A sixth NMOS transistor N6 connected between B) and a second output tap Lt2 and driven according to the second inductor control signal ISC2 and between the node B and the third output tap Lt3. A seventh NMOS transistor N7 connected to the third inductor control signal ISC3 and driven between the node B and a fourth output tap Lt4 and connected to the fourth inductor control signal ISC4. The eighth NMOS transistor (N8) is driven according to.

An operation characteristic of the boost type multi-output DC-DC converter configured as described above will be described with reference to FIG. 12.

Referring to FIG. 12, during the period 'T0' to 'T1', the synchronous rectification control signal SRSC and the first boosting control signal MBSC1 in the HIGH state from the main controller 100 are respectively the first PMOS. As the transistor P1 and the first NMOS transistor N1 are inputted, the first PMOS transistor P1 is turned off and the first NMOS transistor N1 is turned on. )do.

In this state, the fifth NMOS transistor N5 is turned on by inputting the first inductor control signal ISCC1 of the high state to the fifth NMOS transistor N5 from the main controller 100. . As a result, the first closed circuit via the first output tap Lt1, the fifth NMOS transistor N5, and the first NMOS transistor N1 is formed so that the input voltage inputted to the input terminal of the first output tap Lt1 ( The first energy W1 is accumulated by Vin).

Thereafter, the second boosting control signal MBSC2 and the second inductor control signal ISCC of the high state are input to the second NMOS transistor N2 and the sixth NMOS transistor N6, respectively, from the main controller 100. As the first inductor control signal ICSC1 transitions from high to low, the second and sixth NMOS transistors N2 and N6 are turned on while the fifth NMOS transistor N5 is turned off. As a result, the first closed circuit is not interrupted, but passes through the second output tap Lt2, the sixth NMOS transistor N6, and the first NMOS transistor N1, and at the same time, the second output tap Lt2 and the sixth NMOS. Since the second closed circuit via the transistor N6 and the second NMOS transistor N2 is formed, the second energy W2 is accumulated in the second output tap Lt2 by the input voltage Vin input to the input terminal.

Thereafter, the third boosting control signal MBSC3 and the third inductor control signal ISCC of the high state are input to the third NMOS transistor N3 and the seventh NMOS transistor N7, respectively, from the main controller 100. As the second inductor control signal ISC2 transitions from high to low, the third and seventh NMOS transistors N3 and N7 are turned on while the sixth NMOS transistor N6 is turned off. As a result, the second closed circuit is not blocked, but instead of the third output tap Lt3, the seventh NMOS transistor N7, and the first NMOS transistor N1, the third output tap Lt3 and the seventh NMOS transistor. The third output is formed through the N7 and the second NMOS transistor N2, and the third closed circuit is formed through the third output tap Lt3, the seventh NMOS transistor N7, and the third NMOS transistor N3. The third energy W3 is accumulated in the tap Lt3 by the input voltage Vin input to the input terminal.

Thereafter, the fourth boosting control signal MBSC4 and the fourth inductor control signal ISCC of the high state are input to the fourth NMOS transistor N4 and the eighth NMOS transistor N8, respectively, from the main controller 100. As the third inductor control signal ISC3 transitions from high to low, the fourth and eighth NMOS transistors N4 and N8 are turned on while the seventh NMOS transistor N7 is turned off. . As a result, the third closed circuit is not blocked, but instead of the fourth output tap Lt4, the eighth NMOS transistor N8, and the first NMOS transistor N1, the fourth output tap Lt4 and the eighth NMOS transistor. The fourth output tap Lt4, via the N8 and the second NMOS transistor N2, and via the fourth output tap Lt4, the eighth NMOS transistor N8, and the third NMOS transistor N3. As the fourth closed circuit via the eighth NMOS transistor N8 and the fourth NMOS transistor N4 is formed, the fourth energy W4 is applied to the fourth output tab Lt4 by the input voltage Vin input to the input terminal. Accumulate.

During the period 'T1' to 'T2', as the synchronous rectification control signal SRSC and the first to fourth boosting control signals MBSC1 to MBSC4 transition from a high state to a low state, the first PMOS transistor P1 It is turned on and the first and fourth NMOS transistors N1 to N4 are turned off.

In this state, the fifth NMOS transistor N5 is turned on as the first inductor control signal ISC1 transitions from low to high. As a result, a first closed circuit via the first output tap Lt1, the fifth NMOS transistor N5, and the first PMOS transistor P1 is formed, thereby storing the first energy accumulated in the first output tap Lt1 ( W1 is output to the output terminal via the fifth NMOS transistor N5 and the first PMOS transistor P1.

Thereafter, the fifth NMOS transistor N5 is turned off because the first inductor control signal ISC1 transitions from a high state to a low state, and the second inductor control signal ISC2 transitions from a low state to a high state. NMOS transistor N6 is turned on. As a result, the fifth closed circuit is not interrupted, but a sixth closed circuit via the second output tap Lt2, the sixth NMOS transistor N6, and the first PMOS transistor P1 is formed, thereby forming the second output tap Lt2. The second energy W2 accumulated in the is output to the output terminal via the sixth NMOS transistor N6 and the first PMOS transistor P1.

Thereafter, the sixth NMOS transistor N6 is turned off because the second inductor control signal ISC2 transitions from a high state to a low state and the third inductor control signal ISC3 transitions from a low state to a high state. NMOS transistor N7 is turned on. As a result, the sixth closed circuit is not interrupted, but instead, the seventh closed circuit is formed through the third output tap Lt3, the seventh NMOS transistor N7, and the first PMOS transistor P1, thereby forming the third output tap Lt3. The third energy W3 accumulated in the output is output to the output terminal via the seventh NMOS transistor N7 and the first PMOS transistor P1.

Thereafter, the seventh NMOS transistor N7 is turned off by the third inductor control signal ISC3 transitioning from the high state to the low state and the fourth inductor control signal ISC4 transitioning from the low state to the high state. NMOS transistor N8 is turned on. As a result, instead of the seventh closed circuit being cut off, the fourth output tap Lt4 is formed by forming an eighth closed circuit via the fourth output tap Lt4, the eighth NMOS transistor N8, and the first PMOS transistor P1. The fourth energy W4 stored therein is output to the output terminal via the eighth NMOS transistor N8 and the first PMOS transistor P1.

10 is a block diagram of a buck multi-output DC-DC converter according to a second embodiment of the present invention. FIG. 11 is a detailed circuit diagram of the buck multi-output DC-DC converter shown in FIG. 10, showing a four-step buck DC-DC converter.

10 and 11, the buck-type multi-output DC-DC converter includes a main controller 400, a switching unit 500, and an inductor unit 600. The main controller 400 generates control signals for controlling the switching unit 500. The switching unit 500 includes a synchronous rectification switching unit 510, a boost switching unit 520, and an inductor control switching unit 530 and is controlled by a control signal output from the main control unit 400. The inductor 600 includes one embedded inductor having first to fourth output taps Lt11 to Lt14, and boosts an input voltage Vin according to the inductor control switching unit 530. Output to the output.

The main controller 400 controls the synchronous rectification control signal SRSC11 for controlling the synchronous rectification switching unit 510 and the first to fourth boosting control signals for controlling the boost switching unit 520. MBSC11 to MBSC14 and first to fourth inductor control signals ISC11 to ICSC14 for controlling the inductor control switching unit 530 are generated.

The switching unit 500 includes a synchronous rectification switching unit 510, a boost switching unit 520, and an inductor control switching unit 530.

The synchronous rectification switching unit 510 is composed of a first PMOS transistor P11, and the first PMOS transistor P11 is connected between the node B1 and the ground Vss to connect the synchronous rectification control signal SRSC11. Is driven accordingly.

The boost switching unit 220 is connected between a node B1 and an input terminal and is connected between a first NMOS transistor N11 driven according to a first boosting control signal MBSC11 and between the node B1 and an input terminal. A second NMOS transistor N12 driven according to a second boosting control signal MBSC12 and a third NMOS transistor N13 connected between the node B1 and an input terminal and driven according to a third boosting control signal MBSC13. And a fourth NMOS transistor N14 connected between the node B1 and the input terminal and driven according to the fourth boosting control signal MBSC14. That is, the first NMOS transistors N11 to fourth NMOS transistors N14 are connected in parallel between the node B1 and the input terminal.

The inductor control switching unit 530 is connected between the node B1 and the first output tap Lt11 and is driven in accordance with the first inductor control signal ISC11 and the node N15. A sixth NMOS transistor N16 connected between B1 and the second output tap Lt12 and driven according to the second inductor control signal ISC12 and between the node B1 and the third output tap Lt13. A seventh NMOS transistor N17 connected to a third inductor control signal ISC13 and driven between the node B1 and a fourth output tap Lt14 to be connected to the fourth inductor control signal ISC14. The eighth NMOS transistor N18 is driven according to

Driving characteristics of the buck-type multi-output DC-DC converter configured as described above will be described with reference to FIG.

Referring to FIG. 12, during the period 'T0' to 'T1', the synchronous rectification control signal SRSC11 and the first boosting control signal MBSC11 in the high state from the main controller 100 are respectively the first PMOS transistor P11. As the first NMOS transistor N11 is input to the first PMOS transistor P11, the first PMOS transistor P11 is turned off and the first NMOS transistor N11 is turned on.

In this state, the fifth NMOS transistor N15 is turned on by inputting the high inductor control signal ISC11 of the high state from the main controller 100 to the fifth NMOS transistor N15. . As a result, a first closed circuit is formed via the first NMOS transistor N11, the fifth NMOS transistor N15, and the first output tap Lt11, so that the input voltage Vin is output through the first closed circuit. Vout).

Thereafter, the second boosting control signal MBSC12 and the second inductor control signal ISC12 of the high state are input to the second NMOS transistor N12 and the sixth NMOS transistor N16, respectively, from the main controller 100. As the first inductor control signal ISC11 transitions from high to low, the second and sixth NMOS transistors N12 and N16 are turned on while the fifth NMOS transistor N15 is turned off. . As a result, the first closed circuit is not interrupted, but instead of the first NMOS transistor N11, the sixth NMOS transistor N16, and the second output tap Lt12, the second NMOS transistor N12 and the sixth NMOS. By forming a second closed circuit via the transistor N16 and the second output tap Lt12, the input voltage Vin is output to the output terminal Vout through the second closed circuit.

Thereafter, the third boosting control signal MBSC13 and the third inductor control signal ISC13 of the high state are input to the third NMOS transistor N13 and the seventh NMOS transistor N17, respectively, from the main controller 100. As the second inductor control signal ISC2 transitions from high to low, the third and seventh NMOS transistors N13 and N17 are turned on while the sixth NMOS transistor N16 is turned off. As a result, the second closed circuit is not blocked, but instead of the second NMOS transistor N11, the seventh NMOS transistor N17, and the third output tap Lt13, the second NMOS transistor N12 and the seventh NMOS transistor. By forming the third closed circuit via the N17 and the third output tap Lt13 and via the third NMOS transistor N13, the seventh NMOS transistor N17, and the third output tap Lt13, the input voltage Vin is output to the output terminal Vout through the third closed circuit.

Thereafter, the fourth boosting control signal MBSC14 and the fourth inductor control signal ISC14 of the high state are input to the fourth NMOS transistor N14 and the eighth NMOS transistor N18 from the main controller 100, respectively. As the third inductor control signal ISC13 transitions from high to low, the fourth and eighth NMOS transistors N14 and N18 are turned on while the seventh NMOS transistor N17 is turned off. As a result, the third closed circuit is not blocked, but instead of the first NMOS transistor N11, the eighth NMOS transistor N18, and the fourth output tap Lt14, the second NMOS transistor N12 and the eighth NMOS transistor. The fourth NMOS transistor N14, via N18 and the fourth output tap Lt14, and via the third NMOS transistor N13, the eighth NMOS transistor N18, and the fourth output tap Lt14. Since the fourth closed circuit is formed via the eighth NMOS transistor N18 and the fourth output tap Lt14, the input voltage Vin is output to the output terminal Vout through the fourth closed circuit.

During the period 'T1' to 'T2', the first PMOS transistor P11 is turned on as the synchronous rectification control signal SRSC11 and the first to fourth boosting control signals MBSC11 to MBSC14 transition from a high state to a low state. -On and the first and fourth NMOS transistors N11 to N14 are turned off.

In this state, the fifth NMOS transistor N15 is turned on by the first inductor control signal ISC11 transitioning from the low to the high state. As a result, a fifth closed circuit via the first output tap Lt11, the fifth NMOS transistor N15, and the first PMOS transistor P11 is formed, thereby forming the first energy accumulated in the first output tap Lt11 ( W1 is discharged to ground Vss via the fifth NMOS transistor N15 and the first PMOS transistor P11.

Subsequently, the fifth NMOS transistor N15 is turned off because the first inductor control signal ISC11 transitions from a high state to a low state, and the second inductor control signal ISC12 transitions from a low state to a high state. NMOS transistor N16 is turned on. As a result, the fifth closed circuit is not interrupted, but instead, the sixth closed circuit via the second output tap Lt12, the sixth NMOS transistor N16, and the first PMOS transistor P11 is formed, thereby forming the second output tap Lt12. The second energy W2 stored in the discharge is discharged to the ground Vss via the sixth NMOS transistor N16 and the first PMOS transistor P11.

Thereafter, the sixth NMOS transistor N16 is turned off because the second inductor control signal ISC12 transitions from a high state to a low state and the third inductor control signal ISC13 transitions from a low state to a high state. NMOS transistor N17 is turned on. As a result, the sixth closed circuit is not interrupted, but instead, the seventh closed circuit via the third output tap Lt13, the seventh NMOS transistor N17, and the first PMOS transistor P11 is formed, thereby forming the third output tap Lt13. The third energy W3 accumulated in the discharge is discharged to the ground Vss via the seventh NMOS transistor N17 and the first PMOS transistor P11.

Thereafter, the seventh NMOS transistor N17 is turned off by the third inductor control signal ISC13 transitioning from the high state to the low state and the fourth inductor control signal ISC14 transitioning from the low state to the high state. NMOS transistor N18 is turned on. As a result, the seventh closed circuit is not interrupted, but instead, the eighth closed circuit is formed through the fourth output tap Lt14, the eighth NMOS transistor N18, and the first PMOS transistor P11, thereby forming the fourth output tap Lt14. The fourth energy W4 accumulated in the discharge is discharged to the ground Vss via the eighth NMOS transistor N18 and the first PMOS transistor P11.

As described above, the multi-output DC-DC converter of the first and second embodiments of the present invention includes an inductor part consisting of one inductor having a plurality of output taps, a switching part for controlling the inductor part, and the switching part. It is composed of a main controller for controlling the output of multi-level voltage.

As described above, the present invention is constructed by constructing a multi-output DC-DC converter as an inductor part consisting of one inductor having a plurality of output taps, a switching part for controlling the inductor part, and a main control part for controlling the switching part. In addition, the size of the plurality of inductor control switches and the boosting control switches constituting the switching unit can be reduced, and thus there are many advantages in terms of re-use or flexibility of the switches.

Claims (6)

An inductor unit in which a plurality of output taps are formed at predetermined intervals and to which an input voltage is supplied; A control unit for generating control signals; According to the control signals, each output tap of the inductor part is connected to ground to selectively accumulate energy in each output tap, and then each output tap is selectively connected to an output terminal so that the input voltage is connected to the inductor part. Multi-output DC-DC converter comprising a switching unit for outputting to the output terminal. The method of claim 1, A multi-output DC-DC converter, characterized in that the spacing between each tap of the inductor portion is made constant. The method of claim 1, The switching unit comprises: first switching means each comprising a plurality of transistors connected between each output tap of the inductor and a common node and operated according to the respective control signals; Second switching means connected between the node and the output terminal and operated according to the control signal; And And a third switching means comprising a plurality of transistors connected in parallel between said node and ground and selectively operated according to said respective control signals. An inductor unit having a plurality of output taps formed at predetermined intervals and connected to the output terminals; A control unit for generating control signals; Selectively connect each output tap of the inductor part to an input terminal according to the control signals to selectively accumulate energy at each output tap, and then selectively connect each output tap to ground, thereby storing the accumulated energy as ground. And a switching unit for discharging. The method of claim 4, wherein A multi-output DC-DC converter, characterized in that the spacing between each tap of the inductor portion is made constant. The method of claim 4, wherein The switching unit comprises: first switching means each comprising a plurality of transistors connected between each output tap of the inductor and a common node and operated according to the respective control signals; Second switching means connected between the node and ground and operated according to the control signal; And And a third switching means comprising a plurality of transistors connected in parallel between the node and the input terminal and selectively operated according to the respective control signals.