KR100404295B1 - Temperature sensing circuit having hysteresis generating means - Google Patents

Abstract

A temperature sensing circuit comprising hysteresis generating means is disclosed. The temperature sensing circuit of the present invention includes a temperature counter, a hysteresis generator and a comparator. The temperature counter generates a temperature accompanied signal and a temperature backed signal having a voltage level that changes in a direction opposite to each other with respect to a temperature change of the semiconductor device. The hysteresis generator senses and amplifies voltage levels of the temperature accompanying signal and the temperature backward signal to generate a rising comparison signal and a falling comparison signal having hysteresis characteristics. The comparator compares the voltage levels of the rising comparison signal and the falling comparison signal, and generates a temperature detection signal indicative of a predetermined set temperature. According to the temperature sensing circuit of the present invention, even when the internal temperature of the semiconductor device increases or decreases around the set temperature, the output signal has a stable logic state. In addition, while sensing a plurality of set temperatures, the driving of the means for generating the hysteresis characteristics is adjusted according to the range of the internal temperature of the semiconductor device, thereby minimizing the consumption of current.

Description

Temperature sensing circuit including hysteresis generating means {TEMPERATURE SENSING CIRCUIT HAVING HYSTERESIS GENERATING MEANS}

The present invention relates to a temperature sensing circuit of a semiconductor device, and more particularly to a temperature sensing circuit having hysteresis characteristics.

The temperature sensing circuit is a circuit for sensing the temperature of the semiconductor device and is embedded in the semiconductor device. Then, it is possible to determine whether the temperature inside the semiconductor device is higher than the set temperature by the transition of the output signal of the temperature sensing circuit. Such a temperature sensing circuit is variously used for driving a semiconductor device. In particular, the semiconductor memory device may appropriately control the refresh cycle by using the temperature sensing circuit.

By the way, the output signal of the temperature sensing circuit applied to the conventional semiconductor memory device continuously transitions the logic state when the temperature inside the semiconductor device increases or decreases in the vicinity of the set temperature. This continuous transition of logic states destabilizes the operation of the circuits embedded in the semiconductor device.

On the other hand, the conventional temperature sensing circuit is configured to sense one set temperature. Therefore, the semiconductor memory device incorporating the conventional temperature sensing circuit is difficult to control the refresh cycle in various ways.

Accordingly, an object of the present invention is to provide a temperature sensing circuit that generates an output signal having a stable logic state even though the internal temperature of the semiconductor device increases or decreases around the set temperature.

Another object of the present invention is to provide a temperature sensing circuit which senses a plurality of set temperatures and minimizes current consumption.

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram conceptually illustrating a temperature sensing circuit according to an embodiment of the present invention.

FIG. 2 and FIG. 3 are circuit diagrams showing in detail the temperature accommodating part and the temperature convoluting part of FIG. 1, respectively.

4 is a circuit diagram illustrating in detail the integrated hysteresis controller of FIG. 1.

5 to 7 are diagrams specifically illustrating the first to third hysteresis generators of FIG. 1.

FIG. 8 is a diagram illustrating an example of simultaneously implementing the integrated hysteresis controller and the first to third hysteresis generators illustrated in FIGS. 4 to 7.

FIG. 9 is a diagram illustrating the first to third comparators, the first to third hysteresis controllers, and the first to second enable controllers of FIG. 1.

10 to 12 are circuit diagrams specifically illustrating the first to third comparators of FIG. 9.

13A to 13C are diagrams illustrating voltage level changes of the rising comparison signal and the falling comparison signal according to temperature changes.

14 is a view showing a change in voltage level according to the temperature change of the main signals of the present invention.

One aspect of the present invention for achieving the above technical problem relates to a temperature sensing circuit. The temperature sensing circuit of the present invention includes a temperature counter, a hysteresis generator and a comparator. The temperature counterpart generates a temperature accompanying signal and a temperature backing signal having a voltage level that changes in a direction opposite to each other with respect to a temperature change of the semiconductor device. The hysteresis generator senses and amplifies voltage levels of the temperature accompanying signal and the temperature backward signal to generate a rising comparison signal and a falling comparison signal having hysteresis characteristics. The comparator compares the voltage levels of the rising comparison signal and the falling comparison signal to generate a temperature detection signal indicative of a predetermined set temperature.

One aspect of the present invention for achieving a technical problem different from the above relates to a temperature sensing circuit. The temperature sensing circuit of the present invention includes a temperature counter, first to nth temperature detection signal generators, and an integrated hysteresis controller. The temperature counterpart generates a temperature accompanying signal and a temperature backing signal having a voltage level that changes in a direction opposite to each other with respect to a temperature change of the semiconductor device. The first to n-th temperature detection signal generators detect voltage levels of the temperature accompanying signal and the temperature backward signal, and include a first to n-th set temperature where n is an integer of 2 or more. To nth temperature detection signals. In addition, the first to n-th temperature detection signal generators each include hysteresis generating means for causing the first to n-th temperature detection signals to have hysteresis characteristics. The integrated hysteresis control unit generates the integrated hysteresis control signal by combining the first to nth temperature detection signals. The integrated hysteresis control signal may be configured to determine a current path of the hysteresis generating means of each of the first to nth temperature detection signal generators with respect to a temperature of the semiconductor device that is out of the first set temperature and the nth set temperature. Cut off to reduce current consumption.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. For each figure, like reference numerals denote like elements. In addition, in the present specification, in describing transition points of signals having hysteresis characteristics for convenience of explanation, a change in transition point according to hysteresis characteristics may be omitted. This is because the width of the change of the transition point according to the hysteresis characteristic is macroscopically small.

1 is a block diagram conceptually illustrating a temperature sensing circuit according to an embodiment of the present invention. Referring to FIG. 1, the temperature sensing circuit of the present invention includes a temperature counter 100, first to third temperature detection signal generators 111, 121, and 131 and an integrated hysteresis controller 141. The temperature counter 100 detects a temperature change of the semiconductor device and generates a temperature accompanying signal CBS and a temperature backward signal PBS. With respect to the temperature change of the semiconductor device, the voltage of the temperature accompanied signal CBS changes in the same direction, and the voltage of the temperature returned signal PBS changes in the opposite direction. In detail, the temperature counterpart 100 includes a temperature accommodating part 101 for generating the temperature accommodating signal CBS and a temperature accommodating part 103 for generating the temperature accommodating signal PBS.

The first to third temperature detection signal generators 110, 120, and 130 respectively detect voltage levels of the temperature accompanying signal CBS and the temperature backward signal PBS, and respectively, the first to third temperature detection signals TEMP1, TEMP2, TEMP3). The logic states of the first to third temperature detection signals TEMP1, TEMP2, and TEMP3 transition at the first to third set temperatures TDET1, TDET2, and TDET3, respectively. In the present specification, for convenience of explanation, the first set temperature TDET1, the second set temperature TDET2, and the third set temperature TDET3 are set to be high.

The first temperature detection signal generator 110 includes a first hysteresis generator 111, a first comparator 113, and a first hysteresis controller 115. The first hysteresis generator 111 detects and amplifies voltage levels of the temperature accompanying signal CBS and the temperature backward signal PBS to generate a first rising comparison signal VPT1 and a first falling comparison signal VCT1. The first hysteresis generator 111 includes hysteresis means for causing the first rising comparison signal VPT1 and the first falling comparison signal VCT1 to have hysteresis characteristics. The first comparator 113 compares the voltage level of the first rising comparison signal VPT1 and the first falling comparison signal VCT1 and generates a first temperature detection signal TEMP1. The logic state of the first temperature detection signal TEMP1 transitions at the first set temperature TDET1. That is, when the temperature inside the semiconductor device rises to be equal to or higher than the first set temperature TDET1, the first temperature detection signal TEMP1 transitions from "low" to "high". The first hysteresis controller 115 controls the first hysteresis control signal HYS1 to control the first rising comparison signal VPT1 and the first falling comparison signal VCT1 to have hysteresis characteristics. To provide. The first hysteresis control signal HYS1 transitions from "low" to "high" in response to the transition from "low" to "high" of the first temperature detection signal TEMP1.

The second temperature detection signal generator 120 includes a second hysteresis generator 121, a second comparator 123, a second hysteresis controller 125, and a first enable controller 127. The controller 127 generates a first enable control signal TENA in response to the first temperature detection signal TEMP1. The first enable control signal TEA controls the driving of the second hysteresis generator 121, the second comparator 123, and the second hysteresis controller 125. That is, the first enable control signal TENA is activated to be “high” when the temperature inside the semiconductor device is lower than or equal to the first set temperature TDET1, so that the second hysteresis generator 121 and the second comparator 123 are activated. The second hysteresis controller 125 is driven. When the temperature inside the semiconductor device is higher than the first set temperature TDET1, the first enable control signal TANA is deactivated to "low" so that the second hysteresis generator 121 and the second comparator 123 are inactive. The driving of the second hysteresis controller 125 is blocked.

Meanwhile, the configuration and operation of the second hysteresis generator 121, the second comparator 123, and the second hysteresis controller 125 of the second temperature detection signal generator 120 may include the first temperature detection signal generator 110. The configuration and operation of the first hysteresis generator 111, the first comparator 113 and the first hysteresis controller 115 are almost the same. However, the driving of the second hysteresis generator 121, the second comparator 123, and the second hysteresis controller 125 is controlled by the first enable control signal TENA and the second temperature detection, which is an output signal. The only difference is that the logic state of the signal TEMP2 transitions from the second set temperature TDET1.

Similar to the second temperature detection signal generator 120, the third temperature detection signal generator 130 may also include a third hysteresis generator 131, a third comparator 133, a third hysteresis controller 135, and a third controller. It consists of two enable control unit 137. The configuration and operation of the third hysteresis generator 131, the third comparator 133, and the third hysteresis controller 135 may be performed by the second hysteresis generator 121, the second comparator 123, and the second hysteresis controller 125. It is almost identical to its composition and function. However, at the third set temperature TDET3, the logic states of the second enable control signal TNB and the third temperature detection signal TEMP3 are transitioned, so that the third hysteresis generator 131 and the third comparator 133 are transferred. There is only a difference in controlling the driving of the third hysteresis controller 135.

Each element constituting the first to third temperature detection signal generators 110, 120, 130 is controlled according to a range of internal temperature of the semiconductor device. That is, when the internal temperature of the semiconductor device is higher than the first set temperature TDET1, the current paths of the components of the second and third temperature detection signal generators 120 and 130 are blocked. The current path of the component of the third temperature detection signal generator 130 is continuously interrupted even when the internal temperature of the semiconductor device is between the first set temperature TDET1 and the second set temperature TDET2.

The integrated hysteresis control unit 141 logically operates the first to third temperature detection signals TEMP1 to 3 to generate the integrated hysteresis control signal HYSCON. The integrated hysteresis control signal HYSCON is connected to the ground voltage when the first to third temperature detection signals TEMP1 to 3 are all “low”, that is, at a temperature inside the semiconductor device lower than the third set temperature TDET3. VSS) to block all driving of the hysteresis means of the first to third hysteresis generators 111, 121, and 131.

FIG. 2 is a circuit diagram specifically illustrating the temperature accommodating part 101 of FIG. 1. Referring to FIG. 2, the temperature companion part 101 includes two PMOS transistors 211 and 213, two NMOS transistors 215 and 217, a diode D219, and a resistor R211. The PMOS transistor 211 and the NMOS transistor 215 form a current mirror with respect to the PMOS transistor 213 and the NMOS transistor 217.

Subsequently, the operation of the temperature companion portion 101 is described. When the temperature inside the semiconductor device rises, the voltage difference VD1 between the anodes of the diode 219 drops. At this time, the voltage of one terminal N218 of the resistor R221 is also lowered. Therefore, the amount of current flowing through the current path formed by the PMOS transistor 213, the NMOS transistor 217, and the resistor R221 decreases. Therefore, the voltage level of the temperature accompanying signal CBS also rises. Circuit elements forming reference numeral 230 are for maintaining an initial voltage of the temperature accompanied signal CBS at power-up.

3 is a circuit diagram illustrating in detail the temperature retrograde unit 103 of FIG. 1. Referring to FIG. 3, the temperature retrograde unit 103 includes two PMOS transistors 311 and 313 and two NMOS transistors 315 and 317, a resistor R319 and two diodes D321 and D323. do. The PMOS transistor 311 and the NMOS transistor 315 form a current mirror with respect to the PMOS transistor 313 and the NMOS transistor 317. The junction area of the diode D321 is k times (where k is an integer of 2 or more) relative to the junction area of the diode D323.

Subsequently, the operation of the temperature retrograde section 103 is described. When the temperature inside the semiconductor device rises, the voltage difference VD2 between the anodes of the diode D321 falls to a value larger than the voltage difference VD3 between the anodes of the diode D323. Therefore, the voltage difference formed in the resistor R319 increases, and the amount of current flowing through the current path formed by the PMOS transistor 311, the NMOS transistor 315, the resistor R319, and the diode D321 also increases. Therefore, the voltage level of the temperature retrograde signal PBS falls. Circuit elements forming reference numeral 330 are for maintaining the initial voltage of the temperature retrograde signal PBS at power-up.

As a result, when the temperature inside the semiconductor device increases, the voltage level of the temperature accompanying signal CBS rises, and the voltage level of the temperature retrograde signal PBS falls.

4 is a circuit diagram illustrating in detail the integrated hysteresis control unit 141 of FIG. 1. When the temperature inside the semiconductor device is equal to or lower than the third set temperature TDET3 and the logic states of the first to third temperature detection signals TEMP1 to 3 are all "low", the output signal N402 of the noah gate 401 is performed. ) Becomes "high". Thus, since the PMOS transistor 403 is " turned off " and the NMOS transistor 409 is " turned on ", the integrated hysteresis control signal HYSCON becomes " low ", that is, the ground voltage VSS. On the other hand, when the temperature inside the semiconductor device is higher than the third set temperature TDET3, the output signal N402 of the NOR gate 401 becomes "low". Therefore, the integrated hysteresis control signal HYSCON has a predetermined voltage level higher than the ground voltage VSS due to the conductance ratio of the PMOS transistors 401 and 403 and the NMOS transistor 405.

FIG. 5 is a diagram illustrating in detail the first hysteresis generator 111 of FIG. 1. Referring to FIG. 5, the first hysteresis generator 111 includes a falling response means 510, a rising response means 520, and a hysteresis means 530. The falling response means 510 includes PMOS transistors 511, 513, and 515 and NMOS transistors 517 and 519. The gates of the PMOS transistors 511 and 513 are biased by the temperature accompanying signal CBS and the temperature backward signal PBS, respectively. In addition, since the PMOS transistor 515 is gated by the ground voltage VSS, the PMOS transistor 515 always maintains a "turn-on" state. The NMOS transistors 517 and 519 are designed to have the same conductance, thereby representing a current mirror relationship. The falling response means 510 generates the first falling comparison signal VCT1 in response to the temperature accompanying signal CBS and the temperature backward signal PBS. That is, as the temperature inside the semiconductor device rises, the voltage of the temperature accompanying signal CBS increases, and the voltage of the temperature retrograde signal PBS falls. Therefore, the conductance of the PMOS transistor 511 decreases, and the conductance of the PMOS transistor 513 increases. Therefore, as the temperature inside the semiconductor device increases, the voltage level of the first falling comparison signal VCT1 decreases (see FIG. 13A).

The rising response means 520 also has a structure substantially similar to the falling response means 510. However, as the temperature inside the semiconductor device increases, the voltage level of the first rising comparison signal VPT1 provided from the rising response means 520 increases (see FIG. 13A).

As a result, when the temperature inside the semiconductor device rises to the first set temperature TDET1, the voltage level of the first rising comparison signal VPT1 becomes higher than the voltage level of the first falling comparison signal VCT1.

On the other hand, the first falling comparison signal VCT1 and the first rising comparison signal VPT1 have hysteresis characteristics controlled by hysteresis means 530 and 540. That is, the first falling comparison signal VCT1. ) And the logic state of the first rising comparison signal VPT1 occur at the first set temperature TDET1 in the process of increasing the temperature inside the semiconductor device. However, in the process of decreasing the temperature inside the semiconductor device, the temperature of the first falling comparison signal VCT1 and the first rising comparison signal VPT1 is slightly lower than the first set temperature TDET1. Logic state transitions. This is because the current path is formed by the hysteresis means 530, 540.

However, when the integrated hysteresis control signal HYSCON becomes the ground voltage VSS, the NMOS transistors 531 and 541 of the hysteresis means 530 and 540 are " turned off " The hysteresis characteristics of VCT1) and the first rising comparison signal VPT1 are removed.

FIG. 6 is a diagram illustrating in detail the second hysteresis generator 121 of FIG. 1. Referring to FIG. 6, the configuration of the second hysteresis generator 121 is similar to that of the first hysteresis generator 111 illustrated in FIG. 5. However, the falling response means 610 and the rising response means 620 so that the transition of the logic state between the second falling comparison signal VCT2 and the second rising comparison signal VPT2 occurs at the second set temperature TDET2. The conductance of the PMOS and NMOS transistors constituting the PMOS transistor is designed (see FIG. 13B). The PMOS transistor 615 of the falling response means 610 and the PMOS transistor 625 of the rising response means 620 are also designed. Is gated by the inverted signal of the first enable control signal (TENA). The rising response means 620 further includes an NMOS transistor 628 gated by an inversion signal of the first enable control signal TENA. Therefore, the current path of the falling response means 610 and the rising response means 620 is interrupted and unnecessary current above the first set temperature TDET1 at which the first enable control signal TEA is "low". To prevent consumption.

FIG. 7 is a diagram illustrating the third hysteresis generator 131 of FIG. 1 in detail. Referring to FIG. 7, the configuration of the third hysteresis generator 131 is similar to the second hysteresis generator 121 illustrated in FIG. 6. However, the falling response means 710 and the rising response means 720 so that the transition of the logic state between the third falling comparison signal VCT3 and the third rising comparison signal VPT3 occurs at the third set temperature TDET3. The difference is that the conductance of the PMOS and NMOS transistors constituting the PMOS transistors is designed (see FIG. 13C). Also, the PMOS transistor 715 of the falling response means 710 and the rise response means 720 are avoided. The difference is that the MOS transistor 725 and the NMOS transistor 728 are gated by an inverted signal of the second enable control signal TNB.

8 is a diagram illustrating an example of simultaneously implementing the integrated hysteresis controller 141 and the first to third hysteresis generators 111, 121, and 131 illustrated in FIGS. 4 to 7. Each component shown in FIG. 8 is given the same reference numeral as each component shown in FIGS. 4 to 7. Referring to FIG. 8, mirror blocks 510b, 610b, and 710b of the falling response means of the first to third hysteresis generators 111, 121, and 131 may be commonly implemented. With this common implementation, the layout area is reduced.

9 illustrates the first to third comparators 113, 123 and 133, the first to third hysteresis controllers 115, 125 and 135, and the first to second enable controllers 127 and 137 of FIG. 1. It is a figure which shows simultaneously. With reference to Figs. 9 and 14, the configuration and the effect of operation for each element are described. The first comparator 113 receives the first rising comparison signal VPT1 and the first falling comparison signal VCT1 through the positive input terminal IN (+) and the negative input terminal IN (−), respectively, Generate the temperature detection signal TEMP1. The second and third comparators 123 and 133 have substantially the same structure as the first comparator 113. However, the second and third comparators 123 and 133 are enabled when the first and second enable control signals TENA and TENB are in an active state of “high”, respectively.

The first enable control unit 127 is implemented as an inverter that inverts the first temperature detection signal TEMP1 to generate the first enable control signal TENA. The first enable control signal TENA has a logic state opposite to that of the first temperature detection signal TEMP1. That is, as shown in FIG. 14, when the temperature of the semiconductor device is higher than the first set temperature TDET1, the first enable control signal TEA is deactivated to “low”. The second enable control unit 137 is implemented by logical AND means for generating the second enable control signal TENB by ORing the first temperature detection signal TEMP1 and the second temperature detection signal TEMP2. . The second enable control signal TENB is activated "high" when both the first and second temperature detection signals TEMP1 and TEMP2 are "low". Therefore, when the temperature of the semiconductor device is higher than the second set temperature TDET2, the second enable control signal TNB is deactivated to "low".

The first hysteresis control unit 115 generates a first hysteresis control signal HYS1 by ANDing the power supply voltage VDD whose logic state is "high" and the first temperature detection signal TEMP1. Accordingly, the logic state of the first hysteresis control signal HYS1 is the same as the logic state of the first temperature detection signal TEMP1, as shown in FIG. 14.

The second hysteresis control unit 125 generates a second hysteresis control signal HYS2 by ANDing the first enable control signal TENA and the second temperature detection signal TEMP2. Therefore, when the internal temperature of the semiconductor device is lower than the first set temperature TDET1, the logic state of the second hysteresis control signal HYS2 is the same as the logic state of the second temperature detection signal TEMP2.

The third hysteresis control unit 135 generates a third hysteresis control signal HYS3 by ANDing the second enable control signal TNB and the third temperature detection signal TEMP3. Therefore, when the internal temperature of the semiconductor device is lower than the second set temperature TDET2, the logic state of the third hysteresis control signal HYS3 is the same as the logic state of the third temperature detection signal TEMP3.

FIG. 10 is a circuit diagram illustrating in detail the first comparator 113 of FIG. 9. Referring to FIG. 10, the first comparator 113 includes an amplification block 1010 and a buffer block 1030. When the voltage level of the first rising comparison signal VPT1 is higher than the voltage level of the first falling comparison signal VCP1, the output signal N1020 of the amplification block 1010 implemented in the form of a current mirror is the power supply voltage VCC. Rise to). The buffer block 1030 buffers the output signal N1020 of the amplification block 1010 to generate the first temperature detection signal TEMP1 having a "high" state. On the other hand, when the voltage level of the first rising comparison signal VPT1 is lower than the voltage level of the first falling comparison signal VCP1, the first temperature detection signal TEMP1 in the "low" state is generated. In this case, the amplification block 1010 and the buffer block 1030 are limited by the PMOS transistors 1012 and 1032 gated by the bias voltage Vbias.

FIG. 11 is a circuit diagram illustrating in detail the second comparator 123 of FIG. 9. The configuration and operation of the second comparator 123 of FIG. 11 are almost the same as the configuration and operation of the first comparator 113. Therefore, when the voltage level of the second rising comparison signal VPT2 is higher than the voltage level of the second falling comparison signal VCP2, the second temperature detection signal TEMP2, which is an output signal of the second comparator 123, is higher than the voltage level of the second falling comparison signal VCP2. Logical "high". When the voltage level of the second rising comparison signal VPT2 is lower than the voltage level of the second falling comparison signal VCP2, the second temperature detection signal TEMP2 becomes a logic "low".

However, the second comparator 123 has the following difference compared with the first comparator 113. That is, in the first comparator 113 of FIG. 10, the PMOS transistor 1011 and the NMOS transistor 1013 of the amplification block 1010, and the PMOS transistor 1031 of the buffer block 1030 are always turned on. Keep state. On the other hand, in the second comparator 123 of FIG. 11, the PMOS transistor 1111 and the NMOS transistor 1113 of the amplification block 1110, and the PMOS transistor 1131 of the buffer block 1130 are the first. Controlled by the enable control signal (TENA). Therefore, when the temperature inside the semiconductor device becomes higher than or equal to the first set temperature TDET1 and the first enable control signal TANA becomes "low", the amplification block 1110 of the second comparator 123 of FIG. And the current path of buffer block 1130 is blocked. Then, the second temperature detection signal TEMP2 is brought to a "low" state (see Fig. 14).

12 is a circuit diagram illustrating in detail the third comparator 133 of FIG. 9. The configuration and operation of the third comparator 133 of FIG. 12 are substantially the same as the configuration and operation of the first and second comparators 113 and 123. Therefore, when the voltage level of the third rising comparison signal VPT3 is higher than the voltage level of the third falling comparison signal VCP3, the third temperature detection signal TEMP3, which is an output signal of the third comparator 133, is higher than the voltage level of the third falling comparison signal VCP3. Logical "high". When the voltage level of the third rising comparison signal VPT3 is lower than the voltage level of the third falling comparison signal VCP3, the third temperature detection signal TEMP3 becomes a logic "low".

However, the third comparator 133 is compared with the second comparator 123, and the PMOS transistor 1211 and the NMOS transistor 1213 of the amplification block 1210, and the PMOS transistor of the buffer block 1230 ( There is a difference in that 1231 is controlled by the second enable control signal TNB.

In the temperature sensing circuit of the present invention, hysteresis is generated at the first to third set temperatures. Therefore, it is possible to prevent the first to third temperature detection signals from continuously transitioning. The current consumption can be minimized by adjusting the driving of the means for generating the hysteresis characteristics in accordance with the range of the internal temperature of the semiconductor device.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. For example, in the present specification, three temperature detection signals are generated to divide the temperature range into four, but further subdivision is possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the temperature sensing circuit of the present invention as described above, even when the internal temperature of the semiconductor device is increased or decreased near the set temperature, the output signal has a stable logic state. In addition, the temperature sensing circuit of the present invention senses a plurality of set temperatures, and adjusts the driving of the means for generating hysteresis characteristics according to the range of the internal temperature of the semiconductor device, thereby minimizing the consumption of current.

Claims (4)

In a semiconductor device, A temperature correspondence unit configured to generate a temperature accompanied signal and a temperature driven signal having a voltage level varying in a direction opposite to each other with respect to a temperature change of the semiconductor device; A hysteresis generator configured to sense and amplify voltage levels of the temperature accompanying signal and the temperature backward signal to generate a rising comparison signal and a falling comparison signal having hysteresis characteristics; And And a comparator for comparing the voltage levels of said rising comparison signal and said falling comparison signal to generate a temperature detection signal indicative of a predetermined set temperature. The hysteresis generator of claim 1, wherein And hysteresis means controlled by the temperature detection signal. In a semiconductor device, A temperature correspondence unit configured to generate a temperature accompanied signal and a temperature driven signal having a voltage level that changes in a direction opposite to each other with respect to a temperature change of the semiconductor device; First to nth temperature detection signals indicating first to nth (where n is an integer of 2 or more) sequential temperatures by sensing voltage levels of the temperature accompanying signal and the temperature retrograde signal; First to n-th temperature detection signal generators, the first to n-th temperature detection signal generators each including hysteresis generation means for causing the first to n-th temperature detection signals to have hysteresis characteristics; And An integrated hysteresis control unit for generating an integrated hysteresis control signal by combining the first to nth temperature detection signals, wherein the integrated hysteresis control signal is at a temperature of the semiconductor device that deviates between the first and nth set temperatures. And the integrated hysteresis control unit for blocking the current path of the hysteresis generating means of each of the first to nth temperature detection signal generators to reduce current consumption. The hysteresis generating means of claim n, And when the (n-1) th set temperature is sensed, the current path is cut off to reduce current consumption.