KR100404232B1 - micro controller unit - Google Patents

Abstract

With a serial mode control unit, the system can be configured to program / view / erase the flash EEPROM memory embedded in the microcontroller unit (Micro Controller Unit) with only a few pins. The purpose is to provide.

In order to achieve the above object, the microcontroller device includes a parallel mode control unit and a serial mode control unit capable of transmitting and receiving addresses and data in series with the flash memory unit, and a state count unit for controlling the operation of the serial mode control unit. And a shift register and a mode control unit.

Description

Micro controller unit

The present invention relates to a microcontroller, and more particularly, to a microcontroller unit (MCU) incorporating a flash EEPROM.

Referring to the accompanying drawings, a conventional microcontroller device will be described.

1 is a configuration diagram of a conventional microcontroller device, and FIG. 2 is a typical mode layout view of a conventional flash mode.

The conventional microcontroller device is for parallel programming in a microcontroller unit (MCU) incorporating a flash EEPROM.

The conventional structure is composed of a parallel mode control unit 10 and a flash memory unit 11 as shown in FIG.

The parallel mode control unit 10 operates in the parallel mode and enters each mode by the mode control pins CTL0, CTL1, CTL2, and CTL3.

Eight data I / O ports and eight address input ports send and receive data and addresses, respectively.

Interface speed is fast because data and address are exchanged in parallel, but many pins (VCC, GND, CTL0 ~ CTL3, VPP (when using external VPP), 8 data ports, 8 address ports, 2 control pins for flash mode entry) (RST, PSEN)), which is not suitable for system-on-programming.

The flash memory unit 11 includes a flash memory array and a peripheral circuit thereof, and includes a read data latch RD_DLAT, a read data clock RD_CK, a write data bus WTDB, a write program ROM WTPROM, and erase. ), The flash cell is written, read and erased by receiving a signal.

The typical mode of the conventional flash mode is divided into read signal, read lock bits, inquiry code data, program code data, program lock bits, eraser, 4 byte load and 4 byte program mode as shown in FIG. For each mode, input signals of RST, / PSEN, / PROG, / (EA / VPP), P2.5, P2.6, P3.7 and P3.6 separately, and selectively address each mode. In each mode, data is transmitted by byte signal output, lock bit output, code data output, code data input, lock bit input, or eraser bit input in each mode.

The conventional microcontroller device as described above has the following problems.

Many pins are needed when system-on-programming by sending and receiving data and addresses in parallel.

Therefore, it is inconvenient to use, the system configuration cost is high, and the program update is not easy.

The present invention has been made to solve the above problems, and in particular, the system is configured to program / query / erase the flash EEPROM memory embedded in the MCU with only a small number of pins with a serial mode control unit The aim is to provide a microcontroller device suitable for reducing configuration costs.

It is still another object of the present invention to provide a microcontroller device suitable for preventing parallel test mode as well as increasing test cost in the future.

1 is a block diagram of a conventional microcontroller device

Figure 2 is a typical mode layout of the conventional flash mode

3 is a block diagram of a microcontroller device according to the present invention in which a serial mode control unit is added;

4 is a layout diagram of a serial control mode according to the present invention.

5 is a block diagram of a mode control unit for controlling the serial mode control unit according to the present invention

6A and 6B show a serial mode timing diagram in accordance with the present invention.

7 is a timing diagram for serial mode entry and release;

Explanation of symbols on the main parts of the drawings

30: serial mode control unit 31: parallel mode control unit

32: flash memory section 50: status count section

51: shift register 52: mode control unit

The microcontroller device of the present invention for achieving the above object is a state counting unit for counting the serial clock (SCLK) to output the timing signals (ST0 ~ ST14) required for each mode, and the serial input to match the serial clock Shift the data SDATA to output the command according to each mode to the mode control unit, and receive various control signals generated by the mode control unit, convert the serial data into parallel data to make the address or write the data to write It is loaded on a null address bus or data bus, and in the verify mode, a shift register for converting the parallel data read on the data bus into serial data and outputting the same is determined. And the control signal suitable for the determined mode In this mode, the address and data can be input / output from the register. In the parallel mode, the mode control unit controls the write / verify data to be input / output to the n-bit port. And a flash memory unit comprising a plurality of flash cell arrays configured to receive, read, and / or erase a flash cell by receiving a read data latch signal, a read data clock, a write data bus signal, a write program ROM signal, and an erase signal. Receives a serial mode control signal from the unit and receives the serial clock (SCLK) and operates serially through the serial data (SDATA) pin to exchange the address and data with the flash memory unit in series to enable program / query / erase operation. And a mode control unit and a mux with the control signal. In the case of the parallel mode, the flash memory unit includes a parallel mode control unit that exchanges addresses and data in parallel.

The control circuit of the microcontroller device of the present invention will be described with reference to the accompanying drawings.

3 is a configuration diagram of a microcontroller device according to the present invention to which a serial mode control unit is added, and FIG. 4 is a layout view of a serial control mode according to the present invention.

5 is a block diagram of a mode control unit according to the present invention.

6A and 6B are serial mode timing diagrams according to the present invention, and FIG. 7 is a timing diagram for serial mode entry and release.

The present invention is a circuit for controlling data to be transmitted and received serially (Serial) in a microcontroller (MCU) built-in Flash EEPROM.

As described above, the present invention further includes a serial mode control unit 30 in order to exchange data and addresses in series.

By further including the serial mode control unit 30 as described above, the program (PGM), verify and erase (PGM), flash (EGM) of the flash EEPROM are connected by a total of 5 pins including the power pins (VCC, GND). To facilitate system-on-programming.

As described above, the microcontroller device according to the present invention has a serial mode control unit 30, a parallel mode control unit 31, a flash memory unit 32, and the serial mode control unit as shown in FIGS. 3 and 5. A state counter 50, a shift register 51, and a mode control unit 52 for controlling the unit 30 are included.

First, the serial mode control unit 30 operates in the serial mode (S_MODE), operates by receiving a serial clock (SCLK) for synchronizing a signal with the outside, and is input together with the serial clock (SCLK). A command included in the serial data SDATA is decoded, and a control signal for accessing the flash memory unit 32 is generated according to each command.

In addition, an address may be generated or, in some cases, serial data may be converted into parallel data or vice versa.

The total pins used are VCC, GND, SCLK, SDATA, and VPP (if an external VPP is required), which is ideal for system-on-programming.

In addition, the parallel mode control unit 31 operates in the parallel mode, and enters each mode corresponding to the serial mode by the mode control pins CTL0, CTL1, CTL2, and CTL3.

Eight data I / O ports and eight address input ports send and receive data and addresses, respectively.

The control signals for accessing the flash memory are muxed with the control signals in the serial mode.

Since the parallel mode control unit 31 exchanges data and addresses in parallel unlike the serial mode, since the interface speed is high, but many pins need to be allocated, the parallel mode control unit 31 is not suitable for system-on-programming. use.

The pins used in the parallel mode control unit 31 as described above are VCC, GND, CTL0 to CTL3, VPP, eight data ports, and eight address ports.

Next, the flash memory unit 32 includes a flash memory array and a peripheral circuit thereof. The read data latch RD_DLAT, the read data clock RD_CK, the write data bus WTDB, the write program ROM WTPROM, and the erase circuit 32 are erased. The flash cell is written, read or erased by receiving the (ERASE) signal.

Next, a configuration of the mode control unit according to the present invention will be described with reference to FIG.

As shown in FIG. 5, the mode control unit according to the present invention is activated in the flash mode, and the state control unit 50, the shift register 51, and the mode control unit 52 as described above. It is composed.

At this time, the state counter 50 counts the serial clock SCLK and outputs ST0 to ST14, which are timing signals required for each mode.

The shift register 51 shifts the serial data SDATA input in accordance with the SCLK, sends a command portion to the mode control unit 52, and transmits the serial data by various control signals generated by the mode control unit 52. Converts the data into parallel data to create an address or write data to be loaded on the internal address bus and data bus, respectively.In the inquiry mode, the read parallel data on the data bus is converted into serial data and output as SDATA. will be.

The mode control unit 52 deciphers the instruction made in the shift register 51 to determine the mode entry and generates a control signal suitable for each mode so that the address and data can be input / output properly in the shift register 51. In parallel mode, write data or inquiry data can be input / output to an 8-bit port.

The pins required for the interface of the present invention are five in total: VCC, GND, SCLK, SDATA, and VPP when using only the serial mode, and VCC, GND, CTL0 to CTL3, VPP, and data port when using the parallel mode. It has eight address ports, eight address ports, mode control pins CTL0 to CTL3, and two control pins for flash mode entry.

6A and 6B, the serial data format in the serial mode will be described with a timing chart.

Serial data formats include a format consisting of commands and data, and a format consisting only of commands.

As shown in Figs. 6A and 6B, the command is composed of 5 bits, and when the C4 bit is "1", only the command is executed without data exchange, and the next command is waited.

However, if the C4 bit is "0", it is command data. Therefore, the command is decoded to receive or output the data following the command appropriately for each mode.

The data part consists of 10 bits, and the values of the most significant bit (MSB) and least significant bit (LSB) are always "0", and this value is not used.

The state counting unit 50 receives the SCLK clock and generates the state clocks of ST0 to ST14 to find out what the value of SDATA currently being input means. In case of command data, jump to ST0 to receive the next command after ST14.

The mode control unit 52 decodes the commands from the ST4 and generates a mode activation signal for each command, and outputs signals for controlling the flash memory and various signals necessary for address generation and data input / output at an appropriate time. .

The shift register 51 shifts and stores the SDATA input in a register in synchronization with the SCLK, and the command is sent to the mode control unit 52, and the data is made an address or the write data is controlled by the mode control unit 52. Send to internal address bus or data bus.

In the inquiry mode, the data input from the data bus is stored in the shift register 51, and then shifted to SDATA at the rising edge of ST6 in order to output.

Next, the serial control mode and the operation of each mode will be described with reference to FIGS. 4, 6A, and 6B.

As shown in Figs. 4, 6A and 6B, the serial control mode can be explained by dividing into five.

First, the load address mode converts serial address data input to the SDATA pin into parallel address data and loads the upper or lower address counter.

The load address mode is divided into a load high address and a load low address.

In the verify mode, the sense amplifier is operated by the read data latch (RD_DLAT) signal to read the flash memory of the flash memory unit 32, and the data read by the write data bus (WTDB) signal is internal. After loading on the data bus, parallel data is converted to serial data and output as SDATA.

The write mode converts serial data inputted through SDATA into parallel data, and loads the internal data bus by a write data bus (WTDB) signal, and stores the address counter value to the internal address bus. Write to the flash memory using a write program ROM (WTPROM) signal.

In the erase mode, the flash memory can be erased and a flash cell bias condition required for erasing is performed to perform an erase operation while the erase signal is activated.

The increment address mode increases the address of the address counter.

As shown in Fig. 4, in the load high address mode, an 8-bit address is input with the C1 command " high ", and an 8-bit address is input with the C3 and C1 commands " high " Let's do it.

In the inquiry mode, 8-bit data is inputted with the commands C2 and C1 set to "high". In the write mode, 8-bit data is inputted with the command C3 set to "high". In the erase mode, the commands C3 and C2 are entered. 8 bit erase data is inputted with " high ".

In the address increase mode, only a command in which C4, C3, C2, and C1 are "high" is input.

When the mode as described above will be described in more detail with respect to the operation of each mode with a timing chart as follows.

First, in the load " high " or load " low " address mode, as shown in FIG. 6A, the mode controller 52 reads the load address high which is the mode activation signal after decoding the command at the falling edge at which ST4 starts. Activate the mode (Load Address High Mode (LAHM) or Load Address Low Mode (LALM)) to ST4 of the next instruction and change the value of the shift register at ST14, when all the address values enter the shift register 51. Store it in the address counter.

Next, in the load data mode, when the 4-byte write mode is implemented to reduce the write time, the load data mode is used to write the data to be written four times and write them all at once.In the load data mode, the write operation is not performed and the address counter is written to the address counter. It is latched in the flash memory write path of the stored address.

At this time, the address should be increased before loading the next data.

In addition, the inquiry mode is a mode of reading data stored in the flash memory. After reading the instruction in ST4, the read data latch RD_DLAT and RD_CK are made to read the data of the address stored in the address counter and stored in the shift register 51 in ST5. And output to SDATA in synchronization with SCLK from ST6 to ST14.

The write mode decodes the instruction in ST4, creates a WTDB in ST14, loads the data entered into the shift register 51 onto the data bus, latches the data in a write path, and writes while ST0. The write time is until the next command starts after entering the write mode.

The erase mode is a mode for erasing flash cell data. The shift register value input to ST14 is an erase block register (EBR), and an erase signal is generated to erase a block according to the EBR value. As with the write time, the time is until the next command is entered after entering the erase mode.

The 4-byte write mode then creates a 4-byte program mode to write the latched 4-byte data in the load data mode, and holds the write until the next command is entered while ST0.

And address increment mode saves time by using only instructions rather than giving address every time data is read and written.

Since the value of the address counter is incremented and decremented by one, the load address mode must be used to access the address in the address reduction direction.

In the dummy mode, if the last command is a write or erase operation, there is no next command, and thus the write or erase operation is performed continuously. Therefore, the chip may be damaged.

In addition to the serial mode as described above, there is a parallel mode, and this parallel mode uses MUX with control signals for controlling the flash memory.

This parallel mode is intended for use in program / query / erase operations or to test flash memory in ROM writers because of the larger data and address bandwidth than serial mode.

Next, a method of entering and releasing to proceed with the serial mode and the parallel mode will be described with reference to FIG. 7.

First, in parallel mode, as in the conventional method, the control pin (PIN) for resetting the flash mode (RST) and PSEN become "1" and "0", respectively, to enter the parallel mode. In this case, the serial mode, the user mode, and other test modes are entered. Is disabled.

In the serial mode, when both VCC and GND are applied and reset (RST) is "1", when both SDATA and SCLK are "0", the serial mode is entered.

In the user mode, parallel mode, and test mode, if RST is "1", the serial mode is not available because SDATA and SCLK remain "1" by internal pull-up unless SDATA and SCLK are forced to "0" from the outside. no.

In this case, when entering the serial mode, the serial mode entry timing follows the initial entry as shown in FIG. 7.

And even when entering serial mode, serial mode logic is disabled when it enters parallel mode, another test mode, or user mode.

The microcontroller device of the present invention as described above has the following effects.

The addition of a serial mode control unit allows the user to program / query / erase the flash EEPROM with only five pins, reducing system configuration costs.

In addition to supporting serial mode as well as parallel mode, ROM memory can be used to code or test program memory, thus avoiding increased test costs.

Claims (1)

A state counting unit for counting the serial clock SCLK and outputting timing signals ST0 to ST14 necessary for each mode; Shift the serial data (SDATA) input according to the serial clock to output a command according to each mode to the mode control unit, and receive various control signals generated by the mode control unit to convert the serial data into parallel data to create an address A shift register which converts the read parallel data on the data bus into serial data in the Verify mode, and generates data to be written or written to, respectively, on an internal address bus or a data bus. Determining the mode to enter by deciphering the instruction made in the shift register, and making a control signal suitable for the determined mode so that address and data can be input / output in the shift register, and write data or inquiry in parallel mode. (Verify) mode control unit for controlling data to be input / output to the n-bit port, A flash memory unit configured to receive a read data latch signal, a read data clock, a write data bus signal, a write program ROM signal, and an erase signal to write, read, or erase the flash cells; Receives a serial mode control signal from the mode control unit and operates the serial clock (SCLK), and transmits / receives data in series with the flash memory unit and the address through a serial data (SDATA) pin to enable program / query / erase operation. Serial mode control unit, And using the control signal with the serial mode control unit (MUX), and including a parallel mode control unit for transmitting and receiving an address and data in parallel with a flash memory unit in a parallel mode.