KR100401532B1 - Apparatus and method for long cycle test of wafer - Google Patents

Abstract

PURPOSE: An apparatus and method for long cycle test of a wafer are provided to be capable of identifying a fail address. CONSTITUTION: A long cycle test apparatus includes a memory part(20), an address defining part(40), an address selecting part(50) for selecting an input address and outputting the input address, a fail address storing part(60), a fail address comparing part(70), a data generating part(80), a data defining part(90), a storing part(100). The memory part outputs an address and data according to command of a test control part(10). The address defining part determines an input address generated by an address generating part(30) and test execution range.

Description

Wafer Long Cycle Testing Apparatus and Method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a long cycle test apparatus and method for wafers, and more particularly, to an address test apparatus and method for verifying a fail address by performing a long cycle test in a wafer state.

In general, the primary fail in a package appears as a failure related to long cycle testing after burn-in, so long cycle testing requires a device for repair analysis that interprets whether low cost and fail address repairs are possible. .

In this case, the long cycle test is a mask that stores a fail address in a low speed test and can be tested without an algorithm for finding an additional fail bit and without a conventional fail memory. That is, a long cycle test is performed after reading the failed address information in the pretest using a mask memory and skipping generation of the fail address through the fail address mask function. In this case, even if there is no overall fail memory, the repair of the test for a long cycle is possible by performing the repair analysis once more by storing the fail bit address and mixing the fail data in the pretest.

On the other hand, in high-density DRAMs of 16 megabytes or more, long cycle tests and repair analysis must be performed in the wafer state in order to screen the fail for the long cycle test after burn-in.

In this case, however, the repair analysis requires almost the same number of fail memories as the number of high-density devices, so it is virtually impossible to perform long-cycle tests in the state of wafers that require expensive equipment and take time. Existed.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and a long cycle test is performed to check a fail address in a wafer state by using a mask memory that reads a memory repair data file generated after a pretest and stores the failed address. It is an object of the present invention to provide an apparatus and method for testing a long cycle of a wafer.

1 is a block diagram of a long cycle test apparatus for a wafer according to an embodiment of the present invention.

* Explanation of symbols on the main parts of the drawings *

10: test control unit 20: memory unit

30: address generator 40: address limiter

50: address selection means 60: fail address storage means

61: fail mask memory 70: address comparison section

80: data generator 90: data limiter

100: storage unit

In order to achieve the above object, a long cycle test apparatus for a wafer of the present invention has already been stored based on a command of the test control unit which instructs to perform a test by designating an address for a long cycle test. A long cycle test is performed among a memory unit for outputting the address and data being executed, an address generator for generating a long cycle test of the address transmitted from the memory unit, and an address input from the address generator. An address defining unit for determining a range of addresses to be performed, an address selecting unit for selecting and outputting addresses input from the address limiting unit, a fail address storing unit for storing an address where a fail is generated in a wafer state after pretesting; The address selection A fail address comparison unit which compares and judges the addresses inputted from the means and the fail address storing means, and outputs only addresses that do not match, and stores and reads data input from the memory unit at an address input from the address generator; A data generating unit for generating the data, a data defining unit for defining a reading range of the data generated from the data generating unit, and an address and data inputted from the fail address comparing unit and the data defining unit so as to be accessed. It characterized in that it comprises a storage unit for storing.

EXAMPLE

Hereinafter, a preferred embodiment of the present invention with reference to Figure 1 as follows.

1 is a block diagram of a long cycle test apparatus for a wafer according to an embodiment of the present invention.

Referring to FIG. 1, a long cycle test apparatus for a wafer according to an embodiment of the present invention may include a memory unit 30 and a memory unit 30 configured to transfer an address and data that are already stored, based on a command of the test controller 10, to be tested. 20 is generated to be tested by the address generator 30 and inputted, the address defining unit 40 determines a range of addresses to be tested among the generated addresses, and a fail is generated. A fail address storing means 60 for storing an address and an address selected and input by the address selecting means 50 among the addresses output from the address defining unit 40 and an address input from the fail address storing means 60; From the fail address comparison unit 70 and the address generator 30 that output only the addresses that do not match. A data generator 80 for storing and reading the data input from the memory unit 20 at the input address, and a data defining unit 90 for limiting the reading range of the data generated from the data generator 80; And a storage unit 100 which stores the address inputted from the fail address comparing unit 70 and the data inputted from the data defining unit 90 to be accessed and confirmed.

The address limiting unit 40 includes a first address limiting unit 41 for limiting a range for performing a long cycle test of the X address input from the address generating unit 30 and outputting it to the address selecting means 50; A second address limiting unit 42 for limiting the range for performing the long cycle test of the Y address input from the address generating section 30 and outputting it to the address selecting means 50 is provided.

The test control unit 10 instructs the memory unit 20 to perform a long cycle test for checking a fail state of the X addresses and the Y addresses stored in the memory unit 20.

By the test control unit 10, the memory unit 20 stores the X address and the Y address stored in accordance with the instruction for executing the long cycle test of the X address and the Y address transmitted from the test control unit 10. And outputs the stored data to the data generator 80.

The address generator 30 generates the X addresses and the Y addresses input from the memory unit 20 so as to perform a long cycle test, and outputs them to the address defining unit 40. The address limiter 40 limits the range for performing the long cycle test of the X address input from the address generator 30 through the first address limiting unit 41 and performs the long cycle test of the Y address. The range for carrying out is carried out through the second address limiting unit 42.

The address selecting means 50 includes a multiplexer 51 for selecting the X address and the Y address input from the address defining unit 40 and outputs the selected address to the fail address comparison unit 70.

The fail address storing means 60 includes a fail mask memory 61 which reads a memory repair data file generated after a pretest and stores the failed address in a wafer state. The address comparison unit 70 outputs the result.

The address comparison unit 70 compares and determines the address selected and selected by the address selecting means 50 and the fail address input from the fail address storing means 60. Only the non-failed addresses that do not match and do not match are output to the storage unit 100.

The data generator 80 generates the data input from the memory 20 at the address input from the address generator 30 so that the data can be stored and read, and outputs the data to the data limiter 90.

The data defining unit 90 determines a range for reading data input from the data generating unit 80 and outputs the read range to the storage unit 100.

The storage unit 100 stores the address input from the address comparison unit 70, and also stores the data input from the data defining unit 90.

Therefore, the fail address is determined using the address comparison unit 70 as described above, the storage unit 100 stores only the unfailed addresses and data, and accesses and confirms the addresses and data stored in the storage unit 100. As a result, the failed and unfailed addresses can be known, and by storing and confirming only the unfailed address in the storage unit 100, the time required for the long cycle test can be shortened.

As described above, the long cycle test apparatus and method of the wafer of the present invention can save time in long cycle testing on the wafer by providing only an unfailed address, and provide an excellent effect of reducing the cost. .

Claims (4)

A test control unit for instructing a test to be specified by specifying an address for long cycle testing, a memory unit for outputting an address and data already stored according to the command of the test control unit, and an address transferred from the memory unit An address generator for generating a long cycle test; an address limiter for determining a range of addresses to be subjected to a long cycle test among the addresses inputted from the address generator; An address selection means for selecting and outputting addresses, a fail address storage means for storing an address where a fail is generated in a wafer state after pretesting, and comparing and determining addresses inputted from the address selection means and the fail address storage means. As a result, a fail address comparison unit for outputting only addresses that do not match, a data generator for generating data read from the memory unit at the address input from the address generator, and generating the read data; A long cycle test of a wafer, comprising: a data defining unit defining a reading range of the data; and a storing unit storing and storing the fail address comparison unit and the address and data inputted from the data defining unit. Device. The first address limiting unit according to claim 1, wherein the address limiting unit defines a range for performing a long cycle test of the X address inputted from the address generating unit and outputs to the address selecting unit the first address limiting unit; And a second address limiting unit for limiting a range for performing a long cycle test of the input Y address and outputting the address to the address selecting means. The wafer long cycle test apparatus according to claim 1, wherein said address selecting means includes a multiplexer for selecting an address inputted from said address limiting unit. Instructing a long cycle test to check a fail state of the addresses, outputting an address stored based on the long cycle test execution command, and outputting the stored data; Generating a cycle test, defining a range of addresses to perform a long cycle test, selecting and outputting an X address and a Y address, and failing in a wafer state generated after the pretest. Outputting the stored address, outputting only the unfailed address without determining and outputting the fail address, generating and outputting the input data so that the input data can be stored and read, and a range for reading the input data. And outputting the unpaid ad And storing the data, and storing the data, and determining the fail address by accessing and confirming the stored unfailed address.