KR100397400B1 - Multi channel image processing system by digital signal processing - Google Patents

Abstract

The present invention relates to a multi-channel image processing system and a chip of a digital signal processing method, receives an analog composite video signal from one or more channels, digitizes it, stores it in a memory, and stores and stores the stored image data in a memory. Its purpose is to implement an ASIC chip that can be fabricated without a frame loss and communicates with a computer by using a PCI bus. According to an aspect of the present invention, there is provided a multi-channel image processing chip of a digital signal processing method, comprising: a video signal decoding unit for receiving an analog composite video signal input from at least one channel and digitizing each channel; A memory unit for storing processed image data for each channel; A controller unit which obtains and processes image data for each channel from a memory; It outputs the processed image data, and includes a bus interface for interfacing the controller unit and the computer.

Description

Multi channel image processing system by digital signal processing

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-channel image processing system of a digital signal processing method. In particular, a composite video signal inputted in analog from two or more channels is converted into a video signal by a digital signal processing method. The present invention relates to a system that decodes and processes all images input to each channel without losing a frame.

The conventional multi-channel support method operates by switching the video input to the video decoder chip for each channel in order to support one or more multi-channel, or as many video signal decoder chip and the chips as necessary It is using a multi-channel interface chip to connect.

However, the conventional multi-channel support method has the following problems.

First, when multi-channel is supported by one image processing chip, the frames lost due to the synchronization operation for each channel and the switching operation time between channels in the image signal decoder increase the number of frames per second. There is a problem that the number is small.

Second, in the case of supporting multiple channels by using one image processing chip, even if the frame to be lost is reduced as much as possible, the limited frames must be divided into several channels, resulting in fewer frames per channel. For example, if one image processing chip normally supports 30 fps (Frame per Second) and displays four channels separately, even if there is no frame loss, one channel of 30 fps is used. / 4, i.e., only about 7 fps can be displayed, causing serious problems such as unnatural screens.

Third, in the case of supporting multiple channels using two or more image processing chips, hardware size is increased and the price is increased because a multi-channel interface chip for using two or more image processing chips is used in addition to the image processing chip. For example, in case of supporting two channels by using an image processing chip using a Peripheral Component Interconnection (PCI) interface as a computer communication method, communication between the two image processing chips and the computer in addition to the two image processing chips is required. At least one PCI-to-PCI bridge chip must be used.

In order to solve the above problems, the present invention provides an ASIC including an image signal decoder and a memory unit, a controller unit, and a bus interface unit for each channel to process analog signals input for each channel in a single system. Its purpose is to provide a multi-channel image processing system in the form of a chip.

1 is a diagram illustrating a mode of a display screen according to an exemplary embodiment of the present invention.

2 is a block diagram showing a configuration of an ASIC chip according to an embodiment of the present invention.

3 is a block diagram showing a configuration of a video signal decoding unit;

4 is a diagram showing that image data processed by a video signal decoding unit is recorded for each memory area.

5 is a view showing the operation of the controller unit.

Fig. 6 is a diagram showing that the DMA reads image data from each memory area.

7 is a diagram illustrating displaying image data on a monitor screen.

8 is a diagram illustrating a video capture system according to an exemplary embodiment of the present invention.

The multi-channel image processing system of the digital signal processing method according to the characteristics of the present invention for achieving the above object

A video signal decoding unit for receiving an analog composite video signal input from at least one channel and digitizing each of the analog video signals;

A memory unit for storing the processed image data through the image signal decoding unit for each channel;

A controller unit which obtains and processes image data for each channel from a memory;

It outputs the processed image data, and includes a bus interface for interfacing the controller unit and the computer.

The video signal decoding unit may include: an analog digital converter (ADC) unit for digitizing a composite image such as NTSC / PAL; An image decoding unit for processing the digitized data; A scaler unit for reprocessing the resolution of the processed image data at a predetermined ratio; And a video format conversion unit for converting the image data format to be stored in the memory.

In addition, the controller unit controls the image signal decoder and the memory, and performs overall control of obtaining the stored image data from the memory using one direct memory access (DMA) and transferring the image data to the bus interface unit. RISC Processor to perform.

The bus interface unit uses a Peripheral Component Interconnection (PCI) bus interface as a communication method with a computer, and transmits a command signal for performing the controller unit from the computer to the controller unit and transmits image data to the computer. .

Hereinafter, with reference to the accompanying drawings, the most preferred embodiment of the present invention will be described in detail. First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals are denoted by the same reference numerals as much as possible even if displayed on different drawings, in describing the present invention, If the detailed description of the configuration is determined to be apparent to those of ordinary skill in the art, or if it is determined that it may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

1 is a diagram illustrating a mode of a display screen that can be displayed when operating hardware manufactured by applying a 4-channel supporting image processing chip according to an exemplary embodiment of the present invention. As shown in FIG. 1, in the 4-split screen mode, images of all channels can be displayed on the 4-split screen without losing a frame. Also, in the unsplit screen mode, one channel is not divided. Can be displayed on. In this case, any of the four channels that can be displayed on the undivided screen may be displayed, and of course, image data may be stored for channels that are not displayed at the same time. Therefore, when 30 fps video is input per channel, a total of 120 fps video is displayed by adding four channels in the 4-split screen mode.

2 is a block diagram illustrating a multi-channel image processing chip of a digital signal processing method according to an embodiment of the present invention.

As shown in FIG. 2, in the image processing chip supporting four channels, one video signal decoder 100 for digitizing an analog composite video signal input to each channel is allocated to each channel. The image data processed from these image signal decoders is stored in the memory 200, and the DMA controller 300 receives the image data stored in the memory according to a command of the RISC processor 400. The data is transmitted to the PCI interface 500 so that the computer can receive the image data by communicating with the computer using the PCI bus.

3 is a block diagram illustrating a structure of the video signal decoding unit 100 of FIG. 2.

As shown in FIG. 3, an analog composite video signal is received as an input and sampled into a digital signal using an analog to digital converter 101. In this case, the analog composite video signal is a signal such as a National Television System Committee (NTSC) or a Phase Alternation by Line (PAL), such as a TV (Television), a VTR (Videotape recorder), These signals are international standards widely used in camcorders, closed-circuit television (CCTV) cameras, and the like, and these video input devices are not shown.

The data sampled through the analog-to-digital converter 101 is processed into image data while passing through the decoder 102, and the size (resolution) of the image is determined while passing through the scaler 103. This video data is again processed into a conventional video decoded signal through a format convertor 104.

For example, the data sampled through the 10-bit ADC 101 is decoded by the decoder 102 into normal video data such as RGB or YUV in accordance with the synchronization signal, and one frame is 720x480 ( In the case of PAL, 720x576 image data is generated. This image data has resolutions of 640x480, 320x240, 360x240, etc. while going through a scaler, and is processed into data such as YCrCb 4: 2: 2 of the image data standard by the video format converter 104 and stored in the memory.

The above description is deemed to be well known to those skilled in the art, and thus a detailed description thereof will be omitted.

The image data of each channel decoded by the image decoder 100 is recorded in the memory 200, and the recorded image data is displayed on the screen simultaneously without frame loss in the multi-channel image data according to the command of the risk processor 400. Connected to the DM unit 300 so as to be able to do so, the DM unit transfers the image data to the interface unit 500 in a multi-channel processing method through a single DM (DMA). The transfer method of such image data includes the following methods.

First, a method in which the DMA 300 reads image data sequentially recorded in the memory 200 and sequentially transfers the image data to the interface unit 500. That is, when image data for each channel is decoded by the image decoding unit 100, the image data is sequentially recorded in the memory 200, and the sequentially recorded image data is also sequentially read by the DMA 300. It is a method of transmitting to the unit 500.

Second, the memory 200 is divided into areas for each channel to record image data for each channel, and the DMA 300 reads the data for each area and transfers the data to the interface unit 500.

Third, a method of obtaining a natural scaling effect by selectively transmitting the image data recorded in the memory (200).

Since the first of the above methods is determined to be technically difficult for those skilled in the art, a detailed description thereof will be omitted. Therefore, in the following description, a method of simultaneously using the second and third methods will be described.

4 is a diagram illustrating an operation of storing image data of each channel decoded by each image decoder 100 in each memory area. The memory 200 is divided into regions according to respective channels, and the image data for each channel is recorded in the region of the predetermined memory in the following manner.

If each image data has a resolution of 640x480, one frame may be represented by a total of 480 lines in a line unit of 640 pixels. As shown in FIG. 5, a structure of a memory data map including the image data is formed, and image data of about 30 frames per second (30 fps) is processed per channel. do. In addition, according to an embodiment of the present invention, the digital signal processing 4-channel image processing chip may process up to about 120 fps.

5 is a view showing the operation of the controller unit.

As shown in FIG. 4, the image data of each channel stored in each area of the memory is transferred to the PCI interface 500 through one DMA 300 according to a command of the RISC processor 400. Deliver video data. The risk processor 400 also sets a status register 410 of the video signal decoder 100 to determine the mode of the video signal decoder 100, which mode scales. Information such as a video data format.

FIG. 6 is a diagram showing an operation in which the DMA 300 reads image data from each memory area in the 4-split screen mode. In particular, a method of obtaining a natural scaling effect by selectively reading image data is described. If the image data is not selectively read, the unscaled image data is read.

As shown in FIG. 6B, the DMA 300 reads 320 lines of a total of 640 pixels in the same manner as the first, third, fifth, ... in the memory line structure of 640 pixels. To form. As shown in Fig. 6A attached in this manner, the first line from the memory first area 201, the first line from the memory second area 202, the first line from the memory third area 203, and the fourth memory. Read the first line from area 204. After reading the first lines from the four memory regions, the second lines of each memory region are omitted, and the third lines are read in the same manner as when the first lines are read. As such, reading the image data of the memory has the effect of down scaling the image data of 640x480 resolution to the image data of 320x240 resolution. The reason for using this method is to avoid the various problems caused by the overload of the computer and the system when the amount of data increases due to the limitation of the data transfer rate of the PCI bus. have.

FIG. 7 illustrates how the DMA 300 displays the read data on the monitor screen. Devices such as the fisheye interface 500 and the fisheye bus between the DMA and the computer will not be considered for a while to aid understanding.

As shown in FIG. 7, line data read into the DMA 300 is sequentially displayed on each channel of the 4-split display screen. In other words, the line data read in the same manner as in Fig. 6 is sequentially divided into the channel 1, channel 2, channel 3, channel 4, channel 1, channel 2, channel 3, ... (omitted) of the display screen. This is how you can display them in order. This results in the first line 201 of the first region 201 Line1 data of the memory data map divided by the first line of channel 1 of the display screen, the second region 202 line1 data of the second region 202, ...), Line 3 data of the memory first area 201 to the second line of the channel 1, Line3 data of the memory second area 202 to the second line of the channel 2, ... (Omitted) ... results in displaying Line479 data in the memory third region 203 on the 240th line of the channel 3 and Line479 data in the memory fourth region 204 on the 240th line of the channel 4. The line data of each memory area is downscaled from 640 pixels to 320 pixels as described above. Therefore, the total resolution of the final four-segment display screen is 640x480, with a resolution per channel. Is 320x240.

8 is a block diagram showing a simple configuration of a multi-channel video capture system using a multi-channel image processing chip of the digital signal processing method of the present invention.

As described above, the image data stored in the memory 200 is transferred to the PCI interface unit 500 using the DMA 300, connected to the PCI bus slot of the computer, and connected to the PCI bus slot. Is passed on. The data transmitted to the computer is displayed on the monitor using a device driver and an application program. The above description is deemed to be well known to those skilled in the art, and thus a detailed description thereof will be omitted.

As described above, the multi-channel image processing system of the digital signal processing method of the present invention has a synchronization (synchronization) in a conventional multi-channel support method (i.e., a method of using one image processing decoder and an image input terminal switch). It is a fundamental solution to problems such as frame loss due to switch operation time and frame degradation due to channel distribution. In addition, in a multi-channel support method using multiple image processing chips and bridge chips, a single ASIC chip is configured to solve the problem of price increase and difficulty in access and implementation (affecting system stability). .

In addition, the 4-channel video capture system implemented by the above method is configured to support a 30fps for each channel and a video capture system that supports up to 4 channels 120fps, which is a computer built-in or embedded DVR ( Digital Video Recorder) can be applied. As a result, it is possible to solve the problem of unnaturalness of the video, price increase, and problems related to overall system stability due to frame deterioration, which may appear as in the conventional multi-channel support method that constituted the existing DVR (Digital Video Recorder) system. .

Claims (6)

delete delete delete A video signal decoding unit for receiving a composite video signal input from at least one channel and digitizing each of the channels according to each channel; A memory unit for storing processed image data through an image signal decoder for each channel; A controller unit which obtains and processes image data for each channel from a memory; In the multi-channel image processing system of the digital signal processing method for outputting the processed image data, comprising a bus interface unit for interfacing the controller unit and the computer, The controller unit, A DMA controller unit for reading the data recorded in the memory and transferring the data written to the bus interface unit; A digital signal processing type multi-channel image processing system, comprising: an image decoder unit, a memory unit, a DMA controller unit, and a risk processor unit for performing communication with a computer through a bus interface. The method of claim 4, wherein the DMA controller unit, In order to display a multi-channel image on a video display device without losing a frame according to a command of a risk processor using a single DMA, the multi-channel image data stored in a memory is sequentially read or A multi-channel image processing system of a digital signal processing method, wherein image data stored in a channel-specific region of a memory is selectively or non-selectively read and the image data of each channel is transferred to an interface unit. delete