KR100396698B1 - Structure of Flash Memory Device - Google Patents

Abstract

The present invention relates to a structure of a flash memory device for solving a poly bridge problem caused by a moat. The present invention relates to a plurality of bit lines arranged in parallel at regular intervals and at regular intervals perpendicular to the bit lines. A memory cell array comprising a plurality of word lines arranged in a memory cell array, the first active region being formed parallel to the bit line and below the bit line, and formed in the first active region where the bit line and the word line cross each other. A unit cell, a source region and a drain region that are alternately formed between the unit cell and the unit cell, and the source regions that are self-aligned to the source region along the word line and are adjacent in the word line direction An active source region and a region crossing the drain region in a word line direction; A device isolation layer formed in a portion to separate a drain region shared by a neighboring unit cell, and a bit line contact connected to a drain region separated by the device isolation layer simultaneously to connect two neighboring unit cells to the bit line. It is configured to include.

Description

Structure of Flash Memory Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a structure of a flash memory device for preventing a poly ribbon and a poly bridge phenomenon caused by a moat.

In general, a flash memory device is a nonvolatile memory device having a high erase speed because it can erase cells simultaneously.

In a flash memory cell, electrons in a floating gate are tunneled and erased by Fowler-Nordheim (FN) into a source region or a semiconductor substrate, or channel hot electrons are injected into a floating gate and programmed.

In the flash memory having an ETOX (EPROM Tunneling Oxide) structure, which is a typical structure of a flash memory, a self-aligned source method (SAS) is used to reduce a cell area.

This method, called the self-aligned source method, is formed by stacking a floating gate and a control gate in a stacked manner, after etching the stack gate, masking a portion of the stack gate to remove the field oxide film, and then ion implanting to form a source. We adopt process to make.

Hereinafter, a structure of a conventional flash memory device will be described with reference to the accompanying drawings.

1 is a layout diagram of a conventional flash memory, FIG. 2 is a unit cell configuration diagram of a conventional flash memory device, and FIGS. 3A to 3C are photographs photographing defects generated in a conventional flash memory. Is a gate contact.

First, referring to FIGS. 1 and 2, in a memory cell array including a plurality of bit lines 31 and word lines 32 formed at predetermined intervals, a bit line formed of the word line 32 and a metal layer may be formed. A unit cell A having a stack gate structure in which the floating gate 14 and the control gate 32 are stacked is formed in a region where 31 is perpendicular to each other. The two unit cells are connected to the bit line 31 by one bit line contact 20.

Referring to the structure of the unit cell A, a tunnel oxide layer 13 is formed between the floating gate 14 and the active region of the semiconductor substrate 11, and the control gate provided to the floating gate 14 and the word line ( An interlayer dielectric film 15 is formed between 32.

In addition, source / drain regions 16 and 17 are self-aligned to the stacked gate in the active region 12 of the semiconductor substrate 11. The floating gate 14 is formed over a portion of an edge of the active region 12 and the field region 21 on both sides of the active region 12 to be separated from the floating gate 14 of neighboring cells. The control gate 32 includes a floating gate 14 independently formed with the field region 21 interposed therebetween to form a word line by being connected to the control gate 32 of a neighboring cell.

Adjacent unit cells A are formed in opposite directions to share source / drain regions 16 and 17.

That is, since the active region 12 of FIG. 1 is formed in a '井' shape, the source and drain regions 16 and 17 of the unit cell A along the bit line active region 12a parallel to the bit line. Are respectively connected to the source and drain regions 16 and 17 of adjacent cells of the same row.

In addition, the source region 16 of the unit cell A is connected to the adjacent source regions 16 in the same column by the active source region 12b formed of an impurity diffusion layer parallel to the word line 32.

The bit line contact 20 is formed in the drain region 17 shared by two adjacent unit cells A, and the bit line contact 20 formed in the same row is a bit disposed perpendicular to the word line 32. Is electrically connected to line 31.

In addition, a source line contact 18 is formed in the source region 16, one for each of the plurality of bit lines 31.

Here, the field region 21 is mainly formed by a shallow trench isolation (STI) process, and a schematic method thereof is as follows.

First, after the pad oxide film is grown through thermal oxidation of the semiconductor substrate 11 and the nitride film is deposited, the nitride film and the pad oxide film are sequentially removed using a mask in which a trench pattern is formed, and the exposed semiconductor substrate 11 is etched to a predetermined depth. Thus, trenches are formed in the field region of the semiconductor substrate 11.

Subsequently, the semiconductor substrate 11 is thermally oxidized in order to clean the trench on which the trench is formed and to enhance the device isolation characteristics of the trench, thereby depositing a linear high temperature oxide (HTO) film.

Subsequently, an insulating film is deposited by a high density plasma (HDP) deposition process to completely fill and anneal the trench to densify the insulating film embedded in the trench.

The insulating layer is anisotropically dry-etched using a mask having a pattern opposite to that of the trench pattern to remove the insulating layer over the active region other than the trench region, that is, the upper portion of the nitride layer, and to clean the entire surface of the semiconductor substrate 11.

Subsequently, a planarization process is performed using the nitride film as an etch stop film to selectively remove the insulating film, and then the nitride film is removed to form the field region 21 by STI.

Here, due to the difference in physical properties of the pad oxide film, the HTO film, and the HDP film, the oxide film is etched little by little in a subsequent cleaning process, thereby causing a moat phenomenon as shown in the photograph of FIG. 3A.

Subsequently, a control gate 32 is formed and the self-aligned etching of the floating gate 14 is performed to form a stack gate. Residues are generated in a poly-etching process forming the floating gate 14. This is not a problem in the source region 16 where the field region 21 is etched later by the self-aligned source process, but in the drain region 17 the residue remains in the moat region. As shown in FIGS. 3B to 3C, a poly ribbon to a poly bridge phenomenon is generated.

Accordingly, the structure of the conventional flash memory device as described above has a problem in that a production yield decreases because poly ribbons or poly bridges are generated due to muting and shorted between unit cells.

Disclosure of Invention The present invention has been made to solve the above problems, and an object thereof is to provide a structure of a flash memory device suitable for improving the production yield of a device by preventing a poly ribbon and bridge phenomenon.

1 is a layout view of a conventional flash memory

2 is a unit cell diagram of a conventional flash memory device

3A to 3C are photographs showing defects occurring in a conventional flash memory.

4 is a layout view of a flash memory device according to an exemplary embodiment of the present invention.

5 is a unit cell configuration diagram of a flash memory device according to an embodiment of the present invention.

Explanation of symbols for the main parts of drawings

41: semiconductor substrate 42, 42a, 42b: active region

43 tunnel oxide film 44 floating gate

45: interlayer dielectric film 46: source region

47: drain region 49: gate contact

50: bit line contact 51, 51a: field area

52: bit line 53: word line, control gate

The structure of the flash memory device of the present invention for achieving the above object is a memory cell array consisting of a plurality of bit lines arranged in parallel at a predetermined interval, and a plurality of word lines arranged at regular intervals perpendicular to the bit line A first cell comprising a first active region parallel to the bit line and formed at a lower portion thereof, a unit cell formed in the first active region at a portion where the bit line and the word line cross each other, and between the unit cell and the unit cell. A source region and a drain region which are alternately formed in the active region, an active source region which is self-aligned to the source region along the word line, and connects the source regions adjacent in the word line direction, and in the word line direction; Adjacent unit cells formed in a portion including a region crossing the drain region Standing is separated to share the drain region that element separation films and, at the same time connected to the drain region are separated by the element separation films and the configured including the bit line contact for connecting the two unit cells adjacent to the bit line features.

Hereinafter, a structure of a flash memory device of the present invention will be described with reference to the accompanying drawings.

4 is a layout view of a flash memory device according to an exemplary embodiment of the present invention, and FIG. 5 is a unit cell configuration diagram of a flash memory device according to an exemplary embodiment of the present invention, wherein reference numeral 49 is a gate contact.

The flash memory device of the present invention is formed by separating the unit cells with an STI field oxide film in order to prevent the short circuit between the unit cells due to the poly ribbon or the poly bridge in the drain region. Referring to FIGS. .

In a memory cell array including a plurality of bit lines 52 and word lines 53 formed at regular intervals, the floating gate 44 and the control in an area where the bit lines 52 and the word lines 53 are orthogonal to each other. The unit cell B including the stacked gate in which the gates 53 are stacked is formed.

In the structure of the unit cell B, a tunnel oxide film 43 is formed between the floating gate 44 and the active region of the semiconductor substrate 41, and between the floating gate 44 and the control gate 53. An interlayer dielectric film 45 is formed. In addition, source / drain regions 46 and 47 are self-aligned to the stacked gate in the active region 42 of the semiconductor substrate 41. The floating gate 44 is formed over the active region 42a and the field regions 51 on both sides thereof, and the control gate 53 includes the floating gate 44 in a column direction adjacent to each other. Is connected to the control gate 53 of the word line.

In addition, the two neighboring unit cells B are connected to the bit line 52 by one bit line contact 50 as shown in part C, and the drain region 47 of the neighboring unit cell B is connected. Are separated from each other through the STI field oxide layer 51a under the bit line contact 50.

Adjacent unit cells B are formed in opposite directions to share the source region 46.

That is, as shown in 4, the source regions of the unit cells are connected to adjacent source regions of the same row along the active region 42a parallel to the bit line 52, respectively.

In addition, the source region of the unit cell B is connected to the source regions of adjacent cells in the same column by an active source region 42b formed of an impurity diffusion layer parallel to the word line 53.

In addition, source line contacts (not shown) are formed in the active source region 42b, one for each of the plurality of bit lines 52.

Herein, the distance between the active regions separated by the STI field oxide layer 51a, that is, the width W of the STI field oxide layer 51a is set to 0.1 to 0.2 µm, and the contact margin of the drain region 47 is improved. For example, the STI field oxide layer may be overetched by 30% or more when the bit line contact 50 is formed so that the bit line contact 50 is lowered by a predetermined depth from the surface of the semiconductor substrate 41. A contact is made to 51a and drain regions 47 on both sides thereof.

The structure of the flash memory device of the present invention as described above can improve the production yield by preventing the bridge between cells caused by poly residue, poly ribbon, etc. caused by the moat. It can be effective.

Claims (3)

A memory cell array comprising a plurality of bit lines arranged in parallel at a predetermined interval and a plurality of word lines arranged at regular intervals perpendicular to the bit lines. A first active region formed below and parallel to the bit line; A unit cell formed in the first active region where the bit line and the word line cross each other; A source region and a drain region that are alternately formed between the unit cell and the unit cell; An active source region self-aligned to the source region along the word line and connecting the source regions adjacent in the word line direction; An isolation layer formed in a portion including a region crossing the drain region in a word line direction and separating a drain region shared by a neighboring unit cell; And a bit line contact connected to a drain region separated by the device isolation layer and connecting two neighboring unit cells to the bit line. 2. The structure of a flash memory device according to claim 1, wherein the length of the device isolation film formed between adjacent drain regions in the bit line direction is 0.1 to 0.2 mu m. The structure of the flash memory device of claim 1, wherein the bit line contact is configured to contact the device isolation layer and a drain region adjacent to the device isolation layer at a point below a predetermined depth from a surface of the semiconductor substrate.