KR100396109B1 - Terabit per second atm packet switch having out-of-band control with multicasting - Google Patents

Abstract

The present invention relates to out-of-band for large-scale packet switches where the throughput is distributed to the partitions or pipes of the packet switch. Therefore, the out-of-band controller is divided into a plurality of pipe controllers. Since these pipe controllers operate in a ring connection, each pipe controller has a corresponding portion of the packet's input path request. The request is provided to up to three subsequent pipe controllers to hunt the path of packets waiting to be processed simultaneously and any requests not met by one pipe controller. By using up to four levels of parallelism, the controller can search for paths and establish connections for more than 256 ATM packet lines in a general monocast mode, thus providing more than 1 terabit / sec of throughput. The distributed controller design can thus make the overall switching speed very fast. This same generic distribution controller design can also provide a pipe search for a particular packet operation, referred to as multicasting, where one packet from one input line is transmitted to multiple or even entire output lines. As can be appreciated, multicasting can monopolize system assets and give solutions to other ATM packets, so that certain multicasting can be done primarily between specific packets during which multicasting packets can be carried. One such specific packet cycle may occur at system initialization.

Description

[0001] TERABIT PER SECOND ATM PACKET SWITCH HAVING OUT-OF-BAND CONTROL WITH MULTICASTING [0002]

The present invention relates to a large scale telecommunication switch that utilizes data packets to communicate at aggregate throughput at a level of 1 terabit / sec, and more specifically to a large telecommunication switch And the like.

Telecommunications has long used digital switching to encode, multiplex, transmit, and decode audio frequencies to deliver millions of telephone voice calls around the world. Telecommunication switches for voice calls have grown significantly in line with demand. Most switching systems that route and control voice call traffic are called circuit switches because for each call there is a type of bidirectional voice circuit that is set up between the calling party and the called party. . The established circuitry has the bandwidth and transmission timing necessary to simulate face-to-face conversations without undesirable distortion or time delay.

An alternative to circuit switching is packet switching. In packet switching, the caller is responsible for converting the information into one or more packets. This information may be an encoded voice, encoded computer data, or encoded video. Typically, the number of the called party is included in the packet header to forward the packet to its destination. The packet switching network is responsible for routing each packet to each destination without undue delay. Typically, the called party has equipment to receive the packet and decode the information back into the appropriate form.

Under the National Information Infrastructure initiative, the rapid growth of packet switching traffic, which transports voice, computer (LAN / WAN), facsimile, image and video data into increasingly widespread locations, challenges the packet switch protocol and system architecture .

Several vendors and service providers are involved in defining a global standard that allows packet switching services to be offered in a ubiquitous fashion at the same time. The result of such an integration effort is to have a stochastically-distributed arrival rate, such as the recent Asynchronous Transfer Mode (ATM) standard, as a means of efficiently routing and transporting data packets. The rapid development and utilization of ATM has brought about. Thus, ATM is a packet-oriented standard, but unlike most data packet predecessors (X.25, frame relay, etc.), ATM is a short fixed-length 53 byte packet . In addition, ATM utilizes a very streamlined form of error recovery and flow control as compared to packet forwarders. In fact, the ATM standard allows this functionality to be performed by higher-level protocols on the edge of the network, while eliminating most of the error protection and flow control at the link level. This approach minimizes network latency and jitter, allowing short cells to be routed quickly, making ATM compatible with voice, data and video services. Since ATM is used in the computer, LAN and WAN industries, seamless packet communication from a source computer is possible via LAN, WAN and public-switch network.

If this level of connectivity becomes available to the general user and similarly advanced broadband services that combine voice, broadband data and video are available at an affordable price, the scale of ATM traffic that can occur in the future is indeed unlimited . As a result, the number and size of switches and cross-connects needed to route these ATM packet traffic can grow at an alarming rate in the next decade. ATM switches and cross-connects for toll and gateway applications require 2.4 terabits per second (gigabits per second) at aggregate bandwidth of 155 gigabits per second (1000 inputs at SONET OC-3 155 megabit / sec) (1000 inputs at a SONET OC-48 2.4 gigabit / sec speed). In addition, if the demand for broadband services for home and / or LAN / WAN access over public switched networks increases as some experts believe, the local exchange carrier will have a 100 gigabit / sec (Ethernet 10 megabit / sec with a aggregate bandwidth ranging from 775 gigabits per second (SONET OC-3 155 megabit / sec transfer rate and 10% occupancy to 50,000 inputs) to 50,000 inputs at 50% Network: MAN) applications may require ATM switches and cross-connections.

Inevitably, most current structural research and hardware / software development for ATM switches is focused on switches with smaller aggregate bandwidth that meet market needs in the near future. For example, most proposals within the LAN / WAN community support aggregate bandwidths ranging from 150 megabits per second to 12 gigabits per second, and most proposals published within the telecommunications community include 20 gigabit / sec to 160 gigabits / sec. Extending these structures to a larger scale can result in enormous cost and size of the system, and / or due to limitations of the underlying techniques, such systems may be physically unrealizable.

For example, a very general design of a large scale high throughput switch is a multiple stage of switching nodes interconnected by a stage (link-end) of the link providing multiple paths between the input and output ports ). ≪ / RTI > The Clos, Banyan, and Benes networks are examples of such networks. A multi-stage network design can produce a network with very high levels of performance (low blocking probability, low latency, high fault tolerance) and can lower system-level costs, Because the resources (nodes and links) are time-share by a number of different paths that can be established within the network. However, physically realizing a multistage network for ATM has a problem due to a very short packet duration.

The design of any large, high-throughput ATM switching architecture should address two fundamental problems that have a significant impact on the overall performance of the final ATM switch. The first of these problems is cell loss due to blocking in the internal link of the distribution network (also known as switching structure), and the second problem is that there are two or more ATM cells passing the switch at the same instant in time There is a cell loss due to the contention of the output port. Typically, the first problem can be solved by designing the network with sufficient switching structures (nodes and links), so that multiple paths exist between the input and output ports. As a result, if two or more ATM cells are to use the same shared resource (node or link) within the switching structure, the cell will have two disjoint paths to eliminate the blocking problem of the internal network . The second problem is to allow the switch designer to recognize the technique for processing the cell.

A general design technique for a switch for operating a cell assigned to the same output port is described in Eng et al., Growth Packet Switch Architecture, IEEE Transactions on Communications (1992. 2), Yeh et al., The Knockout Switch, ISS AT & T Technical Papers (1987). This general design scheme segments the packet switch into two separate portions, as shown in FIG. Nx (FN) distribution network (with N input ports provided) and K m x n output packet modules (total M = Kn output ports provided). If it is required that each link originating from the distribution network be terminated at one of the inputs to the output packet module, it can be seen that the expression FN = Km must be satisfied. The switching structure is a memory-less Nx (FN) fanout switch in which a predetermined input of the M inputs on the output packet module connected to the desired output port of the cell To the ATM cell. The output packet module is an m x n switch with a buffer that can be used to store cells that must be delayed when two or more cells are contested at a particular output port. If the arriving traffic is evenly distributed across all output ports and the buffer in the output packet module is large enough, the ratio m: n is always large enough to make the cell loss probability within the network lower than the predetermined desired cell loss probability Can be selected. Indeed, when the network size N is large and R represents a switching load, the cell loss probability of a network with an m x n output packet module as described in Eng et al.

Since such a packet switch has an acceptable cell loss probability of about 10 ^-12 , a predetermined loss probability smaller than the existing device can be accommodated.

In an ATM packet switch in which all of the N cells arrive at the input of the distribution network at the same time in addition to the loss of the ATM cell due to an internal circuit contest, It must be processed by each end of the line. For example, if the incoming transmission line is a SONET OC-48. When supporting a bit rate of 2.5 gigabits per second, a group of N ATM cells arriving together must be processed and transmitted every 176 nsec (the duration of the ATM gel at 2.5 gigabit / sec link) at the next stage of the pipeline. Therefore, for a large value of N, a significant amount of processing power is needed to complete the path search operation for all N cells (where N = 256, a 1.45 x 10 ⁹ path search occurs every 684 psec Must be completed every second (sec) corresponding to the average processing speed of the path search of the first embodiment. Current commercial microprocessors can handle about 100,000,000 instructions / sec. If each path search takes only one instruction, at least 15 microprocessors will consume 100% of their processing time to perform these path searches. Therefore, a controller based on something other than a single MIO processor would be needed for a large ATM packet switch.

Two approaches to solving the problem of route retrieval can be planned. One approach uses an in-band scheme, i.e., a self-routing control scheme to perform a route search. Typically, the multistage network of Clos, Banyan and Benes networks described above utilizes in-band controllers and control techniques. In the in-band control scheme, the connection request remains pre-pended in the ATM data cell and is routed along the same path used by the next ATM payload through the switch. Typically, such an in-band control scheme replicates per node in the network in order to perform a localized path search operation (an operation limited to a cell passing through the node) when determining an access request and a method for routing the ATM cell It requires a parallel processing element to be distributed across all nodes in the network, generating relatively complex hardware to be. The second scheme uses an out-of-band controller and an out-of-band control scheme, so that the controller and switch structure are logically separated, and the connection request is input to the switch structure to set the final control signal path It must be routed to the controller that performs the path search before. This second scheme requires that the controller of the band has a very large amount of processing power (described above) due to the multiple path search operations that must be performed in a very short period of time.

Since the path search operation of the switch using the in-band control technique is based only on the localized traffic information and is not based on the global information related to all the switch traffic, Is not always optimal with respect to internal blocking. As a result, networks based on in-band control techniques often require more switch fabric (nodes and nodes) to provide the same operating characteristics as inexpensive switches based on out-of-band control techniques. Therefore, there is a need in the art for a packet switch controller that provides a global view of all paths to provide optimal optical path search to each packet.

For individual users, the path retrieved and used is from one input to one required output. For such a 1: 1 user, it is important to quickly and effectively find non-blocking paths for such packets. This behavior is known as multicasting because there is the ability for multiple users to use multiple outputs on one input, out of 1: 1 usage.

Multicasting is the ability to route a single input ATM cell to multiple output ports. Multicasting is an important feature for applications that require a single source for transmission to multiple destinations. Typical applications of this feature can be found in the distribution of video traffic from a video server within a CATV head-end office to any home synchronized to a particular television show. In addition, the feature of multicasting may be useful in distributing e-mail messages from a user using a single computer to a plurality of spatially distributed computers in a telecommunications environment. Although the protocols and signaling formats required for multicasting routing are not explicitly defined by the ATM standard, one very similar approach is to use all VPI / VCI addresses for all output ports To request a user to set up a connection. For multiple ATM switches based on self-routing control techniques, the selected switch design relates to an input line card for making multiple copies of arriving ATM cells to be multicast before injecting multiple copies of the cell into the network. This known design requires a relatively complicated addition to the hardware within the input line card, since a single input ATM cell may require transmission to all N output ports, so that each input line card has N copies of the ATM cells in the network To be injected. This places a heavy burden on the design of line cards. Therefore, it is desirable to have an ATM switch that provides multicasting without burdening the design of the line card. It is also desirable to have a distributed out-of-band controller that controls the ATM packet switch to provide multicasting of a single data cell for multiple outputs.

Briefly stated, in accordance with one aspect of the present invention, the above-described problem is solved by providing an ATM cell period storage function, a single stage, a reduced complexity switch structure, a band providing a transmission to a multiple output packet module to which a destination output line is attached Out-of-band controller for an ATM packet switch having an external controller and a line interface with an output packet module that provides a copy of the requested ATM cell to each destination output line attached thereto.

According to another aspect of the present invention, the above-mentioned problem is overcome by providing a controller in a packet switch for placing multiple paths for each multicasting telecommunication packet, And a memory for storing a busy-or-idle state of a connection of the mobile terminal. This memory is partitioned into a number of busy / out-of-call status tables, and these busy / busy stalls are simultaneously accessed to quickly locate the requested route for each multicast packet.

According to another aspect of the present invention, the above-mentioned problem is overcome by providing a controller in a packet switch having a switch structure having a plurality of pipes each having a plurality of crossbar switches. This controller is for placing a plurality of paths for multicasting telecommunication packets received on one of the plurality of input lines of the packet switch. The controller includes a plurality of pipe search controllers, each of which controls each pipe from a plurality of pipes. Each such pipe search controller has a plurality of crossbar switch controllers, and each crossbar switch of the pipe has a respective crossbar switch controller associated therewith. The controller also includes a storage for storing a busy / call suspended status table. Each bit of the busy / call suspended state table in the store is associated with a respective connection of each crossbar switch and stores a respective busy / busy stop bit for controlling this connection operation. Moreover, the controller simultaneously accesses each bit of the Busy / Busy State Table and multicasts the packet by requiring at least one path to at least one output packet module for the one or more output lines attached thereto. Therefore, the packet switching operation can be performed quickly and very effectively.

Figure 1 is a block diagram of a low-cost,

Figure 2 is a block diagram schematically showing again the switch of Figure 1;

Figure 3 is a block diagram of a growable packet switch in which the switch structure is divided into L multiple pipes according to the present invention;

Figure 4 is a block diagram similar to Figure 3 as a specific embodiment of the present invention having four pipes (L = 4) and showing the configuration for the pipes,

FIG. 5 is a simplified block diagram of the embodiment shown in FIG. 4 showing the controller in more detail;

6 shows the request timing procedure for the controller shown in Fig. 5, Fig.

Figure 7 is a simplified block diagram of an embodiment of an output module,

8 is a view showing an example of rolling and its operation in a plan view of an amusement park and its satellite parking lot;

FIG. 9 is a diagram showing calculated values of various ATM cell loss probabilities, with or without priority assignment,

Figure 10 is a simplified block diagram of an exemplary switch controller and its link controller,

11 is a detailed logic diagram of the link controller,

12 is a diagram showing the state table of the link controller shown in FIG. 11,

Figures 13A-13D illustrate the operation of the switch controller in combination with each other in response to a request procedure;

Figure 14 illustrates rolling of a route search request through a switch having four pipe controllers according to the present invention;

15 shows multiple paths taken to a destination output line of a multicasting cell;

DESCRIPTION OF THE REFERENCE NUMERALS

10, 10A: ATM switch 12 ₀ -12 _N-1 : Input interface

14, 14A: Switch structure 15 ₀ -15 ₆₃ : Crossbar switch

16 ₀ -16 _V-1 : Output module 17 ₀ -17 ₂₅₅ : Input line card

20: controller 24 ₀ -24 ₃ : pipe search controller

26 ₀ -26 ₆₃ : Switch controller 30 ₀ -30 ₃ : Switching network

Referring to Figure 2, a block diagram of a large scale switch 10 deployed for ATM communications is shown in block diagram form. The ATM switch 10 has a plurality of input interfaces 12 ₀ -12 _N-1 , a switch fabric 14 and buffered output modules 16 ₀ -16 _V-1 have. In an ATM operation, the input interfaces 12 ₀ -12 _N-1 are matched for matching the information received at the input to the multiple input ports of the switch fabric 14, network and power amplifiers. In addition, each of the input interface (12 ₀ -12 _N-1) needs the capability to store one ATM cell, as described below. Similarly, for ATM operation, the buffer output module 16 ₀ -16 _V-1 may be configured to reduce packet loss when two or more packets are sent and the same output line of the output (Out ₀ -Out _N-1 ) It is a concentrator that acts as a buffer.

Switch structure 14 is the fan-out (a fanout: F) in which each output is fanning out to F inputs within switch fabric 14 from the input interface (12 ₀ -12 _N-1) because it contains, ATM switch If switch 10 is an NxN switch, switch structure 14 will have FN outputs for FN internal input and output modules (16 ₀ -16 _V-1 ). The output module 16 ₀ -16 _V-1 has a fanin of F to convert the FN outputs of the switch structure 14 to the outputs of the N output modules Out ₀ -Out _N-1 , (concentration factor). Each output module (16 ₀ -16 _V-1 ) stores the ATM packets arriving in the FIFO queue and, when the output port is available, transfers the ATM packet preceding each of these FIFO queues to the requested output (Out _0- Out _N-1 ).

Switch structure 14 has a network switch, in particular a crossbar switch (crossbar switch) for providing a number of paths to the respective output port (19 ₀ -19 _FN-1) from each input port (17 ₀ -17 _N-1) It is a general distribution network that can be a network. However, it is not feasible to make an NxN switch rather than a single crossbar switch operating as a switching element of the switch structure 14 when the size of N exceeds 32. [ Therefore, some other scheme is required to realize the general architecture shown in Fig.

Referring to FIG. A possible ATM switch 10 is shown for N possible inputs (the size of N is at least 256). A number of paths are provided through the switch fabric 14 from each input port 17 ₀ -17 _N-1 to prevent blocking. These multiple paths are divided into groups called pipes, each having exactly one ( ₁ ) between each input port (17 ₀ -17 _N-1 ) in the network and each output port (19 ₀ -19 _FN-1 ) Lt; / RTI > Therefore, the switch structure 14 is composed of a plurality of pipes 18 _{0 -} 18 _L-1 . The output module (16 ₀ -16 _V-1 ) is essentially the same as the output module shown in FIG.

As can be seen in the co-pending application filed on December 12, 1995, entitled " TERABIT PER SECOND PACKET SWITCH ", which is hereby incorporated by reference, A single stage, memoryless, and a non-self routing network. A controller that hunts paths across all four pipes for each ATM cell, as switch structure 14 is not non-blocking, as in a full NxN crossbar switch 20). The actual purpose of the controller 20 is to find the unblocked path, since each pipe 18 _{0 -} 18 ₃ contains a path that can carry ATM cells.

For the ATM switch 10, if the number of input lines N is 256 and each input line operates at a standard 2.5 gigabit / sec data rate, its overall throughput can be 0.640 terabit / sec. Scaling or growing such an ATM switch to twice as many as 512 input and output lines is easy and the overall throughput is more than 1 terabit / sec. Increasing the ATM switch to a size of 1024 x 1024 has been considered in the prior art and it is believed that the architecture of the present invention will be further extended as the speed of commercially available devices increases and new faster speed techniques are developed .

Referring to Fig. 4, a specific embodiment of an ATM switch 10A is shown. In this particular embodiment, the ATM switch 10A has 256 input interfaces 12 ₀ -12 ₂₅₅ connected to 256 ATM input lines (In ₀ -In ₂₅₅ ). The output of the input interface is connected to the input port 17 ₀ -17 _N-1 of the switch fabric 14A. The switch structure 14A includes a total of sixteen 16x16 crossbar switches 15 ₀ -15 ₆₃ divided into four pipes 18 ₀ -18 ₃ . The fanout F is 4 and the number of output ports = FN or 1024 output ports (19 ₀ -19 ₁₀₂₃ ). The output ports (19 ₀ -19 ₁₀₂₃ ) are connected to the inputs of sixteen 64 × 16 output packet modules (16 ₀ -16 ₁₅ ), respectively. Sixteen 64x16 output packet modules are connected to 256 outputs (Out ₀ -Out ₂₅₅ ). It will be appreciated by those skilled in the art that other combinations of elements, for example 32 32x8 output modules, may be used instead of the 64x16 output module shown in FIG.

In addition, the ATM switch 10A includes a controller 20 that is responsible for retrieving the available pipes through the switch fabric 14A for each ATM packet. The controller 20 takes advantage of the fact that the switch structure 14A is divided into four pipes and divides the pipe search job into four parallel pipe search operations that are time-shifted by an acceptable amount, respectively. A detailed view of one embodiment of this controller 20 is shown in FIG.

In the above described N = 256 embodiment shown in Figures 4 and 5, with a throughput of 0.640 terabit / sec, the controller 20 may be included on about eight printed circuit boards. The controller 20 will receive up to 256 16-bit request vectors from up to 256 line input interfaces (12 ₀ -12 ₂₅₅ ), and retrieve a path search for each of these request vectors within 176 nsec Will do. An ATM cell interval is used to form a connection within the switch fabric 14A to generate 1024 16-bit connection vectors. This requires the controller 20 to operate at a processor clock speed of at least 46 megabits per second. This appropriate clock rate allows the logic in the controller 20 to be implemented in an off-the shelf CMOS EPLD device or similar device, making the use of the controller 20 (large scale) very reasonable.

Moving the request vectors from the input interfaces 12 ₀ -12 ₂₅₅ to the controller 20 and moving the connection vectors from the controller 20 to the crossbar switches 15 ₀ -15 ₆₃ of the switch structure 14A is simple This is because a large amount of control information must be transmitted every 176 nsec ATM cell period. For example, for an ATM switch that includes 256 input interfaces, 256 16-bit request vectors must be sent to the controller 20 every 176 ns, which is between the subsystem of the input interface and the subsystem of the controller 20 So that the total bandwidth is 23 gigabits / sec. In addition, 1024 16-bit connection vectors must be transmitted to the switch fabric 14A every 176 nsec to control the crossbar switches 15 _{0 -} 15 ₆₃ . This requires a total bandwidth of 93 gigabits per second between the subsystem of the controller 20 and the subsystem of the switch fabric 14A. These 93 gigabit / sec connection vector information can be compressed to 29 gigabits / sec (assuming that only one input can be routed to the output for each ATM cell period) by standard compression techniques. However, since such control information must be communicated with high reliability, all control connections or control links between these subsystems are duplicated (not shown in FIG. 4) and thus input interface cards There is actually 46 gigabits per second of data movement between the controller 20 and the switch 20 and 58 gigabits per second of data movement between the controller 20 and the switch structure 14A. Preferably, the high-speed serial link 22 will be used to transmit such control information. In this case, since the input interfaces 12 _{0 -} 12 ₂₅₅ are grouped into four interface groups, only 64 serial links are needed to move the request vector from the input interfaces 12 _{0 -} 12 ₂₅₅ to the controller 20 128 serial links would be needed to move the resulting connection vector from the controller 20 to the pipes 18 _{0 -} 18 ₃ (assuming that the data compression scheme described above is applied to the connection vector).

The use of out-of-band control techniques requires additional hardware costs of these high-speed serial control links 22, but these links 22 do not significantly increase the overall system hardware cost. The 256-input ATM switch 10A of FIGS. 4 and 5 needs 1024 high-speed serial links (4) to route the ATM cells between the input interfaces (12 ₀ -12 ₂₅₅ ) and the switch fabric 14A , And considering that 1024 higher-speed serial links are used to route ATM cells from the output (19 ₀ -19 ₁₀₂₃ ) of the switch fabric to the output packet modules (16 ₀ -16 ₁₅ ) . Therefore, adding 192 serial links 22 to route control information is to increase the total number of high-speed serial links in the system by only 9%.

Assuming that the connections of the inputs are symmetric and independent, as described in the pending application, EPC 95309013.1, filed December 12, 1995, entitled " TERABIT PER SECOND PACKET SWITCH & Knockout Switch ", the ATM cell loss probability of the ATM switch 10A shown in Figs. 4 and 5 is 4.34 x ^10-3 . This cell loss probability does not meet the acceptable ATM cell loss probability of less than 1x10 < ^-12 >

In order to reduce the probability of ATM cell loss, the controller 20 applies a temporal spreading technique known as a rolling technique (which provides many statistical advantages). The rolling technique includes and meets three basic goals that help provide a more evenly distributed traffic load. This goal is to (1) distribute traffic evenly spatially across all pipes 18 _{0 -} 18 ₃ so that one pipe only transmits proportional fractions to the traffic load, and (2) Distributes traffic evenly and spatially across all 16x16 crossbar switches (15 ₀ -15 ₆₃ ) in each pipe (18 ₀ -18 ₃ ) so that the crossbar switch is equally loaded, and (3) To distribute traffic arriving within a given ATM cell period for two ATM cell periods in a timely manner such that the traffic load is significantly reduced in a particular ATM cell period where there is a very large amount of traffic to be received. Thus, greatly reducing the traffic load is achieved by delaying some of the ATM cells arriving during a congested ATM cell period. The cell is delayed until the next succeeding ATM cell period where competing for a popular resource, i. E., Competing for connection to the preferred output packet module can be greatly reduced, so that the deferred cell is routed during the next ATM cell period Probability will be higher. Since the switch fabric 14A is memory-free, the ATM cells that must wait for the next ATM cell period are stored in their respective input interfaces 12 _{0 -} 125 ₂₅₅ .

In addition to satisfying these three basic goals of packet traffic control for distributing the load, the rolling scheme satisfies the goals of another two very important ATM systems. First, the goal (4) is that the order of the ATM cells is easily maintained when the ATM stream is reconfigured in the output packet modules (16 ₀ -16 ₁₅ ), even if the rolling scheme causes certain ATM cells in the stream to be delayed unlike others It is necessary to ensure that Secondly, the goal 5 would be that the controller 20 would attempt to route all ATM cells to each of the four output paths through the desired output packet module, but each successive path search attempt would result in a less loaded 16x16 The first path search attempt, which occurs at the crossbar switch, occurs within a 16x16 crossbar switch with many previously routed ATM cells (thus, the available path to the output packet module is very small) Is to ensure that the rolling technique must be guaranteed to occur within an effectively empty 16x16 crossbar switch (thus providing many available paths to the output packet module). Rolling schemes are similar to spatial path search techniques that pack as many call signals as possible in a fraction of the spatial network (compressing and storing them in less bits than the current data), which accounts for nearly 100% So that if the system utilization is less than 100%, the probability that the remaining calls are successfully routed through the remainder of the system becomes very high. Therefore, in the fourth final path search attempt, rolling increases the probability that an ATM cell is successfully routed to a very high degree. By packing a number of ATM cells in a portion of the network, the target 5 appears to collide apparently with target 1, which requires that traffic be spatially distributed through the network. However, as will be described later, the temporal spreading provided by the rolling technique allows the network to satisfy both objectives 1 and 5 at the same time.

Assuming that each of the 256 input ports 17 ₀ -17 _N-1 of Figure 4 has an ATM cell that needs to be routed through the distribution network and the switch structure 14A has four pipes 18 ₀ -18 ₃ , The out-of-band controller 20 may be required to perform 256 x 4 = 1024 eigen-path searches for the ATM cell before the cell is routed. In order to evenly distribute ATM cells (256 ATM cells requiring connection) to all four pipes, the rolling scheme divides the requests into four groups of equal size. The first group will perform a path search for that ATM cell first in pipe 18 ₀ , then in pipe 18 ₁ , then in pipe 18 ₂ , and finally in pipe 18 ₃ . The second group will perform a path search for that ATM cell first in pipe 18 ₁ , then in pipe 18 ₂ , then in pipe 18 ₃ , and finally in pipe 180. The third group will perform a path search for that ATM cell first in pipe 18 ₂ , then in pipe 18 ₃ , then in pipe 18 ₀ , and finally in pipe 18 ₁ . The fourth group will perform a path search for that ATM cell first in the pipe 18 ₃ , then in the pipe 18 ₀ , then in the pipe 18 ₁ , and finally in the pipe 18 ₂ . The ring-like ordering of this route lookup ensures that the ATM cell to be routed is evenly distributed over all four pipes. Also, if ATM cells within each of the four equal size groups are selected and ATM cells within a single group can be routed to exactly four of the 16 inputs on any 16x16 crossbar switch, then the ATM cells to be routed Will also be evenly distributed across all 16x16 crossbar switches.

Referring to Figures 5 and 6, a timing diagram for a rolling technique according to the present invention is shown. Out-of-band controller 20 uses the time delay / time distribution disclosed in goal 3 and uses the time delay / time distribution disclosed in goal 3 to satisfy target 1, target 2 and goal 5 simultaneously This ATM cell delay must be provided for each ATM cell period. In all cases, when the ATM cell group passes along the ring-shaped controller 20 structure from pipe 18 ₃ to pipe 18 ₀ , the controller 20 reassigns the cell to the next ATM cell period (period) , Which requires that the ATM cell be delayed by one cell period. Due to this reassignment and delay, each cell group will encounter a 16x16 crossbar switch that is much less loaded for the fourth final path search. Of the rolling technique such as this using a reallocation and delay of ATM cell period further advantage it is also 64 large any single output packet module ATM cells reaching through the switch structure (14A) at the same time (16 ₀ -16 ₁₅₎ than (Even if there are only 64 connections or links between switch fabric 14A and each output packet module 16 ₀ -16 ₁₅ ). This is because, in the rolling scheme, not all ATM cells need to be routed during the same ATM cell period. Therefore, if the rolling technique is used in the out-of-band controller 20, the probability of cell loss in both the switch fabric 14A and output modules 16 ₀ -16 ₁₅ is very low, even during transient cell periods with very high traffic loads .

One ATM cell cycle delays caused by certain ATM cells, which are typically routed through switch fabric 14A, will come to the conclusion that it is difficult to satisfy target 4, which requires to maintain the proper cell order. However, to ensure delayed in the ring-shaped path search order is always an ATM cell stream in the out-of-band controller 20 that the cell is routed through a pipe of non-delayed (non-delayed), a lower number than the cells (where pipe (18 ₀ ) Is the lowest numbered pipe, and pipe 18 ₃ is the highest numbered pipe. This information can be used to determine whether the cell is extracted from the switch structure 14A and the order from the lowest numbered pipe to the highest numbered pipe (pipes 18 ₀ , pipe (18 _1), the pipe (18 ₂₎ and the pipe (18 ₃₎₎ according to the output module (16 ₀ -16 ₁₅₎ first-in-first-out (first-in-first-out ) queue (174 ₀ in each of the output modules -174 ₆₃ (shown in FIG. 7), it is ensured that the proper cell order can be maintained.

7, the output module (16 ₀₎ (15 and the remaining output module (16 ₁ -16 ₁₅₎₎ are, jointly, the May 1995 assigned to the assignee of the present invention which is incorporated herein by reference Quot; ASYNCHRONOUS TRANSFER MODE SWITCH ARCHITECTURE ", such as Cyr et al., Which is incorporated herein by reference, may be a 64x16 embodiment of the concentrator disclosed in U.S. Patent No. 5,412,646 entitled " ASYNCHRONOUS TRANSFER MODE SWITCH ARCHITECTURE " An output module (16 ₀₎ of Fig. 7 is a specific example of the generalized concentrator shown in Figure 4 of the patent, such as previously referenced Cyr. The output modules 16 ₀ - 16 ₁₅ are well described in the above-mentioned patents, and are not described further herein for the sake of brevity.

In order to better understand the equations of the rolling technique, reference is made to a similar floor plan of the amusement park system 500 of FIG. 8 in real life. Consider the problem of using an electric train (tram) to transport people between two points in transporting many people from an amusement park (511,512,513,514) to an amusement park (520). The electric train system 530 consists of four motorized trains traveling along a predetermined route similar to the four pipes of the switch structure 14A. Each powered train includes 16 cars (representing a 16x16 crossbar switch in a particular pipe), and each roundabout has 16 seats (representing the output link from a single 16x16 crossbar switch). Similarly, each customer (representing an ATM cell) surrounds the amusement park 520 and reaches the parking lot of one of the four parking lots 511, 512, 513, 514. As a result, each customer is immediately placed in one of the four groups, and since the car parks 511-514 are the same size, each group on average accepts the same number of customers. At this time, customers in any single car park line up on one of the 16 lines, each of which is associated with each car in the amusement park roundtrip. The amusement park 520 is subdivided into 16 different theme areas (past land, future land, etc.), and each of the 16 seats belonging to a specific electric train car has a theme area in which the seat occupant The corresponding name is attached. Before reaching the parking lot, each customer should randomly select one of 16 themed areas (16 output packet modules (16 ₀ -16 ₁₅ )) they wish to spend the day in. The customer should then find available seats associated with the desired theme area on one of the four electric trains passing through the boarding area (531, 532, 533, 534) of the amusement park. If the customer does not find a seat available after the four electric trains have passed, the customer will not be able to enter the amusement park during that day (this exact condition is that all four pipes are blocked in the distribution network) Indicating a small but non-existent probability of loss of the ATM cell due to the loss of the ATM cell).

The first electric train, which stops in the passenger compartment where the customer can try, has already visited three different parking lot areas, so the customer's predetermined seat will probably be filled. However, if the customer finds that the desired seat is empty on the electric train, the electric train can immediately take the customer to the amusement park 520. [ If the customer fails to board the first electric train, the customer must wait for the second electric train which has already visited two different parking spaces. If the customer succeeds in finding his / her predetermined seat on the second electric train, the electric train stops at one other parking space and then takes the customer to the amusement park 520. If the customer fails to board the first and second electric trains, the customer must only visit one other parking lot and wait for the passing third electric train. If the customer succeeds in finding his / her seat on the third electric train, the electric train may stop at two additional parking spaces and take the customer to the amusement park 520. If the customer fails to board any of the first three electric trains, the customer must wait for the fourth final electric train. Fortunately, this electric train has not yet visited any parking lot, so the arriving electric train will be empty and the customer's seat will only be occupied if the other customer on the boarding line of the same parking lot as the customer wishes to occupy the same place . System 530 satisfies goal 5 since the continuously arriving electric train is much less loaded than the previous electric train. Therefore, the ATM cell rolling controller 20 can actually meet the target 1, the target 2 and the target 5.

When used alone, the rolling scheme improves the ATM cell loss probability of the ATM switch 10A from 4.34 x ^10-3 to about 10 ^-11 . Using the analytical technique described in the paper entitled " A Growable Packet Switch Architecture ", the bandwidth controller 20, which independently connects to the input of the switch structure 14 according to Galois field theory and uses the rolling technique, The cell loss probability of the ATM switch 10A provided with the ATM switch 10A can be analytically modeled and calculated. Pipes (18, ₀₎ in the 16 × 16 crossbar switch, each of Ra = R _L / 4 + to receive the same traffic load provided with Rres, where Rres is blocking the pipe (18 ₃₎ the pipe (18 ₀₎ for retry Lt; / RTI > is defined as the fraction of the 16 inputs to a 16x16 crossbar switch that is routed to a 16x16 crossbar switch. For the first attempt to solve the cell loss probability, let Rres = R _L / 16. Thus, the cell loss probability of a single 16x16 crossbar switch in pipe (18, ₀₎ can be determined using the expression of such Eng.

Here, m = 1, n = 1, and the switch load is given by Ra = _RL / 4 + _RL / 16. With this assignment, the final cell loss probability at a 16 x 16 crossbar switch of a fully loaded (R _L = 1.0) pipe 18 ₀ can be calculated as:

Therefore, the portion of the 16 inputs of the 16x16 crossroads delivered to the second pipe after the first attempt is provided by the following equation.

Symmetrically, This is also the same as the portion of the input transmitted from a pipe (18 ₃₎ the pipe (18, _0), the rest home of more than R _L /16=0.062 is incorrect. By making this second attempt by adjusting this assumption, we assume that Rres = R _L / 32. Therefore, the cell loss probability of a single 16 x 16 crossbar switch in pipe 18 ₀ can be determined again using an equation such as Eng, where m = 1, n = 1 and the switch load is Ra = R _L / 4 + R _L / 32. Using this quota, the final cell loss probability of the 16x16 crossbar switch of the fully loaded (R _L = 1.0) pipe 18 ₀ is calculated as:

Therefore, the portion of the 16 inputs of the 16x16 crossroads delivered to the second pipe after the first attempt is provided by the following equation.

The result of this calculation is very close to the assumed value of Rres = R _L /32=3.13x10 ^-2 , so that assumption can be considered satisfactory. The blocked cell is forwarded to the pipe 18 ₁ for subsequent path searching, which is a negligible number of ATM cells from previous attempts. Therefore, a 16 x 16 crossbar switch in pipe 18 ₁ can be modeled for analysis as an incremental packet switch, where m = 1, n = 1 and Ra = f1-2, The probability is 1.4x10 ^-21 . The portion of the sixteen inputs to the 16x16 crossbar switch in the pipe 18 _{1 that} is routed to the pipe 18 ₂ is 4.2 x 10 ^-4 . Using a similar method, the final cell loss probability for a cell entering the pipe 18 ₂ is 1.9 x 10 ^-4 , and the portion of the 16 inputs of the 16 x 16 crossbar delivered to the pipe 18 ₃ is 7.9 x 10 ^-8 . Pipe (18 ₃₎ the final ATM cell loss probability within is 3.7x10 ^-8, pipe (18 ₃₎ that is not routed within (and thus, are not routed in all four pipe attempts) 16 inputs to a 16x16 crossbar switch Is 2.9x10 < ^{-15 &} gt ;. Therefore, the use of the rolling techniques within the controller 20 of the band, ATM cell loss probability of the switch fabric (14A) the ATM switch (10A) connected independently to an input of 2.9x10 is in an unacceptable value of 1.47x10 ^{-6 Lt} ; RTI ID = 0.0 > ^-15 . &^Lt; / RTI >

A preferred technique can be used in conjunction with the rolling techniques described above to further reduce the cell loss probability of the ATM switch 10A. Referring back to the amusement park analogy of FIG. 8, if more than one customer requires the same seat, a certain type of arbitration is required at the boarding area of the electric train to determine which customer will be provided with a particular seat . Likewise, the out-of-band controller 20 should provide an arbitration scheme for selecting which of the arriving ATM cells to assign that particular link whenever two or more cells request access to the same link do. The arbitration scheme used may have a favorable effect on the TM cell loss probability.

One possible arbitration scheme is to randomly determine which cell of an ATM cell is assigned to a link. The random selection scheme is an assumed scheme for the analysis of the rolling technique described above. However, other interventions are possible and one particular intervention that produces the desired outcome is referred to as a preference scheme. First, the arbitration scheme allocates a weight to each ATM cell in a specific group. When two or more cells request access to the same link, an ATM cell with a higher priority weight always precedes an ATM cell with a lower priority weight. As a result, a valid layer is created between the groups of ATM cells.

Since a customer with a higher priority weighting will be better served than a customer with a lower priority weighting, the creation of a hierarchy may seem to create an apparently undesirable characteristic. Indeed, one customer with the highest priority weight in each group never ever blocks his ATM cell from being blocked by another customer's ATM cell. Although this may seem unreasonable, a detailed analysis of the effects caused by this hierarchy shows that in fact all customers (even those at the lowest part of the hierarchy with the lowest priority weight) have improved performance, You can see that it is imported.

The results of this analysis are summarized in FIG. 9, where the probability of an ATM cell loss, i. E. The probability of a cell not being allocated an available path, is shown as a function of the number of path searches that are attempted in the various pipes by the out- have. In this analysis, the group size is four, that is, up to four ATM cells can simultaneously compete for access to the same link. As a result, four different priority weights are assigned to form a hierarchical scheme for the four input ports associated with each group. The priority weight associated with a particular input port is assumed to be a fixed constant that does not change over time. The results charts 901, 902, 903 and 904 of FIG. 9 show that as more path searches are performed in more pipes, the cell loss probability is reduced, but the inputs with lower priority weights 903 and 904 Has a higher cell loss probability than the input with higher priority weights (901, 902). A similar chart 910 showing the probability of being unserved when a random selection arbitration scheme is used instead of a hierarchical arbitration scheme is overlaid on the preceding charts. Surprisingly and unexpectedly, after path lookups are attempted on four different pipes, the random-selection arbitration scheme results in a higher cell loss probability than the average of the cell loss probability of the hierarchical arbitration scheme. Indeed, the chart of randomized arbitration schemes 910 shows that for all input ports, averages significantly higher than the charts 903 and 904 for the average cell loss probability for the input port even with the lowest priority weighting in the hierarchical arbitration scheme Cell loss probability is shown. This phenomenon is due to the fact that the distribution of ATM cell requests entering the fourth pipe after three sets of route discovery in three different pipes is very different depending on whether a random arbitration scheme will be used or a priority arbitration scheme will be used Lt; / RTI > In the random selection arbitration scheme, there is a small but equally likely probability that all ATM cells require one path. However, in a layered arbitration scheme, most ATM cells with higher priority weights will actually require one path with a probability of zero, but certain ATM cells have been denied access to the link in all three previous path search attempts , An ATM cell with the lowest priority weighting may require one path with a significant probability. However, since a single request can always be satisfied because there is no competition for the output link in a single request, a single request arriving with a high probability of reaching the fourth final path search in the controller is less than a number of requests arriving with a low probability Make ATM more routed.

As a result, by using a hierarchical arbitration method to assign priority weights to input ports and solve link-line contention and routing paths in the out-of-band controller, the worst cell loss probability of switch structure 14A is the introduction of rolling techniques from 2.9x10 ^-15 that is achieved by that the same may be reduced to a lower value of 2.4x10 ^-16 becomes clear from the chart of FIG. It is not so important that the input port to which a higher priority weight is assigned has a much lower cell loss probability as shown in FIG.

Referring again to Figure 5, in order to provide a physical embodiment of the rolling and prioritization method, the ATM switch 10A is divided into four basic subsystems. These four subgroups are comprised of input interfaces 12 _{0 -} 12 ₂₅₅ , output modules 16 ₀ - 16 ₁₅ , switch structure _{14 A} and out-of-band controller 20.

The input interfaces (12 ₀ -12 ₂₅₅ ) in the network provide the necessary interface between the incoming transmission link and the link connected to the switch fabric 14A and the out-of-band controller 20. As a result, the input interface (12 ₀ -12 ₂₅₅₎ shall provide a terminal end (termination) on the input transmission line. For example, if the incoming transmit line is a SONET link, the incoming interface may be used for clock recovery, link error detection, SONET pointer handling and delineation, and for system clocks within the ATM cell extraction and distribution network Synchronizing ATM cells should provide a resilient storage function. The extracted ATM cell is loaded into the FIFO buffer of the input interface. In addition, the input interface must read the ATM cell from the FIFO buffer and extract the ATM header from the cell. The VPI / VCI field of each ATM header is used as an address for a translation table placed in the input interface. The output of the translation table provides the new VPI / VCI field and the address of the output packet module to which the ATM cell is to be routed. The new VPI / VCI field is written into the ATM cell as a replacement for the old VPI / VCI field. The output module address is routed to the out-of-band controller 20 as a request vector to the switch fabric 14A. Since the processing time required by the out-of-band controller 20 is a fixed value, the input interface is only used until the out-of-band controller 20 completes the route search and relays the result into the switch structure 14A The ATM cell is held in the buffer. Once the switch fabric 14A is loaded with the new switch configuration to properly route the ATM cell, the input interface can inject the ATM cell into the switch fabric 14A, (16 ₀ -16 ₁₅ ). It should be noted that each of the input interfaces 12 _{0 -} 12 ₂₅₅ has one link for each of the four pipes 18 _{0 -} 18 ₃ of the switch fabric 14A. In addition, using a rolling scheme (i.e., a temporal spreading scheme) within switch structure 14A may require that a copy of the ATM cell be injected into each of the four links for any one of two consecutive ATM cell periods have. As a result, the timing in the input interface (12 ₀ -12 ₂₅₅ ) must be tightly coupled and synchronized with the timing of the remaining subsystems in the ATM switch 10A.

Each of the 256 input interfaces 12 _{0 to} 12 ₂₅₅ of Figure 5 is numbered to an address ranging from 0 to 255 and each input interface is also an alias given as a character between A and P, Address is assigned. This alias address may be used to identify which input port in the switch fabric 14A the input interface is to be connected to. The actual set of four crossbar switches to which a particular input interface is connected is determined by the previously described Galois field technique. This technique ensures independence between all inputs on any 16x16 crossbar switch of any pipe.

In FIG. 5, each of the sixteen output modules 16 ₀ -16 ₁₅ is labeled with an address ranging from AA to PP, and each output module performs an important function within the ATM switch 10A. Each of the output modules 16 ₀ -16 _{15 in} FIG. 5 provides termination for a set of 64 links out of the switch fabric 14A. In addition, each of the output modules 16 _{0 to} 16 ₁₅ provides two basic functions, and each ATM cell arriving through one of the 64 inputs is connected to one of 16 output ports It provides small space switching for routing and provides ATM cell buffering to address the problems associated with multiple packets being sent simultaneously to the same output (Out _{0 -} Out ₂₅₅ ).

There are several ways in which these two functions can be implemented. Most direct methods will usually configure a shared memory switch capable of reading 64 memories and 16 memories in the ATM cell period (176 nsec). At this time, the memory may be processed as a disjoint connection list (one list for each output (Out ₀ -Out ₂₅₅ )) along with a seventeenth connection list containing the idle memory locations. Although simple, this approach will require eight memory accesses every 176 nsec, thus requiring a memory with an access time of 2.2 nsec. Another way is to divide each 64x16 output module (16 ₀ -16 ₁₅ ) into a 64x16 concentrator and a 16x16 shared memory switch. A concentrator may be a memory system that provides 64 memory writes and 16 memory reads per ATM cell period, but the memory speed may be low because these memories do not provide the required buffering due to output line contention problems And the memory speed may be high). In addition, a 64x16 concentrator can be implemented as a single linked list spread across 64 separate memory chips. As a result, each memory chip will require only one write and 16 reads per ATM cell period. Since a 16x16 shared memory switch only performs 32 memory accesses per ATM cell period, low-speed (and large) memory can be used, and buffering for the output line contention problem is provided in this shared memory portion of the output module . Therefore, this last device is another more practical device for the output module.

The switch structure 14A is essentially a small circuit switch group that provides the required connection between the input interface and the output module in response to a control signal generated by the out-of-band controller 20. [ In the embodiment of the ATM switch 10A shown in Fig. 5, the switch structure 14A is made up of 64 16x16 crossbar switches, the disjoint group of 16 switches constituting one pipe. The four pipes are named pipe 18 ₀ , pipe 18 ₁ , pipe 18 ₂ and pipe 18 ₃ and the 16 16x16 crossbar switches in a given pipe have the names of switches 0-15 Respectively. The crossbar switch should be able to receive the control signal generated by the out-of-band controller 20 and reconfigure all switch settings during the guard-band period between consecutive ATM cells. Each 16x16 crossbar switch supports 16 inputs named from input (A) to input (P), and each 16x16 crossbar switch also supports 16 outputs, labeled from output (AA) to output (PP) . Each of the input interface comprises four pipes (18 ₀ -18 _3), but that the connection to a different 16x16 crossbar switch in each of the inside is already pointed out, the pipe (18, ₀₎ in the input (X) (X is the set {A , B, ..., P) is required to be connected to the input X in the other three pipes 18 _{1 -} 18 ₃ as well. An input interface in the switch structure _{(14A) (12 0 -12 255} ) and the actual connection between the crossbar switch is determined using the aforementioned Galois field theory techniques. This technique ensures independence between the input ports for routing within the switches of each pipe of switch structure 14A. 5 also shows one of the 64 inputs for a 64x16 output module labeled YY (YY is the element of set {AA, BB, ..., PP}) from each of the 64 crossbar switches Lt; / RTI >

The basic function of the out-of-band controller 20 for the switch structure 14A is to determine which of the four pipes 18 _{0 -} 18 ₃ a particular ATM cell can be routed through. Once the out-of-band controller 20 successfully determines the pipe to be routed without the ATM cell being blocked, the task of setting the path through that pipe is a simple matter, Since there can be only one path between the input port of the ATM cell and the required output module. As a result, the basic route search operation of the switching network is actually reduced to a simpler pipe search operation in the ATM switch 10A.

The controller 20 of the band is 16x16 crossbar switches and the output modules (16 ₀ -16 ₁₅₎ the intermediate (FN) links the still state jungyimyeo call unavailable state or a call for each of between the switch fabric (14A) is available / RTI >< RTI ID = 0.0 > calls / out-of-call < / RTI > However, such a large busy / busy stop table can be subdivided into small / busy stalls that the controller 20 can access in parallel so that many pipe searching operations can be performed in parallel. There are many ways to implement the controller 20 for a large scale switch with a general growable packet switch architecture. In extreme cases, four levels of parallelism may be applied to the architecture of the controller 20 to perform pipe searches. One embodiment will first be described in detail using three levels of parallelism, and then the fourth level of parallelism will be discussed.

The first level of parallelism is obtained by providing respective pipe search controllers 24 _{0 -} 24 _{3 for} each of the four pipes 18 _{0 -} 18 ₃ . This level of parallelism allows pipe searches to be performed simultaneously across all four pipe search controllers 24 _{0 -} 24 ₃ . The second level of parallelism can be obtained by providing switch controllers 26 ₀ -26 ₆₃ , where there are 16 switch controllers in each of the pipe search controllers 24 _{0 -} 24 ₃ . The unique switch controllers 26 ₀ -263 ₆₃ are associated with respective 16x16 switches within each pipe of switch structure 14A. As a result, the pipe search operation can be performed in parallel within a total of 16 switch controllers of each pipe search controller 24 _{0 -} 24 ₃ . The third level of parallelism is obtained by causing each switch controller 26 ₀ -26 ₆₃ to perform parallel processing on a total of 16 output links attached to each 16x16 crossbar switch. Preferably, each switch controller (26 ₀ -26 ₆₃ ) reads in parallel the 16 call / call stop bits from the busy / call stop memory, performs a parallel pipe search operation based on these 16 bits , And writes the 16 resultant call / call stop bits in parallel with the other call / stop memory for each call / call stop memory. A representative switch controller (26 ₀₎ of the switch controller 64 (26 ₀ -26 ₂₃₎ is shown in FIG. Simultaneous processing of the 16 call / talk stop bits is achieved by providing 16 unique link controllers (AA-PP) to the switch controller 26 ₀ , and each link controller (AA-PP) / RTI > of the intermediate link between the portion of the intermediate link and the respective output module. In the embodiment shown in FIG. 10, the large busy / call pause memory required to control the switch 10A is divided into a number of single bit memories, talk / call stop flip-flops, The medium / busy memory is logically and physically related to each link controller (AA-PP).

A typical data flow for the request vector generated by the input interface (12 _{0 -} 12 ₂₅₅ ) is shown in FIG. For example, Figure 5 an input interface (12, ₀₎ is connected (21, ₀₎ to route the request vector to pipe search controller (20 _0), and the pipe searching ring (i.e., controller 20) in the pipe search controller via the And the rolling plan requires that the request vector be cycled through the pipe search controller 24 ₁ , the pipe search controller 24 ₂ and the pipe search controller 24 _{3 as it} rotates along the ring . In general, each input interface 12 _{0 -} 12 ₂₅₅ generates a request vector, and each request vector will contain a number of bits equal to the number of output modules in the system. Therefore, the request vector from the single input interface of FIG. 5 is a 16-bit data word, where each vector of the request vector specifies one of 16 output modules. If an ATM cell in the input interface requires a connection to the output port on the i-th output module, then bit i in the request vector is set to logic "1" and all other bits in the other request vector are set to logic "0" will be. When the controller 20 receives this particular request vector from the input interface, it can recognize that a path is required between the source input interface and the i-th output module.

The entire 16 bit request vector from the input interface is routed to the four pipe search controllers 24 _{0 through} 24 ₃ via respective control connections 21 _{0 through} 21 ₂₅₅ and the controller 20 sends Forks the vector to one of the 16 switch controllers associated with the switch. As shown in Fig. 10, a 16-bit request vector is injected into the switch controller and distributed to all 16 link controllers in that particular switch controller. Each link controller is associated with a single link between the crossbar switch and the output module, and actually processes one bit of the 16-bit request vector. A finite state machine circuit associated with a single link controller comprises a single flip-flop (a single bit memory required to store the busy / call stop bits associated with the link of this link controller) and four logic gates do. A state table describing the link controller operation is shown in FIG. 12, where the state variable is defined as busy / call stop bits. The link controller hardware provides one request vector input bit, indicated as request-in, one request vector output bit, indicated as request-out, and one connection vector output bit, indicated as a connection. The request vector input bit is a logical " 1 " if the input requires a connection via a link associated with this link controller, otherwise it is a logical " 0 ". The request vector output bit is a logical " 1 " if the logical " 1 " input request vector bit is not satisfied by this particular link controller, and a logical " 0 " The connection vector output bit is a logical " 1 " if the logical " 1 " input request vector bit is satisfied by this particular link controller (which allows the ATM cell to be routed through the link associated with this link controller to the required output module , Otherwise it is a logic " 0 ". 10 is reset to a logical " 0 " (stop) state at the beginning of each ATM cell slot, the first request vector bit, which is provided to the link controller with a logical " (The logical " 1 " connection vector bit and the logical " 0 " output request vector bit) to the logical " 1 " (busy) state during busy / call stop flip-flop. Any subsequent request vector bits provided to the link controller during this particular ATM cell slot will be denied access over this link (such that the connection vector bit is a logical " 0 " output and the same output request vector Bit). A time-lapsed view of a number of contiguous 16-bit 'monocast' request vectors passing through a single switch controller, along with the resulting state of busy / call stop bits stored in the switch controller 13. The resulting output request vector and output connection vector describe the general operation of each pipe search controller 24 _{0 -} 24 ₃ .

Using the rolling technique within the controller 20 requires a very precise temporal ranking for two basic events: poking and busy / flip-flop flip-flops. The timing diagram of Figure 13 illustrates the synchronization of data flows that may be used for logic within the controller 20. [ As indicated by the timing diagrams, the data flow along the ring of the controller 20 begins at the pipe controller 240, passes through the pipe controller 24 ₁ , the pipe controller 24 ₂ , the pipe controller 24 ₃ again And flows to the pipe controller 24 ₀ . The request vector generated by the input interface having the alias addresses A, B, C, D is forked to the pipe controller 24 ₀ . The request vector generated by the input interface with the alias address (I, J, K, L) is forked to the pipe controller 24 ₂ . The request vector generated by the input interface having the alias address (M, N, O, P) is forked to the pipe controller 24 ₃ . Foaming time and busy / call stop bit clear times occur at different times within each pipe search controller 24 _{0 -} 24 ₃ . From any pipe controller point of view, the request vector bit flows alphabetically (A to P) through the pipe controller when ignoring busy / call stop bit clear time. Since the request vector generated at the input interface with the alias address A will always precede the request vector generated at the input interface with the alias address (B, C, D, etc.) Thereby ensuring that the advantages can be realized within the controller 20.

The advantage caused by the independence given between the inputs of a particular 16x16 crossbar switch is to slightly increase the complexity of the pipe search circuit. Due to the independent connection between the independent input interface and switch structure 14A using the Galois field theory, the request vector from a single input interface must be routed appropriately to several different switch controllers at each end of the pipe search ring. Mixing in the Galois field theory generated connections (mixing nature) is required to be so connected to a different set of 16x16 crossbar switches within the switch fabric (14A) each of the input interface (12 ₀ -12 _255), as a result, and Require that the request vectors generated on different input interfaces be routed through a different set of switch controllers in the controller 20. Since the request vector is time multiplexed on the link within the controller 20, all request vectors (in a particular ATM cell slot) coming from a particular switch controller in one pipe search term should be routed to a different switch controller in the next pipe search stage By definition). Each of the pipe search controllers 24 ₀ , 24 ₁ , 24 ₂ and 24 _{3 is} connected to the small-scale switching networks 30 ₀ , 30 ₁ , 30 ₂ and 30 ₃ shown in FIG. 5 to provide this dynamic routing of the request vector. Respectively. Alternatively, a simple multiplexer may be used in place of the switching networks 30 ₀ , 30 ₁ , 30 ₂ , and 30 ₃ , thereby greatly reducing the cost of the controller 20. Fortunately, the preferred structure of these small switching networks 30 ₀ , 30 ₁ , 30 ₂ , and 30 ₃ (or multiplexers) is a structure that cycles back to the same period as the ATM cell period, Quot; hard-code " to a small-scale switching network (multiplexer) during the circuit design of the circuit.

As described above, the ATM switch 10A shown in Fig. 5 can be extended to a number of input lines of 512, 1024 or even larger. For a switch of this size, assuming that the input line carries a data rate of 2.5 gigabit / sec, the total throughput will be 1.0 terabit / sec or more. For switches of this size, a fourth level of parallelism may be needed to provide sufficient processing power to allow controller 20 to search all paths through all the pipes. For an ATM switch with 512 and 1024 input lines, the data transfer rate on the wire in each controller is 204 megabit / sec, which is significantly higher than the 113 megabit / sec transfer rate of the 256 input line version of ATM switch 14A. sec and 386 megabit / sec.

The basic idea behind the fourth level of parallelism is to modify the design of the controller 20 described above to require that the request vector be routed in parallel through the pipe search end. In particular, all request vectors forked to a particular pipe are routed together through a pipe search stage, which is said to form a fork group. In the embodiment shown in FIG. 5, this method for designing the controller 20 generates four groups of forks of a 16-bit request vector, so each fork group contains 64 bits. The four fork groups can be named by concatenating the four alias names on the request vector. As a result, the four fork groups of the redesigned pipe browser of FIG. 5 are ABCD, EFGH, IJKL, and MNOP. Each time a single 64-bit ABCD fork group is routed through one of the switch controllers in the pipe controller of FIG. 5, the 64-bit ABCD fork group is also routed through each of the other fifteen switch controllers in the pipe controller 240 It is important to note. As a result, a total of 1024 request vector bits associated with 16 ABCD fork groups are routed through the pipe 18 ₀ at a single point in time. The modified controller 20 processes the request vector for all N input ports every eight clock cycles (by passing through all four pipe search controllers 24 _{0 -} 24 ₃ ), and this operation is a single 176 nsec The required clock rate in the controller 20 is 46 megabits per second, regardless of the size (overall throughput) of the NxN ATM switch. As a result, since the controller 20 has to perform eight processing steps (irrespective of the network size), the processing is referred to as a route search algorithm of 0 (1). During the execution of the 0 (1) path search algorithm for the N = 256 input ATM switch 10A of FIG. 5, an equivalent 16,384 link controller path search and a 16,384 link controller path search check are performed every 176 nsec, Controller 20 is considered to be a parallel processor capable of supporting a processing speed of 186 giga instructions per second if it is considered that this instruction is executed and each path search check is regarded as instruction execution. The trade-off to maintain the proper transmission rate of the controller 20 (regardless of size) is to increase the logic complexity of the link controller and increase the signal connection through the continuous stages of the controller as the size increases to be. The design of an ATM switch with an overall throughput greater than 1 terabit / sec will require that signals between 4096 and 32,768 (46 megabit / sec) be routed between consecutive pipe controller stages.

In addition to increasing the number of signals between the pipe controller stages, the use of parallelism in the controller 20 requires slightly increasing the hardware requirements for each link controller, since each link controller has four bits in the fork group Because it must support parallel path search for The extra hardware added to the controller 20 by the fourth level of parallelism is canceled by lowering the processing speed.

Multicasting operation

The output packet module has a substantially equivalent complexity to the distribution network and the distribution controller due to the functionality within them. For example, each output packet module should provide the functionality of a concentrator that requires multiple FIFO-like memories, and the access speed to these required memories is directly proportional to the number of inputs and outputs of the concentrator. In addition, each output packet module must provide a large shared buffer memory to accommodate packets that are temporarily blocked from the required output port. The access speed to these required buffer memories is proportional to the number of outputs from the output packet module. In addition, the output packet module must provide a means for delivering the received packet in the correct time sequence to the desired output port. Moreover, each output packet module must provide the ability to multicast cells between its inputs and outputs, forming multiple copies of multicasting cells, injecting a new VPI / VCI field into each multicasting cell , And route them appropriately. As these feature sets are provided, it is clear that the larger the output packet module is, the more difficult and costly it will be to provide all of these functions. Therefore, a trade-off technique that reduces the size of the required output packet module may be highly desirable.

In the system shown in Figure 5, each output packet module is designed to support 64 input links and 16 output links. Since each output packet module must have exactly one link routed from each crossbar switch in the distribution network 14A to the module, its size is directly related to the number of crossbar switches used in the distribution network 14A . The number of outputs from the output packet module is always 1 / F of the number of inputs to the output packet module, where F is the fanout provided by the distribution network 14A. In the distribution network shown in FIG. 5, the fanout (F) is four.

The ATM switch architecture of the present invention, which is based on out-of-band control techniques, makes it possible to use global information related to the state of the switch fabric 14A in various ways. Likewise, the way that the arrival path of an ATM cell is quickly routed within a pipe browser section is likely to be very difficult with an architecture based on in-band / self-routing control techniques, Lt; / RTI > Multicasting is one of these features.

Multicasting is defined as the ability of an ATM switch to route a single input ATM cell to multiple output ports for ATM. Multicasting is an important feature in applications that require a single source to transmit to multiple destinations. Typical applications for this feature include distributing video traffic tailored to a particular television show from the video provider within the CATV headend to all homes. This multicasting characteristic may also be useful in distributing e-mail messages to users using a single computer in a telecommuting environment and users using multiple computers spatially distributed. Although the protocol and signal format required for multicasting routing have not been explicitly defined by the ATM standards committee, the future ATM protocol uses a specific VPI / VCI address indicating the connection list including the entire output port required for the user To set up a connection to all output ports.

Referring to Figure 15, multicasting in accordance with the present invention is shown. Multicasting jobs are separated into two parts, a distribution network (14A) is the output packet module (16 ₀ -16 ₁₅₎ between the service and multicasting, each output packet module (16 ₀ -16 ₁₅₎ is the input, and Provides multicasting between the output ports. As a result, the output packet modules 16 ₀ - 16 ₁₅ (which can perform multicasting using cell copying techniques) need to make only a few copies of the ATM cell reaching one of the inputs. The distribution network 14A can easily provide a multicasting function between any input line card (17 ₀ -17 ₂₅₅ ) and each output packet module associated with multicasting. 15 is showing an ATM cell of a multi-cast to the line card (17 ₀₎ output line output packet module for (0,1,120,240) (16 _0, 16 _7, 16 ₁₅₎ from. If the request vector generated by the line card has more than one bit set to logic " 1 ", pipe finder 20 automatically (without requiring any change to the hardware described above) You will try to route to the module. ATM cell is simply because the line card (17 ₀₎ to flow through the distribution network (14A) through a number of paths from one or more, there is no need at all copying of the cell by the line card. When it comes to the output packet module (16 ₀ -16 ₁₅₎ is required for the multi-cast in the output packet modules as shown in the output packet module (16, ₀₎ in Figure 15, the output packet module receiving buffer for delivery to the output lines And must access the stored cell several times to operate the output packet module during multicasting. The ATM switch 10A can multicast ATM cells in the absence of extra hardware.

Multicasting, which allows one packet from one input line or a group of input lines from a group of input lines to be delivered to all or nearly the entire output line of the output packet module 16 ₀ - 16 ₁₅ , ≪ / RTI > 10A) is not controlled by the input limit, it can have a very significant effect on the cell loss probability. Such input limitations are understood in the art not to be a part of the present invention and are not shown in the drawings. If one input cell utilizes all the output lines for one cell period, then there must be some traffic remaining on the other input line for that cell period and then the next cell period. The simulation shows a switch 10A with a very low cell loss probability for non-multicast ATM cell traffic. For the fully loaded switch shown in FIG. 5, the average cell loss probability is much better than 1x10 ^-12 , and this cell loss probability decreases sharply as input line occupancy decreases from 100% do. During multicasting, the switch system 10A should provide a better cell blocking probability than the blocking probability that it provides when using non-multicasting because the input packet is limited to not exceed the output bandwidth of the switch system 10A. The reason for this is that the required path through the distribution network 14A is less since the copying needs to be provided as required by the output packet modules 16 ₀ -16 ₁₅ during multicasting.

While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form, details and applications may be made. For example, more than four pipes can be used in a switch structure, requiring modifications to the controller. Accordingly, it is the intention that the appended claims cover all such changes in form, detail and application as falling within the scope of the invention.

According to the present invention, multicasting can be provided by a large-scale telecommunication switch that uses data packets to communicate at full throughput at the 1 terabit / sec level.

Claims (4)

1. A packet switch for switching packets from at least one input line to a plurality of output lines of a plurality of input lines, A plurality of input interfaces each having an input port connected to each input line of the plurality of input lines and each of the input interfaces having an output port an output port, A network for switching a plurality of I input ports to a plurality of P output ports, A plurality of output modules each having a plurality of inputs and a plurality of outputs, each input of the output module being connected to a respective output port of the plurality of P output ports, Connected to respective output lines of the plurality of output lines, An out of band controller for multicasting at least one packet from the plurality of input lines to a plurality of output lines, Each of the plurality of input interface output ports being fanned out to a respective group of F of the one input port of the network, The network has a plurality of C pipes - C has an integer equal to P / I - Each pipe of the C pipes having a path connectable to each output line of the plurality of output lines from each of the plurality of input lines. The method according to claim 1, Each said input interface having a store for storing packets, The out-of-band controller rolls a path request for a packet that has not found a path that has not been blocked through the first pipe and the second pipe to the input of the pipe controller of the third pipe, A controller is stored in the input interface while hunting a path that is not blocked for each output line for each multicast packet Packet switch. A plurality of pipes - each having a plurality of crossbar switches for routing multicast data packets - are connected to a controller for a packet switch having a switch structure having a crossbar switch As a result, A plurality of pipe search controllers, each of the pipe search controllers controlling each of the plurality of pipes; A plurality of storage means for storing a busy-or-idle table, Means for accessing each of said busy / busy stalls simultaneously with a multicast request vector, Each said pipe search controller having a plurality of crossbar switch controllers, each crossbar switch of one pipe having a respective crossbar switch controller, Each of the plurality of storage means being associated with a respective crossbar switch controller of the plurality of crossbar switch controllers. And stores the call / out-of-call table for each of them Controller for packet switch. The method of claim 3, Each call / outage table has a number of busy / busy stop bits - each busy / call stop bit corresponding to a busy / outage state of each output of each crossbar switch Controller for packet switch.