KR100395511B1 - Method of construction of parallel In-Output multiplier over Galois Field - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a method for designing a parallel input / output multiplier on a finite body and a computer readable recording medium having recorded thereon a program for realizing the method.

2. Technical problem to be solved by the invention

In the present invention, a parallel input / output multiplier on a finite field for reducing circuit complexity by performing multiplication by dividing a polynomial into three and multiplying polynomials by a modular formula when the number of coefficients of the polynomial is a multiple of three. Its purpose is to provide a design method and a recording medium on which a program is recorded to realize the method.

3. Summary of Solution to Invention

The present invention relates to a multiplier design method applied to a design apparatus of a parallel input / output multiplier on a finite body, and to a gallo field (GF ((2 ⁿ ) ³ )) whose order is a multiple of 3 in the contract polynomial for multiplication. A first step of dividing the polynomial into three equal parts, generating a combinational formula S _i using the divided polynomial, and multiplying the polynomial on the galoa field GF (2 ⁿ ); A second step of selecting an optimized primitive polynomial (P (x)) and an element (α ⁱ ) using the fourth-order polynomial generated by the multiplication; A third step of multiplying by using the primitive polynomial (P (x)) to a second order polynomial of the general form on a Galloa field (GF ((2 ⁿ ) ³ )) having an order multiple of 3; And a fourth step of substituting a combination formula into the resultant expression of the multiplication to calculate a module using the original contract polynomial (P (x)).

4. Important uses of the invention

The present invention is used to implement secure communication, such as error correction code, digital signal processing.

Description

Method of construction of parallel In-Output multiplier over Galois Field}

The present invention relates to a method for designing a parallel input / output multiplier on a finite field. More particularly, when a degree of a weak polynomial is a multiple of 3, the polynomial is divided into three and the operator is replaced by an AND and an exclusive logical operator. The present invention relates to a method for designing a parallel input / output multiplier on a finite body to simplify circuit complexity, and a recording medium on which a program is recorded to realize the method.

Recently, as regularity and modularity are very important in VLSI implementation considering fast processing speed and complexity, studies on multiplier design suitable for this are being actively conducted.

The multiplication algorithm on the conventionally proposed finite field is as follows.

ED Mastrovito has proposed an algorithm for generating C (z) by performing a modulo operation on the GF (2 ⁿ ) using the polynomial G (z). The coefficient c _i of the polynomial C (z) is defined as Equation 1 during the computation of this algorithm.

Where i = 0, Λ, n-1

That is, in Equation 1, the coefficient c _i is defined through a linear function f ⁱ _j determined by the short polynomial G (z) for any polynomial B (z). Where c _i is an n-tupple vector.

Meanwhile, when C (x) is expressed in a matrix form using the linear function f ⁱ _j , Equation 2 is obtained.

Here, M and A represent nxn and nx1 matrices, respectively.

Meanwhile, the linear function f ⁱ _j is expressed using Equation 3 of the polynomial B (z).

Here, u (k) is k ≧ 0 when 1 and ≦ 0 when 0.

The polynomial multiplication of polynomial A (z) and polynomial B (z) results in 2n-2, and the result is modulo operation in order to be a polynomial on GF (2 ⁿ ). It is a polynomial that is the difference.

Here, Equation 4 shows the coefficient generated as a result. At this time, the coefficient q ⁱ _j is defined as (n−1) × n matrix Q.

Here, q ⁱ _j ∈GF (2), the component q ⁱ _j of the matrix Q can be represented by the coefficients of the short polynomial G (z).

That is, if the weak polynomial has the form G (z) = z ⁿ + g _n-1 z ^n-1 + ∧ + g ₁ z + g ₀ , the coefficients are g ₀ in the first matrix of coefficients of matrix Q. = g _j , q ⁰ ₀ = g ₀ = 1 by the coefficients of the contract polynomial G (z) and iteratively define the rest of the row as (Equation 5).

That is, as can be seen from Equation 5, the complexity of the multiplier can be reduced according to the selection of the component q ⁱ _j value. Thus, component (q ⁱ _j ) is determined by the coefficients of the contract polynomial, and selecting the trinomial equation, which is the shortest polynomial with the smallest coefficient for optimal polynomial selection, is given by Equation (6).

G (z) = z ⁿ + z + 1

Here, if the multiplier is designed using Equation (6), the number of gates used is ^two AND gates AND ² and one exclusive OR gate X ² n.

However, when expressing information through a conventional polynomial polynomial, there is a difficulty in finding a suitable polynomial according to the information, and there is a problem that the complexity changes.

Accordingly, the present invention has been proposed to solve the conventional problems as described above, and multiply the polynomials by the number of coefficients of the polynomial and multiply the polynomials by the modularized sum by multiplying the polynomials by the modular sum. The purpose of the present invention is to provide a method for designing a parallel input / output multiplier on a finite body to reduce circuit complexity and a recording medium on which a program is recorded to realize the method.

1 is a flow diagram of an embodiment of a method for designing a parallel input / output multiplier on a finite body in accordance with the present invention.

2 is a block diagram of a multiplier according to a design method of a parallel input / output multiplier on a finite body according to the present invention.

3 is a block diagram of another embodiment of the multiplier by the design method of the parallel input / output multiplier on the finite body according to the present invention;

4 is a block diagram of another embodiment of a multiplier according to a method of designing a parallel input / output multiplier on a finite body according to the present invention;

The method of the present invention for achieving the above object, in the design method of the multiplier applied to the design device of the parallel input-output multiplier on the finite body, the galoa field (order of multiple of the contract polynomial for multiplication) The first step of dividing a polynomial for GF ((2 ⁿ ) ³ )) into three equal parts and generating a combination formula (S _i ) using this divided polynomial to multiply on the galoa field (GF (2 ⁿ )). ; A second step of selecting an optimized primitive polynomial (P (x)) and an element (α ⁱ ) using the fourth-order polynomial generated by the multiplication; A third step of multiplying by using the primitive polynomial (P (x)) to a second order polynomial of the general form on a Galloa field (GF ((2 ⁿ ) ³ )) having an order multiple of 3; And a fourth step of calculating a module by using a primitive polynomial (P (x)) by substituting a combination formula into the result expression of the multiplication.

On the other hand, the present invention, in the design system equipped with a processor for the design of the parallel input and output multiplier on the finite body, the galoa field (GF ((2 ⁿ ) ³ )) of the order of multiple of the contracted polynomial for multiplication A first function of dividing a polynomial with respect to three equal parts and generating a combination equation (S _i ) using the divided polynomial to multiply on a galoa field (GF (2 ⁿ )); a fourth-order polynomial generated by the multiplication A second function of selecting an optimized primitive polynomial (P (x)) and an element α ^{i using} ; A third function of multiplying the second order polynomial of the general form on the Galloa field (GF ((2 ⁿ ) ³ )) having an order multiple of 3 using the primitive drug polynomial P (x); And a computer-readable recording medium having recorded thereon a program for realizing a fourth function of calculating a module with a primitive polynomial (P (x)) by substituting a combination formula into the result of the multiplication.

The objects, features and advantages described above will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the present invention, the multiplier coefficient is applied only when the number of coefficients is a multiple of 3, so that the complexity of the multiplier is improved, and the design is performed through the following process.

First, the polynomial is divided into three equal parts.

That is, the present invention is applicable only when the number of terms of the polynomial in the polynomial is a multiple of 3, and the general polynomial is divided as in Equation 7 and Equation 8.

Then, a combination formula is generated using the polynomial divided by the equation (7) and the equation (8).

That is, an arbitrary polynomial is divided into A (x) and B (x) by three, and then the divided polynomial is represented by A _i (x) and B _i (x), respectively, and a combination formula is generated using these.

Here, the combination formula is represented by a function S _i (x), which is represented by Equation (9).

S ₀ (x) = A ₀ (x) B ₀ (x)

S ₁ (x) = A ₁ (x) B ₁ (x)

S ₂ (x) = A ₂ (x) B ₂ (x)

S ₃ (x) = [A ₂ (x) + A ₁ (x)] · [B ₂ (x) · B ₁ (x)]

S ₄ (x) = [A ₂ (x) + A ₀ (x)] · [B ₂ (x) · B ₀ (x)]

S ₅ (x) = [A ₁ (x) + A ₀ (x)] · [B ₁ (x) B ₀ (x)]

Then, multiplication is performed using the combination formula S _i (x) generated as described above.

That is, polynomial multiplication can be expressed using Equation (9). Where i = 0,1, k, 5. If the result of arbitrary polynomials A (x) and B (x) is defined as C (x), it can be expressed by Equation 10 using the function S _i (x).

Here, if the above polynomial multiplication of Equation 10 is performed, addition and subtraction associations between coefficients are increased, but the number of multiplications can be reduced to 5 / 9m ² . Since the multiplication of polynomials is more complicated than the operations of addition and subtraction, when the polynomial operation is performed using the coefficient S _i (x) as in Equation 10, the total number of operations is reduced.

Since the finite field GF ((2 ⁿ ) ³ ) presented in the present invention is an enlargement of GF (2 ⁿ ), when 2 ⁿ is defined as q, GF ((2 ⁿ ) ³ ) is defined as GF (q ³ ) do.

Therefore, the multiplication process through any two polynomials (A (x), B (x)) expressed as a standard basis on GF (q ³ ) is represented by Equation 11 below.

A (x) = a ₂ x ² + a ₁ x + a ₀

B (x) = b ₂ x ² + b ₁ x + b ₀

Where A (x), b (x) ∈ GF (q ^m ), a _i , b _i ∈ G (q)

That is, when the multiplication is performed using Equation 11, C '(x) = A (x) B (x), which is a fourth-order polynomial, is expressed by Equation 12.

C '(x) = c'₄x⁴+ c '₃x³+ c '₂ ²+ c '_Onex + c '₀= s₂x⁴+ (s₃+ s₂+ s_One) x³+ (s₄+ s₂+ s_One+ s₀) x²+ (s₅+ s_One+ s₀) x + s₀

At this time, p (x), a primitive contract polynomial on GF (q ^m ) for modulating C '(x), is expressed by Equation (13). Here, P (x) should generate 2 ³ⁿ −1 elements due to the characteristics of the dielectric.

p (x) = x³+ p₂x²+ p_Onex + p₀

Where P (x) ∈ GF (q ^m ), p _i ∈ GF (q)

In addition, when Equation (12) is expressed by C (x), the result of calculating the modulo polynomial of P (x), which is the polynomial, is expressed as Equation (14).

C (x) = c₂x²+ c_Onex + c₀

Where c₂= c '₂+ c '₄(p_One + p₂p₂) + c '₃p_{2 ,}c_One= c '_One+ c '₄(p₀ + p₂p_One) + c '₃p_One, c₀= c '₀+ c '_One(p₀p₂) + c '₃p₀, c_ip_iGF (q)

As described above, the multiplier design method according to the present invention will be described based on FIG. 1.

1 is a flowchart illustrating a method of designing a parallel input / output multiplier on a finite body.

As shown in FIG. 1, the polynomial for Galoa field GF ((2 ⁿ ) ³ ), of order multiple of the contract polynomial, is divided into three equal parts for ^{multiplication} (11). Then, using the polynomial divided into three equal parts, a combination equation (S _i ) is generated and multiplied on the Galloa field GF (2 ⁿ ) (12).

Then, an optimized element α ⁱ on the optimized primitive polynomials P (x) and GF ((2 ⁿ ) ³ ) is selected using the fourth-order polynomial generated by the multiplication (13,14). Therefore, multiplication is performed on the Galoafield GF ((2 ⁿ ) ³ ) using a primitive polynomial P (x) as a generalized second order polynomial (15), and the combination expression is substituted into the result of the multiplication. The module is computed with the primitive polynomial P (x) to complete the design of the final multiplier (16, 17).

If the multiplier on the GF ((2 ⁴ ) ³ ) is designed using the multiplier design method as described above.

First, the contract polynomial on GF (2 ⁴ ) is represented by (15), and the contract polynomial on GF ((2 ⁴ ) ³ ) is represented by (16).

G (z) = z ⁴ + z + 1

P (x) = x ³ + x + α ⁷

Where p (x) ∈ GF ((2 ⁴ ) ³ ), α ⁷ = GF (2 ⁴ ), z = GF (2).

Thus, the use of (Equation 15) by performing a multiplication on the GF (2 ^4), and performs multiplication on GF ((2 ^{4) 3)} using (Equation 16) and (Equation 17) Can be obtained.

C (x) = x²(s₄+ s_One+ s₀) + x (s₅+ s₃+ s₀+ s₂α⁷) + (s₃+ s₂+ s_One) α⁷+ s₀

Here, Equation 17 generates a short term polynomial in all cases, selects a trinomial equation capable of generating 4096 elements from the generated short term polynomial, and selects the simplest polynomial having the simplest form of coefficient.

On the other hand, Equation 16 is expressed by Equation 17 by modulating Equation 12 as a module.

2 is a block diagram of a multiplier according to a method for designing a parallel input / output multiplier on a finite body according to the present invention.

That is, FIG. 2 represents a combination formula (S _i ), and when the multiplier is designed on GF ((2 ⁴ ) ³ ), it is necessary to multiply S _i by element α ⁷ on GF (2 ⁴ ). . The multipliers on the GF (2 ⁴ ) all have eight inputs and four outputs, each of which consists of two element vector inputs a _i , b _i (i = 0, ∧, 3).

3 is a configuration diagram of another multiplier according to a method for designing a parallel input / output multiplier on a finite body according to the present invention.

That is, FIG. 3 is a of the variables shown in FIG._iΑ on⁷= α³+ α Parallel input / output multiplier constructed by substituting + 1 and composed of 12 beta-OR gates.

4 is a block diagram of another multiplier according to a method for designing a parallel input / output multiplier on a finite body according to the present invention.

4 is a multiplier of Equation 17 representing the coefficients of C (x), which is a result of multiplication on GF ((2 ⁴ ) ³ ), and is composed of six AND gates and six ORs. Here, block 30 generating S _i, that is, S ₀ (x), S ₁ (x), S ₂ (x), S ₃ (x), S ₄ (x) and S ₅ (x) is shown in FIG. With the configured internal structure shown in 1, the adders each have a 4-bit output by beta-ORing two 4-bit inputs. Also. Multipliers 40 and 42 to which α ⁷ is connected have the internal structure shown in FIG. 3. Here, the signal line actually has a 4-bit data bus structure.

On the other hand, as a method for designing a multiplier on GF ((2 ⁿ ) ³ ), the contract polynomials G (z) and GF on GF (2 ⁿ ) necessary for designing a multiplier in a finite body when n = 4 or less. The optimized polynomial P (x) on ((2 ⁿ ) ³ ) can be optimized and summarized in Table 1.

n G (z) P (x) α ¹ One x ³ + x + 1 One 2 z ² + z + 1 x ³ + x ² + x + α α ¹ 3 z ³ + z + 1 x ³ + x + α α ¹ 4 z ⁴ + z + 1 x ³ + x + α ⁷ α ⁷ + α + 1

In this case, the multiplier is designed using the weak polynomial and the element on the GF ((2 ⁿ ) ³ ) of Table 1, and the number of gates used is shown in Table 2 below.

n α ⁱ × s _i AND-gate EX-OR-gate One 0 6 6 2 2 24 44 3 2 54 86 4 2 96 128

In other words, as shown in Table 2, there is not always a constant polynomial P (x), and the complexity is different according to the polynomial.

Therefore, Table 3 shows nine cases in which the low gate complexity multiplier can be designed in the contract polynomial P (x) on GF ((2 ⁿ ) ³ ) in consideration of the contract polynomial, and the gate complexity is calculated. In summary.

Since most fluids include the nine types of weak polynomials shown in Table 3, the complexity can be obtained from Table 3 when the simple polynomial is selected.

no P (x) AND-gate OR-gate α ⁱ × s _i One x ³ + x + 1 6n ² 6n ² + 8n -6 0 2 x ³ + x ² + 1 6n ² 6n ² + 8n -6 0 3 x ³ + x + α ⁱ 6n ² 6n ² + 10n -6 2 4 x ³ + α ⁱ x + 1 6n ² 6n ² + 10n -6 2 5 x ³ + x ² + α ⁱ 6n ² 6n ² + 10n -6 2 6 x ³ + α ⁱ x ² + 1 6n ² 6n ² + 11n -6 2 7 x ³ + x ² + x + α ⁱ 6n ² 6n ² + 8n -6 2 8 x ³ + x ² + α ⁱ x + 1 6n ² 6n ² + 11n -6 2 9 x ³ + α ⁱ x ² + x + 1 6n ² 6n ² + 13n -6 3

The present invention described above is not limited to the stated embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The present invention as described above, since the number of information that can be expressed in the combination of GF ((2 ⁿ ) ³ ) is 3n can have a regular and modular structure using only limited information, and optimized by designing only the AND gate and the OR gate There is an effect that can implement the VLSI.

Claims (4)

In the design method of the multiplier applied to the design device of the parallel input and output multiplier on the finite body, To multiply, divide the polynomial for galloa field (GF ((2 ⁿ ) ³ )), which is a multiple of order of the contracted polynomial, into three equal parts, and generate a combination equation (S _i ) using this divided polynomial. Multiplying on Galloa field (GF (2 ⁿ )); A second step of selecting an optimized primitive polynomial (P (x)) and an element (α ⁱ ) using the fourth-order polynomial generated by the multiplication; A third step of multiplying by using the primitive polynomial (P (x)) to a second order polynomial of the general form on a Galloa field (GF ((2 ⁿ ) ³ )) having an order multiple of 3; And A fourth step of substituting a combination formula into the result expression of the multiplication and calculating a module with a raw contract polynomial (P (x)) Method of designing a parallel input and output multiplier on a finite body comprising a. The method of claim 1, The multiplication operator used for the multiplication, A method of designing a parallel input / output multiplier on a finite field, which is an AND gate and a beta OR gate. The method of claim 1, The primitive drug polynomial (P (x)), A method of designing a parallel input / output multiplier on a finite body, characterized by generating 2 ³ⁿ -1 elements depending on the characteristics of the finite body. A design system having a processor for designing a parallel input / output multiplier on a finite field, To multiply, divide the polynomial for galloa field (GF ((2 ⁿ ) ³ )), which is a multiple of order of the contracted polynomial, into three equal parts, and generate a combination equation (S _i ) using this divided polynomial. A first function of multiplying on galoa field GF (2 ⁿ ); A second function of selecting an optimized primitive polynomial (P (x)) and an element (α ⁱ ) using the fourth-order polynomial generated by the multiplication; A third function of multiplying the second order polynomial of the general form on the Galloa field (GF ((2 ⁿ ) ³ )), the order of which is a multiple of 3 using the primitive drug polynomial (P (x)); And A fourth function of calculating a module with a raw contract polynomial (P (x)) by substituting a combination formula into the result expression of the multiplication; A computer-readable recording medium having recorded thereon a program for realizing this.