KR100395032B1 - Method and system for testing memory programming devices - Google Patents

Abstract

A novel system and method for testing semiconductor devices has a pattern generator implementing a test signal algorithm uniquely coupled with a recording system which is an individual hardware system for each device under test. The improved pattern generator and recording system functions in conjunction with a system designed to perform parallel test and burn-in of semiconductor devices, such as the Aehr Test MTX System. The MTX can functionally test large quantities of semiconductor devices in parallel. It can also compensate for the appropriate round trip delay value for each chip select state for each device under test. This system of testing provides an effective and practical method for reducing overall test cost without sacrificing quality.

Description

[0001] METHOD AND SYSTEM FOR TESTING MEMORY PROGRAMMING DEVICES [0002]

When fabrication of other semiconductor devices such as integrated circuits and flash memory is completed, the semiconductor devices are subjected to burn-in and electrical inspection to identify and remove defective semiconductor devices prior to shipment to the customer. &Quot; Burn-in " relates to the operation of an integrated circuit at a predetermined temperature or temperature profile, typically at elevated temperatures in an oven. Electrical bias levels and / or signals for certain operations are supplied to the semiconductor devices while they are at the elevated temperature. Utilizing the elevated temperature accelerates stresses that the device experiences during burn-in, so that a failed peripheral immediately after being placed in the service state turns out to be defective during burn-in and is removed prior to shipment. In electrical testing, electrical bias levels and signals for more complex operations are provided to the device for complete inspection of its function.

With respect to the testing of flash memory devices, there is a limit on the number of times each address can be programmed in the device. If one address is erased after being programmed, erasure is the same as programming, because the state of the address is changing. Given these limits, the number of programming operations consumed in testing of the device is critical to enable sufficient residual programming operations for use by the end user. Obviously, it is desirable to keep the number of programming operations as small as possible, consistent with proper device testing.

To write data to memory, the write operation must be repeated several times at the same address. The manufacturer of the device will define the maximum number of operations that can be repeated to write the data to memory. If the number of repetitive actions during the test fails to record the data and reaches this maximum, then the device is defective.

Because of the physical shape associated with the device to be inspected and the process differences across its surface, addresses located in one area of the device can successfully record with only a few iterations, but addresses in other areas of the same device are fairly More repetitive motion may be required. It is desirable to ensure the possibility of avoiding over programming of those devices that can be programmed with several operations and programming devices that require a larger number of operations to a maximum. To achieve this goal, it must have the ability to control each device independently and track the number of repetitive operations on that particular device.

A typical practically usable flash memory test system is shown in FIG. Each device 5 must be coupled to its own chip select pin 1 which enables or disables the device 5 from recognizing any action being performed on it. Each chip select pin 1 enables several consecutive input cycles in the following manner. One command is input to the device 5 and indicates what to do. For example, the input data may instruct the device 5 to write, verify, or read. Finally, the data to be written to that address follows the instruction.

Prior art systems have some limitations. Each device 5 must be coupled to its own chip select pin 1 and the current technology allows only one device (DUT) 5 to be performed per chip select pin 1 at any one time. Also, since there is one signal line for each device, there must be as many signal lines as the number of devices.

Figure 2 shows a programming algorithm of a typical flash memory currently in use. The algorithm starts with an initial condition (12) with n = 0 initial condition (10) and a count of (cnt) = 0. The program starts by inputting a command and writes data to the first address at 14. And verifies the data in the first address at 16. If the device 5 has not been properly programmed, the DUT under test will fail the test at 18. Each time the test fails at 18, the algorithm checks at 20 to see if the count (12) has reached the maximum allowable set by the manufacturer. If not, the count 12 is written, verified, and checked at the first address until 1 is incremented and the count 12 reaches the maximum allowable value or the DUT 5 passes the check at 18 The next cycle of the instruction is executed. When the count 12 reaches a maximum, the DUT 5 is the defective device 5. [ However, if the DUT 5 passes the check at 18, the program moves to the next address and repeats the process. The program continues until it reaches the last address.

A typical example may be the inspection of 64 devices 5, all of which are operated in parallel by the input set with a maximum iteration number of 65 specified by the manufacturer. It is important that only one of the 64 devices 5 at a time is enabled at a time. Since only one device 5 is enabled at any one time, the inspection procedure is time consuming and costly. The overall procedure may need to be repeated up to the maximum number of iterations allowed in each of the 64 devices 5 for each address. Therefore, 1,600 iterations may be required to test this set of devices (5).

Current systems typically have 64 select signals per pattern generator and ten pattern generators. So, typically, the maximum capacity of the current system is 640 devices 5. At present, it is not possible to determine the total time required for these 640 devices 5 because the number of iterations required to program each address is unknown.

Another aspect of the prior art system is to consider the delay time for the inspection system to transfer signals between the inspection system and the DUT 5 to obtain a more accurate time measurement at the DUT 5, It is known as a Round Trip Delay (RDT). The RTD in the prior art may vary from device to device. This diversity makes it difficult to measure the time of the device, such as propagation delay time or access time. Accurate RTD time is essential to know how much system delay is from the time measurement. There is usually a small supplement in the inspection hardware for any fixed amount of RTD. The remaining variation can be handled with programmable hardware delay or software. However, the prior art measures only one round trip delay time for one device 5.

The present invention generally relates to systems and methods for evaluating integrated circuits and other semiconductor devices. And more particularly to software coupled with computer hardware capable of efficiently inspecting a plurality of semiconductor devices.

1 is a typical prior art flash memory test system.

Figure 2 is a typical conventional flash memory programming algorithm.

3 shows a part of a flash memory inspection system according to the present invention.

4 is a schematic diagram of a flash memory test system programming algorithm in accordance with the present invention;

5 is a block diagram and schematic diagram of a flash memory test system in accordance with the present invention.

Figure 6 shows a miniature network of flash memory test systems in Figures 3-5;

Figure 7 is a block diagram of the tester in Figure 6;

Figure 8 illustrates a large network of flash memory test systems in Figures 3-5;

Figure 9 shows a data flow of a flash memory test system in Figures 3-8;

10A shows a conventional distribution pattern of signal lines flowing through an array of devices in a burn-in board;

Figure 10B shows a preferred embodiment of the flow of signal lines through an array of devices in a burn-in board;

11 shows a pattern generator of a preferred embodiment;

A new system and method for inspecting a flash memory device is disclosed herein. The system and method according to the present invention have a single integrated software operating in a recording system. The recording system includes a separate hardware system that tracks continuous programming known as the state of a passflag for each device under test. The recording system of the preferred embodiment includes two sets of latches that track the path flag state. A set of latches tracks the state of the pass flags on each data line of the device. The other latch is triggered when all datapath flags for the address of the device are read as true. The triggering of this second latch indicates that the data has been continuously programmed into the device under test. The recording system determines whether the device is defective in each address unit and performs the appropriate operation irrespective of all other devices being checked in parallel. If the second latch is set to indicate whether the address is correctly programmed, the algorithm triggers a non-operational instruction. This non-operating instruction stops programming at the address for the particular device. The address for the particular device passes the test and no longer receives another test.

The improved software and recording system operates in conjunction with systems configured to perform burn-in and parallel testing of devices such as the MTX Massively Functional Test System (MTX) produced by the Aehr inspection system. MTX can functionally inspect a large amount of devices in parallel, but only one pattern generator is required to inspect all devices. A single system of two sets of latches in a recording system triggered by each device allows multiple use of one pattern generator. Such inspection systems provide an effective and practical way to reduce the overall inspection cost without compromising quality.

A single RTD can not be used for the given test board 47 of FIG. 7, since the input signal lines are connected to more than one DUT 5, and many devices 5 are also connected to the same comparator. Thus, there must be several RTDs, one for each chip select 1 state. This problem is solved by compensating an appropriate one-week delay value by the timing generator 70 for each semiconductor device in each state selected by chip selection.

The present invention includes a method of inspecting a semiconductor device by coupling a pass flag to a recording system. The command and data are sent to the first address of the device and this information is verified. If the data is not continuously written in the first address, the command and data are repeatedly transmitted and verified to the first address. The number of repeated attempts to successively program the first address is counted. When this count reaches a predetermined maximum value, the semiconductor device is rejected as defective. If data is continuously written to the first address, the path flag is set to TRUE. When the path flag is set to " true ", the transfer of the write command to the first address is completed. All preceding steps are repeated for successive addresses until the end address is reached.

Another aspect of the present invention is a system for inspecting a semiconductor device using a single path-flag generator that indicates whether or not a semiconductor device is defective. The first set of latches is coupled to a path flag signal generator for tracking the state of the path flag signal generated by the path flag signal generator for each data bit of the semiconductor device. The second latch tracks the collection set of latches of the first set for each device.

Another aspect of the present invention is a semiconductor inspection apparatus having a pattern generator for generating a plurality of inspection signals for a semiconductor device. The interface connects the plurality of semiconductor devices in parallel to the pattern generator. The plurality of inspection result readers are connected to the interface so that one of the plurality of inspection result readers can be connected to each of the plurality of semiconductor devices. The pattern generator compensates for an appropriate one-week delay value.

The advantages and features of the present invention will become apparent to those skilled in the art in reviewing the specification and drawings of the present invention.

3 shows a part of the flash memory inspection system of the present invention. Unlike the conventional flash memory test system shown in FIG. 1, the present invention allows an individual chip select 1 signal to enable multiple devices 5 simultaneously. Only one pattern system 45 of FIG. 7 is required to inspect the multiple devices 5. Although the multiple devices are enabled at the same time, the software embedded in the pattern generator 45 operates when only one part is checked. Such multiple enabling of the device 5 reduces both inspection time and inspection cost.

The preferred embodiment utilizes a chip select 1 signal that can process up to 16 devices 5 simultaneously. It includes 128 input / output (I / O) pins 25, which simultaneously allow operation of 16 8-bit length devices 5 per chip selection 1. There are 128 I / O pins 25 and 32 chip choices 1 that can accommodate up to 512 devices in a given slot of the preferred embodiment. Since the preferred embodiment includes 30 slots, the present invention can examine more than 15,000 devices 5 compared to 640 devices 5 of the exemplary system shown in Figures 1 and 2.

The flash memory program algorithm shown in Fig. 4 is used in the flash memory inspection system shown in Fig. As in the conventional algorithm of FIG. 2, this improved algorithm performs the standard function of sending commands and data to 14, inspecting the data at 16, and counting the number of iterations at 12. However, in addition to the functions performed by conventional algorithms, the improved algorithm of the present invention includes novel features that utilize the recording system 30 to track information about individual devices 5 that are examined simultaneously in parallel .

The improved algorithm of the present invention is implemented as follows. The address counter 10 and the loop counter (cnt) 12 are initially set to zero. Additional initial conditions are set in the path flag 32A that tracks the pass / fail status of each device 5. [ It is initially set to false assuming that the device under test 5 is not passed early in the test. The program first inputs 14 data to the first address. This address is checked at 16 to ensure that the data is successfully programmed. If the data is not successfully programmed, the state of the path flag 32 is set to true at 32B. Once the pass flag 32 is set to true, the DUT 5 associated with the true path flag 32 will no longer receive the program command. The part receives a non-operational command at 36 to operate the successfully programmed device to do nothing. This operation is performed by combining the algorithms with the recording system 30, which is a separate hardware system for each DUT 5. That is, there are 780 recording systems 30 in the system of FIG. For parts that are not successfully programmed, the individual flag 32 is still set to false. The false state of such a flag signals to the system checking at 20 whether the count 12 reaches the maximum allowable number set by the manufacturer. If not, the count 12 is incremented by one. The system then repeats the loop programming at 14 and checking at 16 for the address until the count 12 reaches the maximum allowed number or the DUT 5 passes the test 18. The pass / fail status of each part is individually recorded until the maximum number of loops set by the manufacturer has been reached. If the count 12 reaches the maximum number of path flags 32 in a false state, the DUT 5 is considered a defective device. However, if the path flag 32 indicates a true state, the DUT 5 passes inspection 18, the program moves to the next address, and repeats this process. The program continues this process until the end address is reached.

Once the maximum number of loops in the algorithm has been reached for all the parts of the DUT 5, all path flags 32 are examined to determine if the device 5 has passed or failed. Figure 5 shows a recording system 30 that interacts with a flash memory programming algorithm that performs the function of examining the path flag 32. [

Initially, when all the path flags 32 are false, the data to be programmed into the part of 14 of Fig. 4 is transferred to the part 14 via the recording system 30. [ At 16 the test operation is performed and the output of the device is compared to this data. The signal for comparing the data has a length equal to the length of the bit length of the part to be inspected.

There are several different configurations of parts. For example, a part may be 8 bits long, 16 bits long, or 18 bits long. If, for example, the part has an 8 bit length, all 8 bits must be checked. If either of the 8 bit lengths is not programmed correctly, the latch 40 of FIG. 5 associated with that part is not set.

The latch 40 of Figure 5 has 16 latches 40 per chip selection 1 of Figure 3 in the preferred embodiment associated with each device 5, 1 < / RTI > The latch 40 is set only when all the bits of the part are passed. In addition, the preferred embodiment has a supplemental set of error latches 41, shown in FIG. 5, that track the path flags of each data bit. The two sets of latches, namely the latch 40 and the error latch 41, can inspect the multiple devices 5 having only the single pattern generator 45 of FIG.

Once the program is successfully executed on a normal sequence of addresses, data output from the pattern generator 45, and on all bits of an address rather than in an instruction, the static register maintains the non-operational instruction 36 of FIG. This non-operating instruction 36 causes the signal of the pattern generator 45 to reprogram the already successfully programmed address.

The improved algorithm and hardware system of the present invention is a system designed to perform swallowing and burning of a memory device 5, such as the Massively Parallel Functional Test System (MTX) manufactured by Aehr Test Systems, as shown in FIG. And so on. The MTX can functionally inspect multiple devices 5 in parallel. This inspection system provides an effective way to reduce the overall inspection cost without compromising quality. The MTX can inspect more than 256 devices 5 on the inspection board 47 of each device shown in FIG.

Each slot of the system can test up to the 128 device I / O pins 25 shown in FIG. The system pattern generator 45 of FIG. 7 enables offloading, data retention, and refresh of long functional test patterns to be examined in a massively parallel environment of MTX from conventional memory automatic test equipment (ATE).

The device check board 47 may use program rewrite pass / fail logic within the pattern generator to provide devices of different shapes without having to make physical changes. Nonprogram rewriting pass / fail logic can also be used as an option to reduce costs.

As a burn-in system, the MTX combines parallel capability checking with common burn-in capabilities. The environmental chamber may have an operating test temperature range of -55 ° C to + 250 ° C, but a preferred inspection temperature range is -55 ° C to +150 ° C. Since this is an inspection during the burn-in system, the MTX detects a larger failure range than the standard method of the separate inspection and burn-in system. By inspection, during the optimization of the burn-in period, absolute detection and burn-in escape recognition and recovery failures are allowed. By inspection, failed parts of burn-in or inspection can be excluded.

The system uses a standard Internet with a TCP / IP network protocol. This provides a flexible network structure. 8, the user may easily configure the network for a single system or may have a number of troubleshooters 51, debug stations 52, loaders and unloaders 50, user stations 55, A large and complicated network having the network server 49 can be easily configured.

Returning to Fig. 9, the network server 49 is a UNIX operating 486 PC (or higher). Some larger networks may require workstations. The server 49 operates an industry standard database engine 57 that maintains the master program library and the inspection data library. When the operation is started, the server 49 stores a copy of all necessary inspection plans on the local controller hard disk. Even if the network fails, the operation can be completed. The tester 51 will store all the test results on the local controller hard disk until it can transmit the data back to the server 49. [ All records are generated by the database engine 57 and can be evaluated and output by the server 49 or MTX tester 51.

In the case of correction, the backup power supplies supply power to the local controller. The tester 51 is immediately interrupted, but the local controller has the time to perform the controlled interception sequence, so that the data is not lost or corrupted. Once the power is restored, the user can manually start operation from the initial state of the last performed inspection step.

Large-scale program debugging capabilities are included within this system. The user can select any step of any inspection program and modify the inspection conditions to immediately execute the modified program. The user instructs the pattern generator 45 to enter into the continuous loop and examine the signals in the center of the pattern in detail by setting a scope sync point.

The operator interface comprises a graphical display, a trackball or a mouse and keyboard. The operator display may be inside another language. All normal manufacturing activities, such as loading and unloading lots, can be performed without using a keyboard. The printer may optionally be added to facilitate printing of the report.

The MTX tester 51 performs all inspection functions. The tester 51 includes an operator interface used to control the operation of the tester 51, such as a loading lot, an unloading lot, a request report or a display state. The tester 51 contains all the test electronics, such as the pattern generator 45 of Figure 7, the power supply, the drivers and the receivers.

Three different environmental chambers can be used in the MTX. That is, there are heating only, heating / cooling up to -20 ° C, and heating / cooling up to -55 ° C. The heating-only chamber has a temperature range of approximately +45 ° C to +150 ° C. This chamber is not sealed. The chamber draws cool air from the required room and exhausts warmth as needed. The chamber may vent the warmth to the room or vent the warmth through an exhaust duct. The heating only chamber can provide up to 30 inspection slots in the chamber for the nominal system capability of the 7680 device (5).

The heating / cooling chamber is sealed. The non-freezing gas freezer provides cooling below +45 [deg.] C. The heating / cooling chamber can provide up to 16 inspection slots in the chamber for the nominal system capability of the 4096 device (5). Heating / cooling down to -55 占 폚 is an option to add another mechanical stage of non-freezing gas refrigeration to the heating / cooling chamber.

In addition to other environmental chambers, the MTX can provide multiple test zones. The inspection zone is shown in Fig. The system usually consists of two zones (15 slots / zone for heating only or 8 slots / zone for heating / cooling chamber).

The systems shown in Figures 1 and 2 have one pattern generator 45 for each slot, the MTX has one pattern generator 45 for each zone, each zone includes multiple slots have. The system reduces the number of required pattern generators 45, thereby reducing inspection costs. As shown in Figure 7, each slot in the zone has a slot interface 59 and may include a selection error analysis 61. [ The pattern generator 45 is algorithmic and can generate N, N ^3/2, and N ² . As shown in FIG. 11, the pattern generator 45 includes a microsequencer 76, a timing generator 70, an address generator 72, a data generator 74 and a chip selection generator 78. The pattern generator 45 also includes a pattern formatter 80 and a state latch 82. The pattern formatter 80 distributes the data generator output across the I / O lines and multiplexes the addresses on the data lines. The state latch 82 resynchronizes the address data and the chip selection output to the master clock T0. The pattern generator may generate all industry standard test patterns.

Microsequencer 76 controls all pattern generator 45 functions and includes all control logic, loops, branching and subroutine logic and refresh timers. The microsequencer 76 also includes facilities for generating area tuned pulses. The MTX also utilizes a timing generator 70 having multiple timing sets to facilitate selection of different timing sets for each pattern condition. do. Each set of timings sets the cycle time to set the positive rising and falling etch locations for each clock channel. The system will allow up to four etches per clock phase whenever appropriate.

The address generator 72 of the MTX generates a 16-bit logical X address, a 16-bit logical Y address, and a 16-bit refresh address. Users can select a commonly used address pattern from a menu. However, when a special pattern is required, there is a selected pattern assembler, so that its own unique pattern can be recorded.

With the optional address scrambler, the user can change the logic memory location to the physical memory location on the DUT. In addition, the address scrambler provides 32K x 16 vector memories after X and Y. The contents of the vector memory are successively addressed and controlled by the microsequencer 76.

The MTX uses a data generator 74 that logically generates 18 bits of single logical data. In addition, there is a parity generator that can be used to generate data based on logical X, Y addresses. All common data patterns can be selected from a menu. If a specific pattern is desired, the pattern assembler can be used to generate a single data pattern.

In order to convert the logical data into physical data, the data generator 74 includes a topological scrambler of very powerful data. It also provides vector memory. The contents of the vector memory are continuously addressed, transmitted, and controlled by a microsequencer.

The pattern generator 45 generates 32 chip select signals. The microsequencer 76 controls chip select generation. For normal testing, the microsequencer allows different chip select (1) signals to select some groups on the device test board 7 of FIG. When a portion is not inspected and is under stress, all 32 chip select signals are activated.

The test slot interface 59 of FIG. 7 includes a DUT 5 power supply, a signal driver, a data output comparator, and pass / fail logic. Each slot has its own single and independent power supply for the DUT (5) power supply. All power supplies have programmable current limit and over / under voltage protection. If the voltage or current exceeds any limit, only the slot exceeding the limit is blocked. The tester 51 stores all errors. The actual output voltage and the actual output current for all power supplies are the lead-back from the respective outputs, and are written to the controller of the tester 51.

Each check slot includes a total of 128 I / O drive channels 25 of FIG. 3 and 32 chip selections (1) of FIG. In addition, there are two copies of 16 physical X bits, two copies of physical Y bits, and four copies of 8 user clocks. These multiple copies tend to be used in separate parts of the component inspection board 47 of FIG. This allows to reduce the load on each driver. This reduction provides the maximum quality of the signal. All of the input signals are monitored on the driver board 47 of FIG. 7 to ensure that the driver operates and that some inputs do not block the signal. The driver board 47 combines timing and data from the pattern generator 45 and provides signals to the DUTs. Each of the 128 data I / O channels 25 in FIG. 3 includes a driver and a dual level comparator. Depending on the geometry of the part to be examined, the physical data signal is copied and fills 124 eight-channel fields; If the portion is X1, the data is repeated 128 times; If the portion is x4, the data is repeated 32 times; If the portion is x8, the data is repeated 16 times; If the portion is x9, the data is repeated 14 times; If the portion is x16, the data is repeated eight times; If the portion is x 18, the data is repeated seven times. There are three programmable high and low level sets for the driver. One set of levels is used for the address driver, another set is used for the data driver, and the other set is used for the clock and chip select driver.

Each 128 data I / O channels 25 in FIG. 3 includes a dual level comparator. There is one programmable high and low level set for the comparator. The error latch 40 of Figure 5 exists for each of the 128 comparators. The chip select (1) signal is transmitted to only one element 5 at a time per I / O channel 25, although several elements 5 are generally connected to each I / O channel 25 of FIG. ).

Each check slot interface 59 of FIG. 7 includes its own pass / fail logic. As each chip selection (1) in FIG. 3 is completed, the contents of the error latch 40 of FIG. 5 are stored and added to the previous results for the chip select (1) state. Depending on the result, at the end of the test phase, the accumulated pass / fault results for the entire 128 I / O channels of Figure 3 during the period up to thirty-two chip select (1) Allows parallel inspection of the parts. The tester 51 of FIGURE 6 represents a portion on the device test board 47 of FIGURE 7 depending on the mapping of the chip select (1) state to the I / O channel 25 of FIGURE 3 and a predetermined socket position Use software.

In addition to the standard pass / fail logic, the MTX has the ability to perform the large-scale error analysis 61 of FIG. Additional circuitry for each slot provides this capability. The error analysis (61) selection can use the error count (12) and error sign in Figure 4 to gather two types of error data.

A 32-bit counter is provided for each I / O channel in FIG. The count 12 is incremented at all times when there is an error in a particular channel. The total number of errors for each channel is recorded.

The same circuit captures the fault sign for each chip selected state. The defect symbol consists of a defect address and a defect data state. The defect address may be a logical or physical address. The defect data state may be a logical or physical data state.

The device inspection board 47 of Fig. 7 includes a device 5 to be inspected. The device test board 47 includes an array of high temperature sockets and terminations for signal transmission lines. The elements 5 are loaded in an element inspection board 47 which is arranged in the environmental chamber alternately.

Proper termination provides the best possible waveform to the device 5 to be inspected. The termination value is unique for each device test board 47 type and is highly dependent on the characteristics of the device 5 to be inspected. In order to determine the correct termination, the device test board 47 should be installed with the actual device 5 being designed.

When the inspection system generates an input signal to the DUT 5, a signal is generated in the tester 51 before it has substantially reached the input pin of the DUT 5 and the pin driver and the interconnection circuit (E. G., ≪ / RTI > This method involves a slight delay time (T _o ) that depends on the fixture and changes from fixture to fixture.

Similarly, when the inspection system inspects the output signal from the DUT 5, the signal must be transferred from the DUT 5 output pin to the interior of the electronics on which the actual inspection is to be performed, via some internal circuitry and a pin receiver . It also involves some delay (T _o ) depending on the fixture and changes from fixture to fixture. This may also be different from Ti due to differences in electronic path delays.

In order for the inspection system to perform a more accurate timing measurement on the DUT 5, the delay time for signal transmission between the inspection system and the DUT 5, that is to say the delay generally known as one-week delay (RTD) do. The RTD for the prior art can be in a wide range for different devices. This wide range can make it difficult to measure timing on elements such as propagation delay time or access time.

Precise RTD time is needed to know how many systems are delayed to subtract from the timing measurements. There is usually compensation within the test hardware for some fixed amount of RTDs. The remaining variable amount can be handled as a programmable hardware delay or a software delay. In this way, the tester of FIG. 6 can measure the exact timing on DUT 5. However, the prior art measures only on a single round trip time for a single device 5.

However, the above problem is more complicated in the case of MTX. There is no single RTD that can be used for a given test board 47 of FIG. 7, since the input signal lines are connected to more than one DUT 5, and many devices 5 are connected to the same comparator. There are several RTDs, and the RTD is one for each chip select 1 state.

When the MTX test board 47 is designed and manufactured first, it is characterized by determining an appropriate RTD value for each chip select 1 state. These settings of values are stored in the database and are associated with the design of a particular test board 47. When the design of the test board 47 is used in an MTX system, the appropriate chip select 1 RTD value is stored in the memory accessed and read from the database at a pattern rate, and is set to one set to cause an appropriate RTD value for a given chip select 1 state Lt; RTI ID = 0.0 > programmable < / RTI > In addition to a chip select 1 signal for selecting a group of devices 5, a chip select signal is used to select any of the round trip delay times for use when inspecting the device 5. The timing generator 70 compensates for an appropriate one-week delay value for each semiconductor device in each state selected by chip selection. Since the information is stored in hardware memory, there is no need to wait for new software downloads or calculations. In this way, the MTX can always provide the maximum overall timing accuracy, even though the effective fixed delay varies throughout the inspection process.

Referring to FIG. 10A, the high temperature inspection board 47 has multiple devices 5 arranged in an array having multiple data lines, clock lines, and chip select signals. A high temperature test board design that is compatible with the present invention is disclosed in U.S. Patent Application Serial No. 08 / 161,282, filed Dec. 1, 1993, herein incorporated by reference. An example is a 16 x 16 array with 16 address lines, 32 data lines, 8 clock lines, and 32 chip select lines placed on board 47. These signal lines must be distributed around the high temperature test board 47 for each device 5. A typical dispersion pattern is shown in FIG. Some very complex routing signals may be required to reach each device 5. The preferred embodiment shown in FIG. 10B divides the board into sections with each section having a dual signal set. For example, in the preferred embodiment, the board 47 can be divided into four sections 65. In working with the previous embodiment, each quadrant 65 has 16 address lines, 32 delinear lines, 8 clock lines, and 8 chip select lines. Each section 65 has the same number as each line having all of the chip select lines from all 32 sections. The signal lines can travel straight through the board 47 rather than proceeding through the complicated structure. The advantage of this structure is that the trace length is truncated to about 3/4, reducing the RTD of the device 5, and the loading is truncated by 3/4, which greatly improves the signal quality.

Each device test board 47 is identified by a single seven digit sequence number. Each digit is passively encoded using a register on the device check board 47. The high temperature (680) pin card edge connector provides an interconnection mechanism between the device inspection board 47 and the system.

MTX has a wide range of self-testing and diagnostic capabilities. Each board 47 in the system performs a reliable test on its own power-up. This confidence check is designed to provide quick verification of basic functionality. In addition, the user can perform a wider diagnosis. The diagnosis is to separate the defects into replaceable subassemblies whenever possible. The system requires very little manual calibration.

An optional device includes a user station 55, which is a remote PC connected to the MTX network. The user station 55 may be used for off-line program deployment, production control (lot limitation, status investigation, etc.) and network management.

Another example of any device is an environmental inspection station or debug station 52. The debug station 52 is a simplified checker 51. It is an inspection electronics for one slot, but not an environmental chamber, so that the whole electrical inspection can be performed in the environment. It also provides casey user access to the device check board 47 and the test electronics. These stations can be used to check the functionality, signal and pattern of the new test program and verify the voltage. The station can be used to repair the inspection electronics or device inspection board 47 and the preliminary loading device inspection board 47 before the boards enter the inspector 51. This helps identify, fix, or mask devices 5 that make poor contact, bad socket locations, or initial defects.

Another option is to use the MTX design to interface with the intelligent autoloader / storage system. When an intelligent loader / sorter system is attached to the network, the server 49 may provide a single, predetermined loading mask to the loader for each device inspection board 47 to indicate a bad socket location that is not loaded . After the portion is examined, the server 49 may provide a single sorting map to the intelligent unloader.

It will be apparent to those skilled in the art that various changes in form and details of the invention shown and described may be made therein. Such variations are included within the spirit and scope of the appended claims.

Claims (50)

1. A method for testing a plurality of semiconductor devices, Coupling a pass flag to a recording system for each discrete semiconductor element of the plurality of semiconductor elements; Transmitting write commands and data in parallel to a first address for each discrete semiconductor element of the plurality of semiconductor elements; Verifying the data on the first address in parallel; Wherein if the data is not successfully written to the first address for all of the plurality of semiconductor devices, then only the semiconductor device in which the data is not successfully written to the first address, among the plurality of semiconductor devices, Repeating the step of transmitting and verifying a write command and data to one address; Counting the number of iterations to successfully program the first address; Rejecting, when the repetition attempt reaches a predetermined maximum value, that the data among the plurality of semiconductor elements is defective as a semiconductor element for which the data was not successfully written to the first address; Stopping further write attempts to the first address if the data is successfully written to the first address of the plurality of semiconductor devices; Setting the pass flag for the particular semiconductor element of the plurality of semiconductor elements to true if the data is successfully written to the first address of a particular semiconductor element of the plurality of semiconductor elements; Stopping sending a write command to the first address of the particular semiconductor element of the plurality of semiconductor elements when the pass flag for the particular semiconductor element of the plurality of semiconductor elements is set to true; And And repeating all of the steps for successive addresses until a final address is reached. 2. The semiconductor device according to claim 1, wherein, for each of the plurality of semiconductor elements, Setting a loop count to zero; setting n to zero; Setting an address to zero; Setting a pass flag to false; Sending an instruction at address = n; Transmitting data at address = n; Verifying the data at address = n; If address = n is not successfully programmed, checking if the loop count has reached a maximum value; Repeating the step of adding 1 to the loop count and then transmitting the command and data again at address = n if the loop count is less than the maximum allowed, and verifying the data; Checking a state of the path flag when the loop count reaches a maximum value; Rejecting the particular semiconductor element of the plurality of semiconductor elements as defective if the path flag is still set to false; If the address = n is successfully programmed, setting the pass flag for the particular semiconductor element of the plurality of semiconductor elements to true; Stopping transmission of the write command by sending a non-operational command to the first address for the particular one of the plurality of semiconductor elements when the pass flag is set to true, and adding 1 to n ; And And repeating the steps starting from the step of sending an instruction to the address = n. 2. The method of claim 1, wherein the recording system coupled with the pass flag is a separate hardware system for each device under test. 2. The method of claim 1, wherein the recording system coupled with the path flag tracks the state of the path flag. The semiconductor device test method according to claim 4, wherein the state of the path flag is true or false. 2. The system of claim 1, wherein the recording system comprises: a first latch set for tracking a state of a pass flag for each data bit of a semiconductor device; And And a second latch set for tracking the first latch set. 7. The method of claim 6, wherein the device under test is coupled to both the first and second latch sets. A semiconductor device test system using a memory programming algorithm according to the method of claim 1, Wherein the test device is coupled with the algorithm to perform a parallel test of the semiconductor device. 9. The apparatus of claim 8, wherein the test apparatus comprises: A pattern generator for generating information to be input to the element under test; And And a device test board connected to the pattern generator to facilitate testing of the semiconductor device. 10. The semiconductor device test system according to claim 9, wherein the pattern generator generates information to be inputted to a plurality of semiconductor devices. 10. The semiconductor device test system of claim 9, wherein the system utilizes reprogrammable pass / fail logic for application to devices of different structures. 10. The semiconductor device test system of claim 9, wherein the device test board is divided into a plurality of sections, each of the sections having its own signal set. 10. The apparatus of claim 9, wherein the pattern generator comprises: A chip selector for allowing a semiconductor device to be tested; And And a timing generator having a plurality of timing sets. 14. The semiconductor device test system of claim 13, wherein the timing generator variably compensates for round trip delay values for each semiconductor device in each state selected by the chip selector. 14. The semiconductor device test system of claim 13, wherein the chip selector simultaneously enables the plurality of semiconductor devices. 14. The apparatus of claim 13, wherein the pattern generator comprises: A micro-sequencer controlling the pattern generator function; An address generator for selecting or generating an address pattern; And Further comprising a data generator for selecting or generating a dedicated data pattern. 14. The semiconductor device test system of claim 13, wherein the test apparatus further comprises a drive board for collecting information from the pattern generator and providing the information to the element. 10. The semiconductor device test system of claim 9, wherein the test apparatus further comprises an unsealed thermal chamber having a temperature range from about +45 to + 250 < 0 > C. The semiconductor device test system according to claim 18, wherein the heat chamber discharges cooling air when necessary and heats air if necessary. 10. The system of claim 9, wherein the test apparatus further comprises a sealed heating / cooling chamber having a temperature range of + 45 < 0 > C or less. 10. The semiconductor device test system of claim 9, wherein the test apparatus further comprises a peripheral station that does not require temperature control. A system for testing semiconductor devices, A pass flag signal generator coupled to a memory programming algorithm for indicating whether a semiconductor device is defective and performing a parallel test of the semiconductor device; A first latch set coupled to the pass flag signal generator for tracking the state of a pass flag signal generated by a pass flag signal generator for each data bit of the semiconductor device; And A second latch set for tracking a set of said first set of latches for each element; The algorithm comprises, for each semiconductor element: Transmitting instructions and data to the first address; Verifying the data at the first address; Repeating the steps of sending and verifying commands and data to the first address if the data is not successfully programmed to the first address; Counting the number of iterations to successfully program the first address; Rejecting the particular semiconductor element of the plurality of semiconductor elements as defective when the iterative attempt reaches a predetermined maximum value; Setting the pass flag to true for the particular semiconductor device among the plurality of semiconductor devices if the data is successfully programmed to the first address; Stopping sending a write command to the first address for the particular semiconductor device among the plurality of semiconductor devices if the pass flag is set to true; And And repeating all of the above steps for successive addresses until a final address is reached. 23. The semiconductor device test system according to claim 22, wherein the state of the path flag is true or false. 23. The method of claim 22, wherein the algorithm further comprises: Setting a loop count to zero; setting n to zero; Setting an address to zero; Setting a pass flag to false; Sending an instruction at address = n; Transmitting data at address = n; Verifying the data at address = n; Stopping further write attempts to address = n if the data has been successfully written to the first address of all of the plurality of semiconductor devices; If address = n has not been successfully programmed, checking if the loop count has reached a maximum value; Repeating the step of adding 1 to the loop count and then transmitting the command and data again at address = n if the loop count is less than the maximum allowed, and verifying the data; Checking the state of the pass flag connected to the recording system when the loop count reaches a maximum, the pass flag signal being coupled to the recording system; Rejecting the particular semiconductor element of the plurality of semiconductor elements as defective if the path flag is still set to false; Setting the pass flag to true for the particular semiconductor device among the plurality of semiconductor devices when address = n is successfully programmed; Stopping transmission of a write command by sending a non-operation command to the first address for the particular one of the plurality of semiconductor elements when the path flag is set to true, and adding 1 to n ; And ≪ / RTI > repeating the steps starting from sending a command to address = n. 23. The semiconductor device test system of claim 22, comprising a test device coupled to the algorithm. 26. The apparatus of claim 25, wherein the test apparatus comprises: a pattern generator for generating information to be input to a device under test; And And a device test board connected to the pattern generator to facilitate testing of the semiconductor device. 27. The semiconductor device test system of claim 26, wherein the pattern generator generates information to be input to a plurality of devices. 27. The semiconductor device test system of claim 26, wherein the system utilizes reprogrammable pass / fail logic for application to devices of different structures. 27. The semiconductor device test system of claim 26, wherein the device test board is divided into a plurality of sections, each of the sections having its own signal set. 27. The apparatus of claim 26, wherein the pattern generator comprises: A chip selector for allowing a semiconductor device to be tested; And And a timing generator having a plurality of timing sets. 31. The semiconductor device test system of claim 30, wherein the timing generator compensates for a round-trip delay value for each semiconductor device in each state selected by the chip selector. 31. The apparatus of claim 30, wherein the pattern generator comprises: An address generator for selecting or generating an address pattern; A data generator for selecting or generating a dedicated data pattern; And And a micro-sequencer for controlling the pattern generator function. 31. The semiconductor device test system of claim 30, wherein the chip selector simultaneously enables the plurality of semiconductor devices. 31. The semiconductor device test system of claim 30, wherein the test apparatus further comprises a drive board to collect information from the pattern generator and provide the information to the element. 27. The semiconductor device test system of claim 26, wherein the test apparatus further comprises an unsealed thermal chamber having a temperature range of +45 to +250 < 0 > C. 36. The semiconductor device test system of claim 35, wherein the heat chamber discharges cooling air when necessary and heats the air if necessary. 27. The semiconductor device test system of claim 26, wherein the test apparatus further comprises a sealed heating / cooling chamber having a temperature range of + 45 < 0 > C or less. 27. The semiconductor device test system of claim 26, wherein the test apparatus further comprises a peripheral station that does not require temperature control. A semiconductor device testing apparatus comprising: A pattern generator for generating a plurality of test signals for semiconductor devices; An interface for coupling a plurality of semiconductor devices in parallel with the pattern generator; And And a plurality of test result readers coupled to the interface for being connectable to each of the plurality of semiconductor devices, Wherein said pattern generator compensates for an appropriate round-trip delay value for different groups of semiconductor devices. 40. The semiconductor device test apparatus of claim 39, wherein the interface for coupling is a chip selector that simultaneously enables the plurality of semiconductor elements. 40. The apparatus of claim 39, wherein the pattern generator comprises a timing generator having a plurality of timing sets. 42. The apparatus of claim 41, wherein the timing generator compensates for an appropriate round-trip delay value for different groups of semiconductor devices. 40. The apparatus of claim 39, wherein the pattern generator comprises: A micro-sequencer controlling the pattern generator function; An address generator for selecting or generating an address pattern; And Further comprising a data generator for selecting or generating a dedicated data pattern. 40. The apparatus of claim 39, further comprising a drive board to collect information from the pattern generator and provide it to the device. 40. The apparatus of claim 39, wherein the test apparatus further comprises an unsealed thermal chamber having a temperature range from about +45 to + 250 < 0 > C. 46. The semiconductor device test apparatus of claim 45, wherein the heat chamber discharges cooling air when necessary and heats the air if necessary. 40. The apparatus of claim 39, wherein the test apparatus further comprises a sealed heating / cooling chamber having a temperature range of + 45 < 0 > C or less. 40. The method of claim 39, wherein the semiconductor device is mounted on a device test board, the device test board is divided into a plurality of sections, each of the sections comprising a chip select signal for testing groups of the devices in the section And has its own signal set. 2. The method of claim 1, wherein the step of sending a write command to the first address for the particular semiconductor element in the plurality of semiconductor elements comprises the step of transmitting a write command to the first address for the particular semiconductor element in the plurality of semiconductor elements, Wherein the semiconductor device is stopped by transmitting an instruction. 1. A method for testing a plurality of semiconductor devices, Generating a plurality of test signals for the semiconductor device; Coupling a plurality of semiconductor devices in parallel to receive the plurality of test signals; Coupling a plurality of test result readers to each of the plurality of semiconductor devices; And generating the plurality of test signals for each of the plurality of semiconductor devices, Transmitting a write command and data to a first address; Verifying the data on the first address; Repeating the step of transmitting and verifying the write command and data to the first address if the data is not successfully written to the first address; Counting the number of iterations to successfully program the first address; Rejecting a specific semiconductor element in the plurality of semiconductor elements when the repetition attempt reaches a predetermined maximum value; Setting the pass flag signal to true for a particular semiconductor device among the plurality of semiconductor devices if the data is successfully written to the first address; Stopping sending a write command to the first address for the particular semiconductor device of the plurality of semiconductor devices when the pass flag is set to true; And And repeating all of the steps for successive addresses until a final address is reached.

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