KR100393973B1 - burn-in test mode circuit - Google Patents

Abstract

The present invention relates to a one-time test mode circuit that automatically enters a burn-in test mode without additional configuration or manipulation when a certain temperature is exceeded. The present invention relates to a burn-in test mode circuit of a DRAM embedded in a packaged MML. A temperature detector for outputting a burn-in signal when the temperature is detected to be higher than or equal to a predetermined temperature and a burn-in signal when the temperature detected by the temperature detector is higher than or equal to a predetermined temperature to operate a sense amplifier while sequentially enabling word lines to operate a sense cell. A self-refresh section for refreshing the signal, a clock generator for generating a self-refresh clock when the burn-in signal enters the self-refresh section, and a burst counter for receiving a refresh signal of the self-refresh section. Boo, the burst car The pattern generator which generates the write data by receiving the column address of the tab and the burn-in signal of the temperature detector are output to control the burst counter, the pattern generator and the write operation during the burn-in test, and the word line is newly enabled. And a controller for initializing the column address input to the burst counter unit each time.

Description

Burn-in test mode circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a burn-in test mode circuit which is easy to burn-in test even in a packaged state such as a merged memory logic (MML).

In general, burn-in test is a method of preliminarily filtering out a product that is likely to have a defect in order to increase reliability of a semiconductor product.

The burn-in test method in DRAM is to continuously stress a memory cell with certain operations at high temperatures (above 125 ° C).

In this case, applying static stress to the memory cell is not known to help filter out potentially damaging memory cells, so it is necessary to continue to perform certain patterns of DRAM operation. This means that a dynamic stress must be applied to the memory cell.

Typical single-unit DRAM products have no problem with the burn-in test above.

However, the majority of products such as DRAM embedded in MML do not have the ability to control only DRAM from outside the package.

This is because DRAM-specific pins are not exposed outside the package due to factors such as price. DRAM testing of these products is therefore typically done at the wafer level.

In this case, however, burn-in testing in a packaged state is virtually impossible.

The conventional burn-in test mode circuit to enable this is to add a BIST (Built In Self Test), etc. into the MML, so that the BIST must operate the DRAM. In this case, the area of the chip is increased and the design period is extended. Is raised.

However, the above-described conventional burn-in test mode circuit has the following problems.

In other words, by designing the BIST and the like into the MML, the BIST operates the DRAM, which increases the area of the semiconductor chip and increases the design period, thereby raising the price of the product.

An object of the present invention is to provide a one-time test mode circuit that automatically enters a burn-in test mode without additional configuration or manipulation when a predetermined temperature is solved to solve the conventional problems as described above.

1 is a block diagram showing a burn-in test mode circuit according to the present invention

2 is a structure of a typical memory cell

3 is a pattern of stressing a memory cell

4 is a circuit diagram illustrating a temperature detector of FIG. 1.

5 is a circuit diagram illustrating a control unit of FIG. 1.

Explanation of symbols for the main parts of the drawings

21: temperature detector 22: self-refresh unit

23: clock generator 24: burst counter

25 pattern generator 26 control unit

27: light operation

Burn-in test mode circuit according to the present invention for achieving the above object is a burn-in test mode circuit of the DRAM embedded in the packaged MML, detecting the temperature of the package to detect the burn-in signal when the temperature is above or below a certain temperature A self-refreshing unit which outputs a temperature detector and a burn-in signal whose temperature detected by the temperature detector is equal to or higher than a predetermined temperature and operates a sense amplifier while sequentially enabling word lines to refresh memory cells, and the burn-in signal by the on-detector A clock generator for generating a self-refreshing clock when entering the self-refreshing unit, a burst counter unit for generating a column address upon receiving a refresh signal of the self-refreshing unit, and receiving a column address of the burst counter unit for writing data. Pattern generating part and phase to generate A control unit for controlling the burst counter unit, the pattern generator unit, and the write operation during the burn-in test by outputting the burn-in signal of the temperature detector unit and initializing the column address input to the burst counter unit each time the word line is newly enabled. Characterized in that configured.

Hereinafter, a burn-in test mode circuit according to the present invention will be described in detail with reference to the accompanying drawings.

The burn-in test mode circuit of the present invention includes a self refresh unit for operating an internal circuit and a burst counter unit for automatically increasing a column address without external control.

That is, FIG. 1 is a block diagram illustrating a burn-in test mode circuit according to the present invention, FIG. 2 is a structure of a general memory cell, FIG. 3 is a pattern for applying stress to the memory cell, and FIG. 4 is a temperature detector of FIG. 5 is a circuit diagram illustrating the control unit of FIG. 1.

In the burn-in test mode circuit of the DRAM embedded in the MML in the package state, as shown in FIG. 1, a temperature detector 21 for detecting a package temperature and outputting a burn-in signal when the temperature is above or below a predetermined temperature (about 125 ° C.) A self-refresh unit 22 which operates a sense amplifier while sequentially enabling word lines by receiving a burn-in signal having a temperature detected by the temperature detector 21 at a predetermined temperature or more, and the temperature detector 21. When the burn-in signal enters the self refresh unit 22, a burst counter for generating a column address by receiving the refresh signal of the self-refresh unit 22 and the clock generator 23 which generates a clock for self refresh. A pattern generator 25 that receives the column address of the burst counter 24 and generates write data, and the temperature detection unit 24. The control unit 26 for controlling the operation of the burst counter unit 24, the pattern generator 25, the self refresh unit 22, and the write operation 27 during the burn-in test by outputting the burn-in signal of (21). It consists of

Referring to the operation of the burn-in test mode circuit of the present invention configured as described above are as follows.

First, the temperature of the package rises while only power is supplied to the DRAM in the packaged MML. At this time, if the temperature of the package is above a certain temperature (about 125 ° C), the temperature detector 21 inside the DRAM operates to turn on the burn-in signal.

Subsequently, the burn-in signal of the temperature detector 21 is turned “ON” to operate the self-leaf massage unit 22.

In general DRAM, the self-refresh operation operates on the inside itself without external control. At this time, a self-refreshing clock is generated, which of course occurs automatically in most DRAMs.

When the self refresh unit 22 operates, a specific word line of the DRAM is enabled, and a sense amplifier accompanying the same operates.

At this time, the sensing operation is also a stress in the burn-in test, so the burn-in test can also be performed. In this case, even if a very monotonous pattern is sensed, the same data is written to all addresses in the structure of the memory cell (Fig. 2). Dynamic data is applied to the memory cells because data is stored in phase opposite to the adjacent cells.

However, in this case, since the data of the same phase as the upper and lower cells are likely to be stored, it has only about 25% of the dynamic stress effect.

On the other hand, in order to give 100% dynamic stress, all cells must have opposite data from adjacent cells, and all of these data must be reversed and stored again (Fig. 3).

In addition, in order to implement FIG. 3, a process of writing data to a memory cell is required. In order to perform the actual write operation without external control, the burst counter 24 inside the DRAM is used.

That is, the write operation 27 may be performed using the burst counter 24 and the pattern generator 25 to form cells attached to one word line as shown in FIG. 3.

3 is a memory cell in which High data is stored, and ⓛ is a memory cell in which Low data is stored.

Of course, at this time, the burst counter 24 operates in the full page mode. The full page mode is a mode in which the column operation continues indefinitely.

Subsequently, after a predetermined time (the time at which the column address can be executed at least once), the enabled word line is disabled and the operation of the burst counter unit 24 is also stopped.

On the other hand, if one word line is disabled, the self refresh unit 22 automatically enables the next word line after a predetermined time.

When the operating temperature drops below a certain temperature, the temperature detector 21 turns off the burn-in signal.

The memory cell of FIG. 2 is composed of a pair of bit lines BL and one transistor and one capacitor, each of which has a gate and a source connected to a word line WL passing in a direction perpendicular to the bit line. A sense amplifier S / A is connected to one end of the pair of bit lines BL, respectively.

The temperature detector of FIG. 4 uses a CMOS circuit. In other words, the temperature detection circuit utilizes different temperature characteristics between the CMOS transistor and the resistor.

On the other hand, the temperature detector 21 of the present invention can be used when there is no external control pin, and if it is possible to apply a control signal from the outside, it is possible to apply a signal from the outside without using the temperature detector and the rest other than the temperature detector. You can also control the block.

5 controls the operation of the burst counter 24, the pattern generator 25, the self refresh unit 22, and the write operation 27 during the burn-in test. Let each block work.

Detecting that the word line on the self refresh is enabled / disabled, enable / disable the operation of the burst counter unit, and also internally generate a light command to light the pattern shown in FIG.

Each time the word line is newly enabled, the column address input to the burst counter section is initialized.

Meanwhile, as shown in FIG. 5, the controller includes a wordline detector 31, a column address initializer 32, a write command generator 33, and a write sense amplifier. It is made of a portion 34.

As described above, the burn-in test mode circuit according to the present invention has the following effects.

This means that burn-in tests can be performed in MML to increase product reliability, and there is no additional cost to embed a separate BIST to implement burn-in tests or to take out DRAM control pins out of the package. Do.

Claims (5)

In the burn-in test mode circuit of DRAM embedded in the packaged MML, A temperature detector for detecting a temperature of the package and outputting a burn-in signal when the temperature is above or below a predetermined temperature; A self-refresh unit which receives a burn-in signal whose temperature detected by the temperature detector is equal to or higher than a predetermined temperature and operates a sense amplifier while sequentially enabling word lines to refresh memory cells; A clock generator for generating a self refresh clock when the burn-in signal enters the self refresh unit in the temperature detector; A burst counter unit which receives a refresh signal of the self refresh unit and generates a column address; A pattern generator which receives the column address of the burst counter and generates write data; A control unit for controlling the burst counter unit, the pattern generator unit and the write operation during the burn-in test by outputting the burn-in signal of the temperature detector unit and initializing the column address input to the burst counter unit each time the word line is newly enabled. Burn-in test mode circuit comprising a. delete The burn-in test mode circuit according to claim 1, wherein the temperature detector uses different temperature characteristics between the plurality of CMOS transistors and the resistor. delete 2. The burn-in test mode circuit of claim 1, wherein the burst counter unit operates in a full page mode.