KR100392383B1 - A semiconductor chip having divisional bus - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a semiconductor chip having a bus circuit such as an embedded processor, and an object thereof is to provide a semiconductor chip capable of reducing power consumption of a bus circuit without increasing the chip area. The present invention provides a semiconductor chip having a plurality of functional blocks, comprising: a first bus to which one or more functional blocks are connected; a second bus to which one or more functional blocks are connected except for the functional blocks connected to the first bus; Drive means for driving said first and second buses.

Description

A semiconductor chip having divisional bus

The present invention relates to semiconductor technology, and more particularly to a semiconductor chip having a bus circuit, such as an embedded processor.

All embedded processors have a common signal line called a bus, which serves as an intermediary for communication between multiple functional blocks inside the processor. Therefore, whenever the signal transfer occurs, the bus repeats charging and discharging, and a lot of energy is required to charge / discharge the signal line. This is a major factor in power consumption.

Methods for reducing the power consumption of large scale integrated circuits have been studied in various ways. Improvements in the semiconductor design stage, reduction of power consumption through the improvement of the manufacturing process, and improvement of the efficiency of the application method at the system stage were mainly studied. Among them, there are five ways to reduce power consumption in semiconductor design. First, to reduce the supply voltage, second, to reduce the operating frequency, third, to reduce the area when designing drawings, fourth, to simplify the circuit through efficient circuit design, fifth, to use a completely different design techniques such as asynchronous circuit How to do it.

Recently, through the development of process technology, the device's operating voltage is drastically lowered from 5V to 3.3V, 2.0V, 1.8V, etc. to reduce power consumption. However, as the operating voltage is lowered, the speed becomes slow and the leakage current flows excessively, and various studies have been made to adjust the threshold voltage accordingly. However, lowering the operating voltage has the disadvantage that development of manufacturing technology must be preceded. On the other hand, the method of lowering the operating frequency has a great effect on the power consumption, but in view of the trend of increasingly high-performance and high-performance communication devices, lowering power consumption can cause various problems. For example, as the clock slows down, power consumption per unit clock decreases, but the execution time is longer for the same operation. Embedded communications processors serve a variety of purposes by combining a variety of basic circuits. Therefore, the power characteristics of the entire circuit can be improved by improving the performance and characteristics of the basic circuit to be used. Examples include low power clock generation methods and low power logic circuits. However, these methods also cannot achieve the power savings of the entire circuit without the consideration of low power in the integration of the respective functional blocks.

1 is a diagram illustrating a bus structure of a general embedded processor, including an arimatic logic unit (ALU) 1, a registry file 2, and a random access memory 3. , Functional blocks such as read-only memory (ROM) (4), parallel I / O (PIO) (5), timer (6), and universal asynchronous receiver / transmitter (UART) (7) 10. This structure has the advantages of simple implementation and simple control circuitry, while the load capacitance of the bus 10 is large, resulting in a decrease in speed and power consumption. .

As a technique to solve this problem, a partitioned-bus structure is adopted, and a method of dividing a bus line by providing a repeater having control inputs is proposed. The repeater consists of a bi-directional tri-state buffer, which is controlled by the control inputs to ensure that buslines that are not related to data transfer remain unchanged. Therefore, the entire bus line is prevented from being unnecessarily driven, and as a result, power consumption is reduced by reducing the frequency of switching the bus line.

Another method is variable-width-bus technology. This method is a concept of selectively driving bits of a bus line. That is, in the case of a 32-bit bus, the entire 32-bit bus is divided into several units to switch only the bus unit whose value is changed. This method can be implemented in various forms depending on the unit of bus division. Experiments have shown that it is most effective to divide it into 4 units of 8 bits each.

However, the prior art as described above has a disadvantage in that the chip area is increased by 30% or more.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a semiconductor chip capable of reducing power consumption of a bus circuit without increasing the chip area.

1 is a general bus structure diagram of a microcontroller.

2 is an equivalent circuit diagram of a bus circuit.

3 is a block diagram illustrating an embedded processor having a split bus structure according to an embodiment of the present invention.

4 is a circuit diagram of the driver cell of FIG. 3.

5 is a layout parameter extraction result when the actual circuit design by the method proposed in the present invention.

6 is an exemplary clocking diagram according to a bus separation structure.

* Explanation of symbols for the main parts of the drawings

30: bus A

31: bus B

36: driver cell

In order to achieve the above technical problem, the present invention provides a semiconductor chip including a plurality of functional blocks, wherein at least one function block except for a first bus to which at least one functional block is connected and a functional block to be connected to the first bus. And a second bus to which blocks are connected, and drive means for driving the first and second buses.

Preferably, a functional block having a relatively high intercommunication frequency is connected to the same bus.

Preferably, the driving means includes a first driver cell for driving the first bus and a second driver cell for driving the second bus.

Preferably, the second driver cell is controlled by an inverted clock of the enable clock of the first driver cell.

Preferably, the first and second driver cells each include a first three-phase inverter for driving the bus, a second three-phase inverter for receiving data from the bus, and latching an output of the second three-phase inverter. It has a latch for.

If the load on the bus is small, the bus is short, or the charge / discharge frequency is low, the energy required to drive the bus is reduced by that amount, resulting in reduced power consumption. The present invention proposes a separate bus structure that can reduce the number of gates directly connected to the bus in order to reduce the load on the bus.

The power consumption of the CMOS circuit, which occupies most of the electronic circuit, may be represented by Equation 1 below.

P = P _dynamic + P _short + P _leak + P _static

Here, P _dynamic is power consumption in the dynamic state and represents the power consumption by switching the CMOS gate, P _short represents power consumption by a short-circuit formed between power and ground, and P _leak is CMOS. P _static represents power consumption due to leakage current formed by the reverse bias between the source and the drain, and P _static represents power consumption in the electrostatic state that occurs when the gate output does not change.

In general, most of the power consumption is occupied by the _dynamic power consumption (P _dynamic ) can be expressed by the following equation (2).

P _dynamic = Cout × Vdd ² × F

That is, the dynamic power consumption P _dynamic is proportional to the load capacitance C _out of the bus and the switching frequency F of the gate, and is closely related to the power supply voltage Vdd. Since power supply voltage is related to manufacturing technology, it is not a designer's concern because it is not a part that can be changed during circuit design.

Accordingly, the present invention proposes a split bus structure in which the load capacitance C _out of the bus is reduced and the switching frequency F is reduced to reduce the dynamic power consumption P _dynamic .

2 is a diagram illustrating an equivalent circuit of a bus circuit, in which a bus driver circuit and a bus can be modeled simply by resistance and capacitance. That is, the sum Cgate of the input capacitances of the PMOS and the NMOS, the sum Csd of the junction capacitance between the PMOS and the source-drain of the NMMOS, and the resistance Rinv of the gate.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

3 is a block diagram of an embedded processor having a split bus structure according to an exemplary embodiment of the present invention.

The embedded processor according to the present embodiment includes a bus A 30 and a bus B 31, a CPU 32 connected to the bus A 30, a registry file 33, and a DRAM connected to the bus B 31. And a driver cell 36 for driving the bus A 30 and the bus B 31. That is, in the present invention, a plurality of functional blocks constituting the embedded processor are connected to two buses 30 and 31, and the bus A 30 has a CPU 32 and a registry file 33 having high data transfer rates. ) Is connected to use the same bus, and the remaining functional blocks of relatively low communication frequency are connected to bus B31.

4 is a circuit diagram of the driver cell of FIG. 3, wherein the driver cell 40 includes a bus driver for driving bus B and an input latch for receiving data from bus B. As shown in FIG. A three-phase inverter 41 is used as a bus driver, and a latch composed of a three-phase inverter 42 and two inverters 43 and 44 is used as an input latch. The driver cell for driving the bus A also has the above configuration.

The embedded processor of the present invention configured as described above has the following advantages. First, the load capacitance of the bus is reduced. The separation of the bus dramatically reduces the number of fan-outs connected to the bus, which in turn reduces the input capacitance of the entire gate. Second, the load capacitance of the bus is reduced, which drastically reduces the size of the driver circuit for driving the bus. Each functional block connected to the bus has its own driver circuit to drive the bus, whose size matches the driving capability of the bus. If the load capacitance of the bus is small, the driving capability of the driver circuit is improved, and thus the circuit size is reduced.

Table 1 below is prepared for the difference between the conventional bus (common bus) and the bus (divided bus) structure according to an embodiment of the present invention.

Common bus Split bus Number of buses One 2 Switching frequency 460 370/280 Load capacitance 1840Cgate + 1840Csd 1580Cgate + 1670Csd Equivalent capacitance 20240Csd 17579Csd

Referring to Table 1, it can be seen that the load capacitance (equivalent) of the bus is greatly reduced by dividing the bus. All bus structures can be changed to a switching model according to the equivalent circuit of FIG. 2, and load capacitance can be obtained by the same switching model. As a result, it can be seen that the split bus structure of the present invention has a smaller capacitance value than the conventional common bus structure despite the increase in the number of buses. On the other hand, in the calculation of Table 1, the gate capacitance (Cgate) of the transistor is assumed to be 10 times the junction capacitance (Csd), but in general, the difference appears to be much larger in the semiconductor process. Therefore, the effect of bus division can be greater.

5 is a diagram illustrating a layout parameter extraction result when an actual circuit design is performed by the method proposed in the present invention. The load capacitance value of the bus was extracted in the circuit design state. The result is almost identical to the value previously calculated by the switching model (see Table 1). It can be seen that the capacitance loaded on the two divided buses is less than that of the conventional one bus.

On the other hand, when data transfer between separate buses is required, the delay time is long because two buses must pass. This problem can be solved by modifying the bus clocking method. The smaller the load capacitance of the bus, the easier it is to drive the bus and the shorter the time required to drive the bus. That is, since the time required for the bus to complete charge / discharge is shortened, even if the bus enable time is short, sufficient charge / discharge can be achieved. Therefore, even when the bus is divided into two, as shown in FIG. 6, the two buses can be driven during one clock cycle as in the related art. For example, a split bus B enable clock is used as a control input of the three-phase inverter 41 of FIG. 4, and a driver cell for a bus A (not shown) is controlled by the split bus A enable clock.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

For example, in the above-described embodiment, the embedded processor has been described as an example, but the bus structure of the present invention can be applied to other semiconductor chips.

In addition, in the above-described embodiment, the case where the bus is divided into two has been described as an example, but the present invention can also be applied to the case where the bus is divided into three or more.

The present invention described above can significantly reduce the load capacitance of the bus due to the bus separation and reduce the size of the bus driver circuit, thereby greatly reducing the dynamic power consumption of the entire circuit. In addition, the present invention can lower the switching frequency of the bus required for the same performance, and can increase the operating frequency of the bus at the same power consumption, thereby improving the performance of the entire circuit.

Claims (5)

In a semiconductor chip having a plurality of functional blocks, A first bus to which one or more functional blocks are connected; A second bus to which one or more functional blocks are connected except for the functional blocks connected to the first bus; And Drive means for driving the first and second buses A semiconductor chip comprising a. The method of claim 1, A semiconductor chip characterized by connecting a functional block having a relatively high mutual communication frequency to the same bus. The method of claim 1, The drive means, A first driver cell for driving the first bus, And a second driver cell for driving the second bus. The method of claim 3, The second driver cell, And controlled by an inverted clock of an enable clock of the first driver cell. The method of claim 3, The first and second driver cells, respectively A first three-phase inverter for driving the bus, A second three-phase inverter for receiving data from the bus, And a latch for latching the output of the second three-phase inverter.