KR100389742B1 - Device for compensating frequency abnormal gps receiver in imt-2000 bsc system - Google Patents

Abstract

The present invention relates to a frequency compensator in case of an abnormal GPS receiver in an IMT-2000 control station system, and more particularly, when an abnormality occurs in the output of the system clock due to a failure of a GPS receiver or a node that supplies a system clock. The present invention relates to a frequency compensation device in case of a GPS receiver abnormality in an IMT-2000 control station system that enables 10 MHz frequency compensation. According to the present invention, a frequency compensation device in case of a GPS receiver abnormality in an IMT-2000 control station system is provided. In case of an abnormality, it not only secures the frequency of 10MHz, but also maintains the hold over function of the GPS receiver, thereby providing a higher quality service to users by supplying a stable system clock.

Description

Frequency compensation device in case of abnormal GPS receiver in IMT-2000 control station system {DEVICE FOR COMPENSATING FREQUENCY ABNORMAL GPS RECEIVER IN IMT-2000 BSC SYSTEM}

The present invention relates to a frequency compensation device in case of an abnormal receiver of a Global Positioning System (GPS) in a system of an International Mobile Telecommunication (IMT) -2000 control station. The present invention relates to a frequency compensation device in case of a GPS receiver failure in an IMT-2000 control station system that enables 10 MHz frequency compensation through its own board when an abnormality occurs in the output of the system clock due to an abnormal GPS receiver or a node failure. .

In the conventional mobile communication control station system, the GPS frequency providing apparatus includes four GPS clocks (GPSA10M +,-) from a GPS receiver that receives a 1PPS reference clock from a GPS satellite and generates a clock of 10 MHz by itself. GPS clock level converter (1) which receives GPSB10M +,-; GPSAPPS +,-; GPSBPPS +,-and simultaneously converts the levels of the four GPS clocks, GPS clocks (GPSA10M, GPSB10M) from the GPS clock level converter (1). , GPSAPPS, GPSBPPS) and at the same time the corresponding SCGA10M, and outputs the SCGAPPS mux (2), and receives the SCGA10M, and SCGAPPS from the mux (2) and simultaneously control the corresponding system clock of 10MHz It is composed of TSB blocks (3) that output to all domestic boards

However, in case of supplying the system clock using the conventional GPS frequency providing apparatus in the mobile communication control station system as described above, if the GPS clock is disconnected from the GPS receiver, it is not compensated for and the frame offset (8KHz) from the exchange. ) To generate the required clock group by generating it in the TSB block, but there was a problem that a hand off occurs as the clock source is switched to its own network in the lower stage.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to ensure a more stable frequency of 10 MHz even when a GPS receiver malfunctions. The present invention provides a frequency compensation device in case of a GPS receiver failure in an IMT-2000 control station system for providing high service.

In order to achieve the above object, the GPS receiver in the IMT-2000 control station system of the present invention has four GPS clocks from a GPS receiver that receives a 1PPS reference clock from a GPS satellite and generates a clock of 10 MHz by itself. A GPS clock level converter which converts the levels of the four GPS clocks at the same time as receiving the input;

When the GPS clock is input from the GPS clock level converter, the corresponding GPS10MPLD, OCXO10MPLD, GPS10M, and GPSPPS are output. ;

Upon receiving the GPS10M and GPSPPS from the MUX, the system clock outputs the corresponding 10 MHz system clock to all the boards in the control station, while the SCGA10M and the SCGAPPS input from the MUX are outputted to the corresponding system clocks of the 10 MHz. TSB block output to the board;

The reference frequency clock (GPS10MPLD) and the comparison frequency clock (OCXO10MPLD) are inputted from the mux, the reference frequency clock (GPS10MPLD) and the comparison frequency clock (OCXO10MPLD) are compared, and the corresponding phase difference is converted into a voltage value (PD_OUT). Output to PLL;

An analog / digital converter for receiving a voltage value PD_OUT from the PLL and converting the voltage value PD_OUT into a digital signal;

A memory configured to receive a digital signal from the analog / digital converter and simultaneously store the digital signal;

A digital / analog converter configured to receive a stored digital signal from the memory and convert the digital signal into an analog signal; And

An oscillator (0CXO) for receiving an analog signal from the digital / analog converter and outputting the corresponding OCXO10M to the mux.

1 is a functional block diagram showing the configuration of a conventional GPS frequency providing apparatus in a mobile communication control station system;

FIG. 2 is a functional block diagram showing the configuration of a frequency compensating device in the event of a GPS receiver failure in an IMT-2000 control station system according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: GPS Clock Level Converter 200: MUX

300: TSB Block 400: PLL

500: analog-to-digital converter 600: memory

700: digital-to-analog converter 800: oscillator

Hereinafter, an apparatus for compensating for a GPS receiver in an IMP-2000 control station system according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a functional block diagram of a frequency compensation device in an IMT-2000 control station system according to an embodiment of the present invention. FIG. 2 is a functional block diagram of a WPS receiver in an IMT-2000 control station system according to an embodiment of the present invention. The frequency compensating device includes a GPS clock level converter 100, a muxer 200, a TSB (Transcode Selector Bank) block 300, a PLL (Phase Loop Lock). 400), an analog to digital converter 500, a memory 600, a digital to analog converter 700, and an oscillator (0CXO) 800. .

The GPS clock level converter 100 receives four GPS clocks (GPSA10M +,-; GPSB10M +,-; GPSAPPS +,-; and GPSBPPS +,-) from a GPS receiver that receives a 1PPS reference clock from a GPS satellite and generates a clock of 10 MHz. ) And at the same time converts the levels of the four GPS clocks to output to the mux (200).

Meanwhile, when the MUX 200 receives four GPS clocks GPSA10M, GPSB10M, GPSAPPS, and GPSBPPS from the GPS clock level converter 100, the mux 200 outputs corresponding GPS10MPLD and OCXO10MPLD to the PLL 400. , GPS10M, and GPSPPS are output to the TSB block 300, and if the four GPS clocks (GPSA10M, GPSB10M, GPSAPPS, and GPSBPPS) are not received from the GPS clock level converter 100, the corresponding SCGA10M, and Outputs SCGAPPS to the TSB block 300.

At this time, the TSB block 300 receives the GPS10M and the GPSPPS from the mux 200 and simultaneously outputs a system clock of 10 MHz corresponding to all the boards in the control station, and also the mux 200. When SCGA10M and SCGAPPS are inputted, the corresponding 10MHz system clock is outputted to all boards in the control station.

In addition, the PLL 400 receives a reference frequency clock GPS10MPLD and a comparison frequency clock OCXO10MPLD from the mux 200 and compares the reference frequency clock GPS10MPLD with a comparison frequency clock OCXO10MPLD. Thereafter, a voltage value PD_OUT indicating a phase difference corresponding thereto is output to the analog-to-digital converter 500.

Meanwhile, the analog-to-digital converter 500 receives a voltage value PD_OUT indicating a phase difference from the PLL 400 and simultaneously converts the voltage value PD_OUT into a digital signal and stores the voltage value PD_OUT in a digital signal. Play a role.

The memory 600 receives and stores a digital signal from the analog-to-digital converter 500 and provides the stored digital signal to the digital-to-analog converter 700.

Meanwhile, the digital-to-analog converter 700 receives a digital signal stored from the memory 600 and simultaneously converts the digital signal into an analog signal and outputs the analog signal to the oscillator (0CXO) 800.

The oscillator (0CXO) 800 receives an analog signal from the digital / analog converter 700 and simultaneously outputs the corresponding OCXO10M to the mux 200.

Next, a description will be given of a frequency compensating device in the event of a GPS receiver failure in an IMT-2000 control station system having the above configuration.

First, the GPS clock level converter 100 receives four GPS clocks (GPSA10M +,-; GPSB10M +,-; GPSAPPS +,-and GPSBPPS +,-) from a GPS receiver and simultaneously converts the levels of the four GPS clocks ( ELC level to TTL level) and output to the mux (200).

Then, the MUX 200 receives four GPS clocks GPSA10M, GPSB10M, GPSAPPS, and GPSBPPS from the GPS clock level converter 100 and outputs corresponding GPS10MPLD and OCXO10MPLD to the PLL 400. Simultaneously, GPS10M and GPSPPS are output to the TSB block 300. At this time, GPS10MPLD is a clock coming from GPS, and OCXO10MPLD is an output clock value of the oscillator (OCXO) 800.

Subsequently, the TSB block 300 receives GPS10M and GPSPPS from the MUX 200 and simultaneously outputs a system clock of 10 MHz corresponding to all boards in the control station.

The PLL 400 receives a reference frequency clock GPS10MPLD and a comparison frequency clock OCXO10MPLD from the MUX 200, and compares the reference frequency clock GPS10MPLD with a comparison frequency clock OCXO10MPLD. After that, the voltage value PD_OUT indicating the corresponding phase difference is output to the analog-to-digital converter 500. At this time, if the phase of the comparison frequency clock (OCXO10MPLD) is behind the reference frequency clock (GPS10MPLD), the voltage value is increased, if the phase of the comparison frequency clock (OCXO10MPLD) is faster than the reference frequency clock (GPS10MPLD) voltage value This goes down.

Then, the analog-to-digital converter 500 receives a voltage value PD_OUT indicating a phase difference from the PLL 400, and simultaneously converts the voltage value PD_OUT into a digital signal and stores it in the memory 600. .

Here, the analog-to-digital converter 500 will be described in more detail. When the voltage value PD_OUT (between 0 and 5 Volt) is received from the PLL 400, the voltage value is coded into a binary value of 16 bits. do. For example, when 0V is input as an input voltage value, the output data is output as (0000 0000 0000 0000) and stored at a specific address of the memory 600, and when an intermediate voltage value (+ 2.5V) is input, the output data is output. The data is output as (1000 0000 0000 0000) and written to the memory 600.

At this time, the memory 600 receives and stores a digital signal from the analog-to-digital converter 500 and simultaneously provides the stored digital signal to the digital-to-analog converter 700.

Subsequently, the digital-to-analog converter 700 receives a digital signal stored from the memory 600 and simultaneously converts the digital signal into an analog signal and outputs the digital signal to the oscillator (0CXO) 800.

Then, the oscillator (0CXO) 800 receives an analog signal including a phase difference between the reference frequency clock (GPS10MPLD) and the comparison frequency clock (OCXO10MPLD) from the digital / analog converter 700 and includes a phase difference thereof. The OCXO10M compensating for the difference in phase difference using an analog signal is generated and output to the MUX 200.

On the other hand, when the mux 200 does not receive four GPS clocks (GPSA10M, GPSB10M, GPSAPPS, and GPSBPPS) from the GPS clock level converter 100, the output clock value of the OCXO10M received from the oscillator 800 SCGA10M and SCGAPPS are generated using the same and output to the TSB block 300.

Thereafter, the TSB block 300 receives the SCGA10M and the SCGAPPS from the MUX 200 and outputs a corresponding system clock of 10 MHz to all the boards in the control station.

As in the above-described operation, the frequency compensation apparatus in the event of a WPS receiver failure in the IMT-2000 control station system according to an embodiment of the present invention can be applied to all fields using the system clock as well as the IMT-2000 control station system.

As described above, according to the present invention, the frequency compensation device in case of a GPS receiver abnormality in the IMT-2000 control station system provides an error in the output of the system clock due to an abnormality of the GPS receiver supplying the system clock or a node failure. By enabling 10MHz frequency compensation through the board, it ensures the maximum 10MHz frequency even in case of GPS receiver failure, and maintains the hold over function of the GPS receiver, thereby providing a stable system clock. Through this, there is an excellent effect that it can provide higher quality service to users.

Claims (1)

A GPS clock level converter which receives a 1PPS reference clock from a GPS satellite and receives four GPS clocks from a GPS receiver that generates a clock of 10 MHz and simultaneously converts the levels of the four GPS clocks; When the GPS clock is input from the GPS clock level converter, the corresponding GPS10MPLD, OCXO10MPLD, GPS10M, and GPSPPS are output. ; Upon receiving the GPS10M and GPSPPS from the MUX, the system clock outputs the corresponding 10 MHz system clock to all the boards in the control station, while the SCGA10M and the SCGAPPS input from the MUX are outputted to the corresponding system clocks of the 10 MHz. TSB block output to the board; The reference frequency clock (GPS10MPLD) and the comparison frequency clock (OCXO10MPLD) are received from the mux, and the reference frequency clock (GPS10MPLD) is compared with the comparison frequency clock (OCXO10MPLD), and the corresponding phase difference is converted into a voltage value (PD_OUT). Output to PLL; An analog / digital converter for receiving a voltage value PD_OUT from the PLL and converting the voltage value PD_OUT into a digital signal; A memory configured to receive a digital signal from the analog / digital converter and simultaneously store the digital signal; A digital / analog converter configured to receive a stored digital signal from the memory and convert the digital signal into an analog signal; And And an oscillator (0CXO) configured to receive an analog signal from the digital-to-analog converter and output the corresponding OCXO10M to the mux.