KR100388473B1 - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR100388473B1 KR100388473B1 KR10-2000-0087660A KR20000087660A KR100388473B1 KR 100388473 B1 KR100388473 B1 KR 100388473B1 KR 20000087660 A KR20000087660 A KR 20000087660A KR 100388473 B1 KR100388473 B1 KR 100388473B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 title claims description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 38
- 239000010410 layer Substances 0.000 claims abstract description 37
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 29
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 9
- 239000011229 interlayer Substances 0.000 claims abstract description 7
- 230000004888 barrier function Effects 0.000 claims abstract description 6
- 238000004140 cleaning Methods 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 10
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 7
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 3
- 230000002265 prevention Effects 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 239000002245 particle Substances 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/1469—Assemblies, i.e. hybrid integration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
본 발명은 암배드 화소(Dark bad pixel)의 오류에 대한 저항성이 우수한 이미지센서의 제조 방법에 관한 것으로, 이를 위한 본 발명은 반도체기판상에 다수의 게이트전극을 형성하는 단계, 상기 게이트전극을 포함한 반도체 기판상에 실리사이드방지막을 형성하는 단계, 상기 실리사이드방지막상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 상기 반도체기판의 소정 부분을 노출시키는 단계, 상기 노출된 반도체기판의 표면을 전세정하는 단계, 상기 노출된 반도체기판에 금속실리사이드막을 형성하는 단계, 상기 실리사이드막을 제거하는 단계, 상기 층간절연막을 선택적으로 식각하여 상기 금속실리사이드막이 포함된 금속콘택영역을 오픈시키는 단계, 및 상기 금속실리사이드막에 접속되는 금속콘택을 형성하는 단계를 포함하여 이루어진다.The present invention relates to a method of manufacturing an image sensor excellent in resistance to errors of a dark bad pixel, the present invention for forming a plurality of gate electrodes on a semiconductor substrate, including the gate electrode Forming a silicide barrier layer on the semiconductor substrate, applying a photoresist layer on the silicide barrier layer, and patterning the photosensitive layer by exposure and development to expose a predetermined portion of the semiconductor substrate, pre-cleaning the surface of the exposed semiconductor substrate; Forming a metal silicide film on an exposed semiconductor substrate, removing the silicide film, selectively etching the interlayer insulating film to open a metal contact region including the metal silicide film, and a metal connected to the metal silicide film Forming a contact.
Description
본 발명은 이미지센서의 제조 방법에 관한 것으로서, 특히 배드 화소(Bad pixel)에 대한 저항성(Immunity)을 개선시키도록 한 이미지센서의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an image sensor, and more particularly, to a method of manufacturing an image sensor to improve immunity to a bad pixel.
일반적으로 CMOS 이미지센서(Image sensor)의 단위셀(Unit cell)은 포토다이오드(PhotoDiode) 및 4개의 NMOS 트랜지스터를 포함하는 단위화소로 이루어지며, 특히 640*480, 800*600모드의 셀어레이 또는 메가화소(Mega pixel)로 갈수록 좁은 단면적을 가지는 단위셀의 설계와 이에 적절하게 영상정보를 정확하고 빠르게 읽을 수 있는 칩을 설계해야만 한다.In general, a unit cell of a CMOS image sensor is composed of a unit pixel including a photodiode and four NMOS transistors, in particular, a cell array or a mega array of 640 * 480 and 800 * 600 modes. As the pixel goes to the pixel, it is necessary to design a unit cell having a narrow cross-sectional area and a chip capable of reading image information accurately and quickly accordingly.
도 1은 통상적인 CMOS 이미지센서의 단위화소(Unit Pixel)를 나타낸 등가회로도로서, 하나의 포토다이오드(PD)와 네 개의 NMOS(Tx,Rx,Sx,Dx)로 구성되며, 상기 네 개의 NMOS(Tx,Rx,Sx,Dx)는 상기 포토다이오드(PD)에서 집속된 광전하(Photo-generated charge)를 플로팅디퓨젼영역(Floating Diffusion; FD)으로 운송하기 위한 트랜스퍼트랜지스터(Transfer transistor; Tx), 원하는 값으로 노드의 전위를 세팅하고 전하(Cpd)를 배출하여 플로팅디퓨젼영역(FD)을 리셋(Reset)시키기 위한 리셋트랜지스터(Reset transistor; Rx), 소오스팔로워-버퍼증폭기(Source Follower Buffer Amplif ier) 역할을 하는 드라이브트랜지스터(Drive transisor; Dx), 스위칭으로 어드레싱(Addressing)을 할 수 있도록 하는 셀렉트트랜지스터(Select transistor; Sx)로 구성된다.FIG. 1 is an equivalent circuit diagram illustrating a unit pixel of a conventional CMOS image sensor, and includes one photodiode PD and four NMOSs (Tx, Rx, Sx, and Dx). Tx, Rx, Sx, and Dx are transfer transistors (Tx) for transporting photo-generated charges concentrated in the photodiode (PD) to a floating diffusion region (FD), Reset transistor (Rx), source follower buffer amplifier (Source Follower Buffer Amplif) to reset the floating diffusion region (FD) by setting the potential of the node to the desired value and discharging the charge (C pd ) It consists of a drive transistor (Dx) that acts as an ier, and a select transistor (Sx) that allows addressing by switching.
여기서 상기 트랜스퍼트랜지스터(Tx) 및 리셋트랜지스터(Rx)는 네이티브트랜지스터(Native NMOS)를 이용하고 상기 드라이브트랜지스터(Dx) 및 셀렉트트랜지스터(Sx)는 일반적인 트랜지스터(Normal NMOS)를 이용하며, 리셋트랜지스터(Rx)는 CDS(Correlated Double Sampling)를 위한 트랜지스터이다.Here, the transfer transistor Tx and the reset transistor Rx use a native transistor (Native NMOS), the drive transistor Dx and the select transistor Sx use a common transistor (Normal NMOS), and a reset transistor (Rx). ) Is a transistor for correlated double sampling (CDS).
상기와 같은 종래기술의 이미지센서의 단위화소(Unit Pixel)는 네이티브트랜지스터(Native Transistor)를 사용하여 포토다이오드영역(PD)에서 가시광선파장대역의 광을 감지한 후 감지된 광전하(Photogenerated charge)를 플로우팅디퓨전영역(FD)으로, 즉 드라이브트랜지스터(Dx)의 게이트로 전달한 양을 출력단(Vout)에서 전기적신호로 출력한다.The unit pixel of the image sensor of the prior art as described above is a photogenerated charge detected after detecting light in the visible wavelength band in the photodiode region PD using a native transistor. The amount transferred to the floating diffusion region FD, that is, the gate of the drive transistor Dx, is output as an electrical signal at the output terminal Vout.
도 2는 CMOS 이미지센서의 개략적 평면도로서, CMOS 이미지센서를 이루는 활성층(11)에 접합되는 3개의 콘택(Active CT) 예컨대, VDD 콘택(12), 리셋트랜지스터(Rx)콘택(13) 또는 플로우팅디퓨젼(FD) 콘택, 셀렉트트랜지스터(Sx) 콘택(14)이 폴리실리콘 콘택(Polysilicon)에 비해 취약한 특성을 보임에 따라 암배드 화소가 유발되는 것으로 추정된다.FIG. 2 is a schematic plan view of a CMOS image sensor, in which three active (CT) contacts, such as a VDD contact 12, a reset transistor (Rx) contact 13, or a floating device bonded to an active layer 11 forming a CMOS image sensor are shown in FIG. It is assumed that the fusion (FD) contact and the select transistor (Sx) contact 14 exhibit weak characteristics as compared to the polysilicon contact, thereby causing the dark pixel.
CMOS 이미지센서의 암배드화소(dark bad pixel)의 주요 원인은 배리어메탈과 알루미늄으로 이루어지는 금속콘택의 갭필 불량에 의해 유발되고, 소자격리 정의후 활성층상에 존재하는 큰 크기의 파티클(Particle)로 인한 활성층과 금속콘택 계면 접촉 불량에 의해 발생된다. 또한, 금속콘택홀의 오픈 불량에 의해서도 유발된다.The main cause of dark bad pixels in CMOS image sensors is caused by gap fill defects in metal contacts made of barrier metal and aluminum, and due to the large particles present on the active layer after device isolation. It is caused by poor contact between the active layer and the metal contact interface. In addition, it is caused by the open failure of the metal contact hole.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 활성층과 금속콘택간의 계면 저항 증가로 인한 암배드 화소를 억제하는데 적합한 이미지센서의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the prior art, and an object of the present invention is to provide a method of manufacturing an image sensor suitable for suppressing the dark pixel due to the increase in the interface resistance between the active layer and the metal contact.
도 1은 통상적인 이미지센서의 등가회로도,1 is an equivalent circuit diagram of a conventional image sensor,
도 2는 이미지센서의 개략적 평면도,2 is a schematic plan view of an image sensor;
도 3a 내지 도 3e는 본 발명의 실시예에 따른 이미지센서의 제조 방법을 도시한 도면.3A to 3E illustrate a method of manufacturing an image sensor according to an exemplary embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : 게이트산화막21 semiconductor substrate 22 gate oxide film
23 : 게이트전극 24 : 스페이서23: gate electrode 24: spacer
25 : 질화막 26 : 감광막패턴25 nitride film 26 photosensitive film pattern
27 : 티타늄실리사이드 28/29 : TEOS/BPSG27: titanium silicide 28/29: TEOS / BPSG
30 : 금속콘택30: metal contact
상기의 목적을 달성하기 위한 본 발명의 이미지센서의 제조 방법은 반도체기판상에 다수의 게이트전극을 형성하는 단계, 상기 게이트전극을 포함한 반도체 기판상에 실리사이드방지막을 형성하는 단계, 상기 실리사이드방지막상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 상기 반도체기판의 소정 부분을 노출시키는 단계, 상기 노출된 반도체기판의 표면을 전세정하는 단계, 상기 노출된 반도체기판에 금속실리사이드막을 형성하는 단계, 상기 실리사이드막을 제거하는 단계, 상기 반도체기판의 전면에 층간절연막을 형성하는 단계, 상기 층간절연막을 선택적으로 식각하여 상기 금속실리사이드막이 포함된 금속콘택영역을 오픈시키는 단계, 및 상기 금속실리사이드막에 접속되는 금속콘택을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.Method of manufacturing an image sensor of the present invention for achieving the above object comprises the steps of forming a plurality of gate electrodes on a semiconductor substrate, forming a silicide prevention film on a semiconductor substrate including the gate electrode, on the silicide prevention film Exposing a predetermined portion of the semiconductor substrate by applying a photoresist film and patterning by exposure and development, pre-cleaning the surface of the exposed semiconductor substrate, forming a metal silicide film on the exposed semiconductor substrate, removing the silicide film Forming an interlayer insulating film on the entire surface of the semiconductor substrate; selectively etching the interlayer insulating film to open a metal contact region including the metal silicide film; and forming a metal contact connected to the metal silicide film. Characterized in that it comprises a step do.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 3a 내지 도 3e는 본 발명의 실시예에 따른 이미지센서의 제조 방법을 도시한 도면으로서, 활성층에 접속되는 콘택의 형성 방법을 도시하고 있다.3A to 3E illustrate a method of manufacturing an image sensor according to an exemplary embodiment of the present invention, which illustrates a method of forming a contact connected to an active layer.
도 3a에 도시된 바와 같이, 반도체기판(21)상에 게이트산화막(22)을 형성하고, 게이트산화막(22)상에 폴리실리콘을 증착한 후, 폴리실리콘을 선택적으로 패터닝하여 다수의 게이트전극(23)을 형성하는데, 이 때, 게이트전극(23)은 트랜스퍼트랜지스터(Tx), 리셋트랜지스터(Rx), 드라이브트랜지스터(Dx)의 게이트전극으로 이용된다.As shown in FIG. 3A, a gate oxide film 22 is formed on the semiconductor substrate 21, polysilicon is deposited on the gate oxide film 22, and then polysilicon is selectively patterned to form a plurality of gate electrodes. At this time, the gate electrode 23 is used as the gate electrode of the transfer transistor Tx, the reset transistor Rx, and the drive transistor Dx.
계속해서, 게이트전극(23)을 포함한 전면에 측벽용 절연막을 증착 및 전면식각하여 게이트전극(23)의 양측벽에 접하는 스페이서(24)를 형성한 다음, 전면에 질화막(25)을 증착한다. 여기서, 질화막(25)은 후속 선택적 실리사이드 공정(Slective Silicide Process)을 진행할 때 실리사이드가 형성되지 않아야 할 보호하기 위한 막으로 작용하며, 질화막(25)외에 BPSG(Boro Phospho Silicate Glass)를 이용할 수 있다.Subsequently, a sidewall insulating film is deposited and etched on the entire surface including the gate electrode 23 to form a spacer 24 in contact with both sidewalls of the gate electrode 23, and then a nitride film 25 is deposited on the entire surface. Here, the nitride film 25 serves as a protective film to prevent silicide not to be formed when a subsequent selective silicide process is performed. In addition to the nitride film 25, BPSG (Boro Phospho Silicate Glass) may be used.
도 3b에 도시된 바와 같이, 질화막(25)상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 실리사이드막이 형성될 부분을 노출시키는 감광막패턴(26)을 형성하고, 감광막패턴(26)을 마스크로 이용하여 하부의 질화막(25)을 식각하여 반도체기판(21)의 활성층을 소정 부분 노출시킨다.As shown in FIG. 3B, a photoresist film is coated on the nitride film 25 and patterned by exposure and development to form a photoresist pattern 26 exposing a portion where a silicide film is to be formed, and using the photoresist pattern 26 as a mask. The lower nitride film 25 is etched to expose a predetermined portion of the active layer of the semiconductor substrate 21.
이 때, 감광막패턴(26)을 이용한 식각 공정은 플로우팅디퓨전(FD) 및 리셋트랜지스터의 콘택과 VDD 콘택이 정의될 영역을 노출시키는 것으로 이러한 패터닝 공정을 통해 티타늄실리사이드(Ti-Silicide)화 시킬 활성층, 즉 금속콘택영역을 노출시킨다.At this time, the etching process using the photoresist pattern 26 exposes the region of the floating diffusion (FD) and the reset transistor and the region where the VDD contact is to be defined, and the active layer to be formed of titanium silicide (Ti-Silicide) through this patterning process. That is, the metal contact region is exposed.
도 3c에 도시된 바와 같이, 감광막패턴(26)을 제거하고 노출된 활성층 표면을 전세정(Precleaning)을 실시하여 산화막 성분의 잔막 또는 파티클 성분을 제거한다. 전술한 것처럼, 활성층과 금속콘택 계면 저항을 증가시키는 파티클이나 잔막은 대부분 산화막(Oxide) 계열로, 이러한 전세정을 통해 암배드 화소 페일(dark bad pixel Fail)을 유발시킬 수 있는 활성층상의 잔막 또는 파티클 역시 제거된다.As shown in FIG. 3C, the photoresist pattern 26 is removed and the exposed active layer surface is precleaned to remove the residual film or the particle component of the oxide film component. As described above, the particles or residual film which increases the interface resistance of the active layer and the metal contact are mostly oxide-based, and the residual film or particles on the active layer which can cause dark bad pixel fail through this pre-cleaning. It is also removed.
전세정 실시후, 실리사이드 공정을 실시하는데 실리사이드 공정은, 감광막패턴(26)이 제거된 후 노출된 질화막(25)상에 티타늄(31)을 증착한 후 소정 열처리를 실시하여 활성층과 티타늄(31)의 반응으로 활성층 표면에 티타늄실리사이드(27)를 형성한다. 이 때, 통상 진행되는 실리사이드공정과는 다르게 선택적으로 노출된 부분에만 티타늄실리사이드막(27)이 형성되며, 게이트전극(23) 상부에는 질화막(25)이 잔류하므로 실리사이드화 반응이 일어나지 않는다.도 3d에 도시된 바와 같이, 미반응 티타늄(31)을 제거한 후 질화막(25)을 제거한다.After performing pre-cleaning, a silicide process is performed. In the silicide process, after the photoresist layer pattern 26 is removed, the titanium layer 31 is deposited on the exposed nitride layer 25 and subjected to a predetermined heat treatment, thereby performing the active layer and the titanium 31. The reaction forms a titanium silicide 27 on the surface of the active layer. At this time, unlike the conventional silicide process, the titanium silicide layer 27 is formed only on the portions selectively exposed, and the nitride layer 25 remains on the gate electrode 23, so that no silicide reaction occurs. As shown in FIG. 5, the nitride film 25 is removed after the unreacted titanium 31 is removed.
도 3e에 도시된 바와 같이, 전면에 TEOS(Tetra Ethyl Ortho Silicate)(28), BPSG(29)를 증착한 후, BPSG(29)를 플로우(Flow)시켜 평탄화한다. 이 때, TEOS/BPSG(28/29)를 이용하므로 게이트전극(23)간 갭필(gap-fill)이 충분히 이루어지도록 한다.As illustrated in FIG. 3E, after the TEOS (Tetra Ethyl Ortho Silicate) 28 and the BPSG 29 are deposited, the BPSG 29 is flowed to planarize. At this time, since the TEOS / BPSG 28/29 is used, a gap fill between the gate electrodes 23 is sufficiently achieved.
후속 금속콘택 공정을 실시하여 금속콘택(30)을 형성하는데, TEOS/BPSG(28/29)를 습식 및 건식 식각하여 금속콘택영역을 오픈시킨 다음, 오픈된 영역에 금속콘택(30)을 매립시킨다. 이 때, 습식식각 및 건식식각을 순차적으로 진행하므로써 후속 금속콘택(30)용 전도막 증착시 매립이 우수하다.The metal contact 30 is formed by performing a subsequent metal contact process. The metal contact region is opened by wet and dry etching the TEOS / BPSG 28/29, and then the metal contact 30 is embedded in the open region. . At this time, since the wet etching and the dry etching are sequentially performed, the filling of the conductive film for the subsequent metal contact 30 is excellent.
이처럼 금속콘택(30) 하부에 티타늄실리사이드막(27)이 형성되므로 금속콘택과 반도체기판(21)의 활성층간의 계면저항을 감소시킬 수 있다..As such, since the titanium silicide layer 27 is formed under the metal contact 30, the interface resistance between the metal contact and the active layer of the semiconductor substrate 21 may be reduced.
본 발명은 0.5㎛급 로직 공정 즉, 텅스텐실리사이드(WSi), 습식과 건식으로 이루어지는 금속콘택 식각을 적용하는 다른 소자에서도 금속콘택의 갭필 특성 향상이나, 활성층 상에 존재할지 모르는 큰 크기의 잔막 또는 파티클이 금속콘택 및 활성층 계면에 영향을 미치지 못하도록 방지하기 위한 목적으로 용이하게 적용 가능하다.The present invention improves the gap fill characteristics of metal contacts or other large residual films or particles that may be present on the active layer even in other devices that apply 0.5 μm-class logic processes, that is, tungsten silicide (WSi) and wet and dry metal contact etching. The present invention can be easily applied for the purpose of preventing the metal contact and the active layer from affecting the interface.
아울러, 0.35㎛급 이미지센서에서도 적용 가능하다.In addition, it can be applied to 0.35㎛ image sensor.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명은 금속콘택 식각시 비교적 큰 크기의 파티클로 인한 금속콘택의 부분적 오픈 불량이나 접촉불량, 갭필 불량 등을 방지할 수 있는 효과가 있다.As described above, the present invention has an effect of preventing partial open defects, poor contact, gap fill defects, etc. of the metal contacts due to particles of a relatively large size when the metal contacts are etched.
또한, 활성층과 금속콘택의 계면저항을 감소시킬 수 있으며, 콘택저항이 충분히 감소되므로 공정 변화에 따른 콘택저항 변화에 대한 칩의 공정 마진을 증가시킬 수 있는 효과가 있다.In addition, since the interface resistance between the active layer and the metal contact can be reduced, and the contact resistance is sufficiently reduced, there is an effect of increasing the process margin of the chip for the change in contact resistance according to the process change.
그리고, 폴리실리콘 영역을 제외한 활성층 영역만 선택적으로 실리사이드화 시키므로써 일반적인 실리사이드 공정에서 유발될수 있는 활성층과 폴리실리콘간 브릿지를 억제시킬수 있으며, 일련의 선택적 실리사이드 공정에 의해 암배드화소의 오류율을 감소시켜 이미지센서의 생산성을 향상시킬 수 있는 효과가 있다.In addition, the active layer region except for the polysilicon region is selectively silicided to suppress the bridge between the active layer and the polysilicon which may be caused in a general silicide process, and a series of selective silicide processes reduce the error rate of the dark-bed pixel. There is an effect that can improve the productivity of the sensor.
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| KR940001432A (en) * | 1992-06-12 | 1994-01-11 | 문정환 | CCD image device |
| JPH07283384A (en) * | 1994-04-12 | 1995-10-27 | Nikon Corp | Infrared solid-state image sensing device |
| KR19990079275A (en) * | 1998-04-03 | 1999-11-05 | 김영환 | Solid state imaging device manufacturing method |
| KR20000003406A (en) * | 1998-06-29 | 2000-01-15 | 김영환 | Complementary metal-oxide-silicon image sensor containing self-aligned silicide layer and manufacturing method thereof |
| KR20000017459A (en) * | 1998-08-27 | 2000-03-25 | 카네코 히사시 | Solid-state image sensor and method of fabricating the same |
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| KR940001432A (en) * | 1992-06-12 | 1994-01-11 | 문정환 | CCD image device |
| JPH07283384A (en) * | 1994-04-12 | 1995-10-27 | Nikon Corp | Infrared solid-state image sensing device |
| KR19990079275A (en) * | 1998-04-03 | 1999-11-05 | 김영환 | Solid state imaging device manufacturing method |
| KR20000003406A (en) * | 1998-06-29 | 2000-01-15 | 김영환 | Complementary metal-oxide-silicon image sensor containing self-aligned silicide layer and manufacturing method thereof |
| KR20000017459A (en) * | 1998-08-27 | 2000-03-25 | 카네코 히사시 | Solid-state image sensor and method of fabricating the same |
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