KR100383155B1 - Combined full-speed / commercial service communication system and its service provision method and mobile station - Google Patents

Abstract

Apparatus and method for providing a dual speed full speed / full speed service type including a full speed codec having a front end including a full speed codec and one bit mapping rearrangement module arranged to communicate with the full speed codec are described.

Description

Combined full-speed / communication service communication system and its service providing method and mobile station

Field of invention

The present invention relates generally to communication systems, and more particularly to a method and apparatus for providing a combination full / half rate service type in a communication system.

Background of the Invention

Digital communication systems have components that encode and decode speech for communicating on radio frequencies. In Global System for Mobile Communications (GSM), speech transcoders provide encoding and decoding capability in one component, sometimes referred to as speech codec. GSM speech transcoder is strictly defined as 16 bits by GSM Recommendation 06.10. Similarly, there are channel codecs that encode and decode additional information and data into speech for transmission and reception on the air.

In current GSM digital cellular radio systems, the speech codec delivers 13 Kbits of compressed speech to the channel codec, which in turn delivers 22.8 Kbits in the radio frequency (RF) path. This is called the full rate service type. A half speed speech service is planned, where a half rate speech codec will deliver about 6 Kbits to the half speed channel codec, which in turn carries 11.4 Kbits to the RF path.

In addition to the compressed speech data, the speech / channel codec interface also uses extra 3 Kbits to convey control information. This control information includes a Bad Frame (BFI) flag that tells the speech decoder whether there is an error in the current compressed speech frame received from the channel decoder. The flag is used by the DTX (Discontinuous Transmission) scheme in the speech decoder to improve the subjective quality of the received speech. These 3Kbits also carry the service type for the call. Service types include full speed and full speed speech. The service type is passed to the channel codec. The channel codec then sends this service information to the speech codec.

The speech codec carries a frame of compressed speech bits grouped with respect to speech parameters representing the original speech. The bits arranged with this parameter are rearranged in sensitivity ordering by the channel codec. If there is a single bit error in one of the highest sensitivity bits, the original speech cannot be reproduced intelligibly. On the other hand, even bit errors within the lowest sensitivity bits cause only a slight subjective degradation of the decoded speech.

The channel codec is typically at the base transceiver site (BTS), while the speech codec may be at the BTS, base station controller (BSC) or mobile switching center (MSC) sites. If the speech codec is not at the BTS site, GSM specifies the interface or protocol that should be used between the remote speech codec and the channel codec. This interface exists for full speed (GSM 08.60) and is planned for full speed (GSM 08.60 or new literature).

The algorithms used for the full-speed speech codec and the algorithms currently proposed for the full-speed speech codec are completely different. Therefore, the parameters generated by the algorithms and the parameters for parameter sensitivity ordering are also different.

In both full speed and full speed services, the channel codec has three classes of bits: 1a, 1b and 2, where 1a is the highest sensitivity bit and 2 is the lowest sensitivity bit. Different types and amounts of channel coding then apply to each of these three classes.

Full speed includes 50 class 1a bits, 3 cyclic redundancy check (CRC) bits, 132 class 1b bits, 78 class 2 bits and 4 tail bits, which are 456 bits after coding. Form. At half speed are 22 class 1a bits, 3 CRC bits, 73 class 1b bits, 17 class 2 bits, 6 tail bits, and form 228 bits after coding.

At both full speed and half speed, 1a bits have a CRC associated with them, 1a, 1b and CRC are coded in convolution, and no extra protection is added to the bits of class 2.

At full speed, the main use of the CRC is to flag the BFI. At half speed, the BFI is set not only by CRC but also by the Window Error Detection (WED) scheme specified as part of Motorola's half speed algorithm.

Full-speed remote speech codec to full-channel codec interface uses a 16Kbits GSM interface (GSM 08.60). The equivalent half-speed interface can be lowered to 8Kbits and has the advantage of reducing the lease cost of the serial link between the remote speech codec and the base site (channel codec) by half. Plans are underway to formulate both 8Kbits and 16Kbits modes for the full-speed remote speech codec-to-channel codec interface.

1 illustrates uplink communications in the prior art in which full-speed speech services are implemented using full-speak speech coder 14 and full-channel coder 20. Speech is communicated to input 10 of voice interface 12 of mobile station 11. The speech is coded in the full speech codec 14 of the mobile station. The coded speech is passed to the channel codec processor 16. The channel codec processor 16 includes a full-length channel codec 20 as well as a standard predefined parameter to sensitivity bit rearrangement module 18. The output from full speed codec 14 is passed to standard parameter to sensitivity bit rearrangement module 18. The output of the standard parameter to sensitivity bit rearrangement module 18 is passed to the full channel codec 20 for subsequent processing and then to the radio frequency (RF) interface 22 for transmitting indication signals 24 on the atmosphere. Is delivered).

Indication signals 24 are received at base transceiver station 13 and communicate RF interface 22 to channel codec processor 17 similar to channel codec processor 16 of mobile station 11. Is processed through.

The signals are passed to the full channel codec 21 for initial decoding and then processed by the sensitivity versus parameter bit rearrangement module 19. The output of the sensitivity versus parameter bit rearrangement module 19 is then passed to full speed codec 15 for next decoding and outputs 64 Kbit / s speech 26. For clarity, the dedicated speech codec 15 is located at the BTS site. Similarly, half speed service can be implemented using half speed speech and channel codec.

Advantages of lower cost can be obtained from a full speed service and it is desirable to be able to provide a combined full speed / full speed service in which the robustness and quality of the full speed service are obtained.

Summary of the Invention

Combined full speed with full speed codec having a front end comprising a full speed speech codec and a bit mapping re-ordering module arranged for communicating with the full speed speech codec according to the invention. A communication system with a coherent service type is provided.

In accordance with the present invention there is described a method for providing a dual full speed / propagation service in a communication system having a speech codec and a channel codec comprising providing a bit mapping rearrangement as a front end for the channel codec for communicating with a speech codec. .

Detailed description of the preferred embodiment

Referring to FIG. 2, a communication system includes a full-speed channel codec having a front end including a full speed speech codec 30 and a bit mapping rearrangement module 33 arranged to communicate with the full speed speech codec 30. It is possible to provide a combined full speed / speed independent service type including 32).

In particular, the implementation of this combined service type can be described with reference to FIG. 3 shows a block diagram of uplink communication using the full speed / full speed service of the present invention.

Speech is communicated to input 10 of voice interface 12 of mobile station 11. The voice interface transmits speech to the first half speed speech codec 30 to provide coded signals.

The coded signals are passed to a parameter to sensitivity bit rearrangement module 33 of the first hybrid channel processor 16 that rearranges the bits of the coded signals as described below. The rearranged bits are passed to full channel codec 20 for further processing. The output of the full channel codec 20 is transmitted over the RF interfaces 22 to a second mixed channel processor 31 located in the base transceiver station 13 on the air.

The full channel codec 21 of the second mixed channel processor 31 decodes the transmitted signals 34 and rearranges the bits of the decoded signals so that the transmitted signals of the second mixed channel processor 31 Pass to sensitivity versus parameter bit rearrangement module 35. The rearranged bits are then sent to the second half speed speech codec 37 via serial link 39 for further decoding and output 64 Kbit / s speech at its output 26. Serial link 39 is required if the second half speed speech codec 37 is located far from the mixed channel processor 31. In other words, the second half speed speech codec 37 need not be located far from the mixed channel processor 31.

4 is a flowchart of the operation of the speech codecs 30 and 37 according to the present invention. Since the speech codecs should be able to operate in full speed, full speed service or full speed / half speed service according to the present invention, You need to direct the action. For example, in FIG. 4, the speech codec determines what mode of operation is required as in step 40, and if the mode is full speed, a normal full speed speech coding or decoding operation is implemented as in step 44. If half speed or full speed / half speed is required, then a normal half speed speech coding or decoding operation is implemented as in step 42.

However, the bit rearrangement module 33 is supplied for the channel coder operation of the hybrid channel processor and operates as described in FIG. 5 in accordance with the preferred embodiment of the present invention. The mixed channel processor or codec 32 determines what channel service type is required as in step 48. If full speed, normal full channel coding is implemented as in step 53. Similarly, at half speed a normal half speed channel coding operation is implemented as in step 51.

However, if full / full-speed channel service is indicated, the bit rearrangement module 33 of the mixed channel processor 32 maps the full-speed speech parameters into the sensitivity array as defined in the standard half-speed algorithm as in step 50. The bit rearrangement module 33 then takes all 22 class 1a bits and determines a 3-bit CRC as defined at half speed using the standard half speed method as in step 52, resulting in a 22 channel codec class 1a. And three CRC bits. At the same time, in step 56, the bit rearrangement module 33 then takes all 73 class 1b bits and 17 class 2 bits, adds 70 zeros, as defined at half speed, The result is 160 channel codec class 1b bits.

The resulting 22 channel codec class 1a and 3 CRC bits and 160 channel codec class 1b bits are all processed in step 54 respectively, and 22 class 1a, 3 CRC, 160 class 1b and 4 bits Tail bits are processed through the full speed convolution encoder, resulting in bits coded with 378 convolutions. As in step 58, the convolutionally coded bits are added to the channel codec class 2 bits (78 zeros) to make up 456 bits. The 456 coded bits are sent to the rest of the full channel coder, including interleaving as in step 60.

The channel decoder operation of the hybrid channel processor requires reverse operation of the bit rearrangement module 35 according to the preferred embodiment of the present invention as described in FIG. The mixed channel processor or codec 31 determines what channel service type is required as in step 60. If it is full speed normal full channel decoding is implemented as in step 61. Similarly, if it is half speed, a normal half speed channel decoding operation is implemented as in step 63.

However, if full speed / half speed is indicated, the normal full speed deinterleaving output is processed as in step 62, resulting in 456 coded bits. The 456 coded bits are processed to remove redundant channel codec class 2 bits (78 zeros) as in step 64, resulting in 378 convolutional coded bits. The 378 convolutionally coded bits are processed by regular (standard) full-channel decoding, optionally including WED, as in step 66 and divided into channel codec class 1a and 1b bits.

The resulting 22 class 1a bits and 3 CRC bits optionally contain WED as in step 68 and are processed by standard half-speed CRC checking, resulting in BFI. As expected, the 22 speech coded class 1a bits are mapped to parameters as required in the standard half speed speech decoder as in step 70.

The resulting other 160 channel codec class 1b bits are also mapped to parameters as required in the standard half speed speech decoder as in step 70.

A new service type may be indicated by adding a size to a flag sent to the channel codec indicating whether a service type of full speed, half speed, or full speed / half speed is being used.

The drawings can be easily inferred even for downlink communication.

In summary, the bit rearrangement module can use a table to map bits. First, the table used to map the bits and passed from the speech coder and subjective sensitivity arrangement in the parameter array is a half speed table instead of a full speed table. Second, after mapping these bits, they are again mapped to three classes for the full-channel codec. The number of channel codec class 1a bits is 22, the number of channel codec class 1b bits is 160, and the number of channel codec class 2 bits is 78. This replaces all 22 speech codec class 1a bits with 22 channel codec class 1a bits, and 73 speech codec class 1b and 17 speech codec class 2 bits as 90 bits of 160 channel codec class 1b bits. Mapping and setting the remaining 160-90 = 70 channel codec class 1b bits to some known value, such as 0, and all 78 channel codec class 2 bits to some known value, such as 0.

Therefore, all speech bits are mapped to both class 1a or class 1b and therefore will be protected by the channel coder.

The reason for reducing the number of class 1a bits is as follows. The CRC should only operate on those bits whose meaning is very important, which can mean that at any one the error cannot be understood to reproduce the original speech. If there are more bits in this class 1a without extra bits, the frame is unnecessarily discarded because the CRC objective criteria are met. Therefore, there is a need or restriction that the bits must be included in class 1a when really needed. As a result, more (or more usability) Class 1b bits are needed to have enough bits to pass through to the regular full-speed convolutional coder. In the normal full speed approach, the number of bits passed to the convolutional coder is 189 (50 for 1a, 3 for CRC, 132 for 1b, 4 for tail). According to the present invention, the number of class 1a is 22, the CRC is 3, the tail is 4, and the remaining class 1b is 160 (189-22-3-4).

The third change to the channel codec is to include the WED in the channel decoding as indicated for the half speed channel codec described with reference to FIG.

The combined full speed / full speed system and method of the present invention can provide a more robust full speed service and can take advantage of 8Kbits sub-rate multiplexing between the remote speech codec and the channel codec. The present invention provides a service similar to full speed, but has the advantage of low cost of 8K sub-rate multiplexing between the remote speech codec and the channel codec.

Advantages of the present invention over exclusive services are as follows. Since the speech coder to channel coder is half-speed (i.e., 8Kbits instead of 16Kbits), the present invention provides a full-speed service at half-speed lease cost of serial links between the remote speech codec and the base site. Full-speed channel coders can use full-speed WED to improve channel decoding, resulting in more robust and better perceived speech quality.

Advantages of the present invention over the regular service are as follows. The present invention provides more robust and better perceived speech quality since all half-speed speech bits are protected and more than half the channel bits are known, even though the interleaving is the same.

The present invention introduces the full speed / full speed speech service type in addition to the existing full speed and full speed speech service types. In the full / full speed service type, the Motorola full speed speech codec is used over the full speed speech codec during this call. Therefore, the full speed speech codec is mixed with the modified full channel codec. The channel codec used during this call would be a full channel codec with a different front end. Thus, a more robust half-rate service is presented, resulting in a cost savings for speech codec to channel codec link.

1 is a block diagram of prior art uplink full rate service communication.

2 is a block diagram of a full speed / combination service according to the present invention.

3 is a block diagram of uplink communications including the full speed / full speed service of FIG.

4 is a flow chart for a speech codec in accordance with the present invention.

5 is a flowchart of a channel coder according to the present invention.

6 is a flowchart of a channel decoder according to the present invention.

Explanation of symbols on the main parts of the drawings

12: voice interface 13: base transceiver station

20, 21: full channel codec 22: RF interface

30, 37: half speed speech codec 31, 32: mixed channel processor

33: parameter vs sensitivity bit rearrangement module

35 Sensitivity vs. parameter bit rearrangement module

39: serial link

Claims (5)

In a communication system for providing a combined full-speed / full-speed service type, the communication system, A half speed speech codec; A full-speed channel codec having a front end arranged to communicate with the half-speed speech codec, The front end is, A bit mapping rearrangement module for mapping the half speed speech parameters into the half speed sensitivity array; A CRC processor for processing a first portion of the mapped speech parameters using a half speed method and for determining a cyclic redundancy check (CRC), And a convolutional encoder for full-speed encoding at least the first and second portions of the mapped speech parameters to form the encoded set of bits. 2. The communications system of claim 1 wherein the full channel codec is located at a known transceiver station and the full speed speech codec is located far away. A mobile station arranged to communicate in a communication system, the mobile station comprising: A half speed speech codec; A full-speed channel codec having a front end arranged to communicate with the half-speed speech codec, The front end is, A bit mapping rearrangement module for mapping the half speed speech parameters into the half speed sensitivity array; A CRC processor for processing a first portion of mapped speech parameters using a half speed method and for determining a cyclic redundancy check (CRC); And a convolutional encoder that encodes at least the first and second portions of the mapped speech parameters to form the encoded set of bits. In a communication system having a full speed speech codec and a full speed channel codec, a method for providing a combined full speed / full speed service, the method comprising: Generating half speed speech parameters; Providing a bit mapping rearrangement as a front end for the full channel codec for communicating with the full speed speech codec, wherein the bit mapping rearrangement comprises mapping the full speed speech parameters to a full speed sensitivity array. Providing step; A CRC processing step of determining a CRC by processing a first portion of the mapped speech parameters using a cyclic redundancy code (CRC); A full convolutional encoding step of performing full convolutional encoding of at least the first and second portions of the mapped speech parameters to form an encoded set of bits; Passing at least the encoded set of bits to the full channel codec. A method for providing a combined full speed / full speed service in a communication system having a first and second half speed speech codec and a first and second mixed full channel codec processor, the method comprising: Transmitting speech to the first half speed speech codec to provide coded signals; Transmitting the coded signals of the half speed speech codec to a first hybrid full channel codec processor; Rearranging the bits of the coded signals in the first hybrid full channel codec processor; Transmitting the rearranged bits to an exclusive channel codec to provide other coded signals; Transmitting the other coded signals to a full channel codec of a second hybrid full channel codec processor to provide decoded signals; Rearranging the bits of the decoded signals in the second hybrid full channel codec processor; Transmitting to the second half-speed speech codec for further decoding the rearranged bits.