KR100378324B1 - Segmented column memory device voltage steering technique - Google Patents

Abstract

A method and associated circuitry is disclosed for applying the high column segment voltage needed to erase and program (write) a segmented column flash EEPROM memory. Low-voltage CMOS transistors are used for both read column precharge paths and write / erase data transfer paths. In addition, the column segment select switch may be composed of a single low voltage n-channel transistor rather than two complementary high voltage transistors. All of these reduce the precharge and discharge times, increasing the read speed of the memory. This also prevents the precharge time that occurs as the characteristics of high voltage transistors degrade as performance degrades. The present invention provides the additional advantage of eliminating the need to use a less reliable high voltage transistor in certain off-pitch circuits required for write and erase functions, thereby improving overall chip reliability.

Description

Integrated circuit with electrically programmable memory and method of performing high voltage memory operation {SEGMENTED COLUMN MEMORY DEVICE VOLTAGE STEERING TECHNIQUE}

The present invention is part of a series of applications of US Patent Application No. 09 / 247,302, which is incorporated herein by reference.

FIELD OF THE INVENTION The present invention relates to electrically programmable memories, and more particularly to flash EEPROM memories.

As used herein, the term "high voltage" usually refers to a voltage more than 5 volts, and the term "low voltage" refers to 5 volts or less (5 volts or less). less voltage, usually 3.3 volts or less. The term "high voltage transistor" refers to a transistor (e.g. a thick oxide transistor) designed to operate at high voltages with minimal degradation, and the term "voltage transistor" is designed to operate only at low voltages. This refers to a transistor (for example, a low voltage CMOS transistor).

The use of Electrically Erasable Programmable Read Only Memory (EEPROM) is increasing in cellular phones, answering machines, wireless phones, and other devices including silicon integrated circuits. . In current-generating flash EEPROMs, because the columns must rise to high voltages during erase and programming operations (collectively referred to herein as " high voltage memory operations "), to erase and program (write) flash memory cells. The use of thick oxide transistors and circuits capable of handling high voltages (eg, approximately 7 volts) in critical read column precharge paths is required. However, the use of high voltages in the EEPROM adversely affects performance. For example, in high voltage transistors operating at high voltages, parameters are susceptible to degradation and inherently less reliable than low voltage core CMOS transistors operating at lower voltages (e.g., less than 5 volts, typically about 3 volts). . Because the gain of the high voltage transistor is very low (typically less than half the gain of the low voltage core CMOS transistor), the read precharge and cycle time are also increased when the high voltage transistor is used in the required read thermal precharge path.

1 illustrates a representative EEPROM circuit 10 of the prior art. 1 illustrates a flash EEPROM memory array 20 having N columns (C ₁ , C ₂ , ... C _N ) and M rows (R ₁ , R ₂ , ... R ₃ ), and associated on pitch sensing Associated on-pitch sense amplifier block 30, column select transistor block 40, high voltage precharge transistor block 50, and write / erase data transfer gate block. 60 is shown.

Each memory cell in the memory array 20 includes a floating gate transistor, where the drain terminal is connected to an associated column, the gate terminal is connected to an associated row, and the source terminal is connected to a source. do. In essence, a floating gate transistor is arranged on top of a current channel of a transistor and separated from the current channel by an insulating layer (oxide), i.e., a floating gate, and is arranged above the first gate and by another insulating layer. A second gate, that is, a fixed gate, is separated from the first gate. The fixed gate is directly connected to the gate terminal of the transistor. Both stacked gate and separated gate designs are known in the art.

The column precharge transistor block 50 includes high voltage transistors 51 (1), 51 (2), ... 51 (N)} each connected to each column and made of thick oxide.

As is known in the art, in order to read a flash memory cell, the column associated with that cell must be precharged to a specific voltage, for example one volt. Once the cell has been written, i.e., if the cell stores logic 1, the transistor containing the cell will remain off when the corresponding row is asserted, and the voltage placed in the column through the precharge transistor. Will not discharge. On the other hand, if the memory cell is erased, i.e., the memory cell stores digital zero, the memory cell will be turned on when the corresponding row is asserted, thus leading the column to ground through the source-drain path of the memory cell transistor. .

The sense amplifiers 30 (1), 30 (2), ... 30 (m) amplify the thermal voltage set by the cell to the column, and the column is read to generate an output. As is known in the art, when erasing a flash EEPROM memory array, the column (drain terminal of the memory cell) rises to a high voltage, usually 7 volts, while the row (gate terminal) R ₁ , R ₂ , ... R _M is maintained at ground (0 volts) or reduced to a negative potential below ground. The source is typically open circuited for erasing. The high gate-drain voltage difference causes electron tunneling from the drain of the transistor to the floating gate, raising the nominal potential of the floating gate. When the corresponding row is asserted (i.e. when the fixed gate rises to a logic high level, such as 3.3 volts), the nominal potential of the floating gate to the point at which the nominal potential rises above the threshold current of the transistor. Sufficient electron tunneling may occur to elevate. This causes the transistor to conduct when the corresponding row is asserted (to read that cell), driving the corresponding column to ground.

When writing the flash EEPROM memory array 20, the column (gate) associated with the cell to be written (i.e., the cell to store digital 1) is at high potential, usually 7 volts, as in the case of the column (drain) associated with the cell to be written. Is raised. The source terminal is grounded. Other columns associated with the cell along the same row that will not be written to remain at ground. This condition causes hot electron injection from the current channel to the floating gate, lowering the nominal potential of the floating gate. Even when the gate terminal rises to 3 volts, i.e. when the corresponding row is asserted, sufficient electron injection occurs to lower the nominal potential of the floating gate to the point where the floating gate is still below the threshold voltage so that the transistor is not conducting. Can be. Thus, no heat is discharged and the cell will be read into logic one.

Thus, it can be seen that when erasing or writing a cell, it is necessary to raise the relevant column to a high voltage level. Therefore, the column precharge transistor having a drain terminal connected to the column must be a thick oxide transistor of a high voltage in order to handle the high voltage. During the erase and write operations, the gates of the precharge transistors 51 (1), 51 (2), ... 52 (N) are at ground (0 volts) along the PRECHARGE input 52. As a result, the gate-drain potential for each transistor is high (e.g., 7 volts), and the high voltage transistor will easily withstand this high potential, but the low voltage core CMOS transistor will be destroyed.

Refer to the first column C ₁ of FIG. 1, it will be described a method and circuit of the related art. For erase and write operations, the precharge input 52 is prevented from conducting through the precharge transistor 51 (1) in the precharge block 50 before applying a high voltage to the inputs D ₁ and RC ₁ . It must be set to ground. Also, in preparation for applying a high voltage to the first column C ₁ for write / erase, a high voltage, typically 7 volts, is applied to the data input D ₁ and read control input RC ₁ of the write / erase data transfer gate block 60. do. When entered as above, data is set up but conduction through devices M7 and M8 is interrupted.

When the entire memory is cleared, all data input terminals D ₁ , ..., D _n receive high voltage. However, for programming, only the column containing the cell to be programmed is charged. Then, writing or erasing is started by lowering the read control input RC ₁ and thus allowing a high voltage applied to the data input D ₁ to be transferred to the column C ₁ . Specifically, lowering the read control input RC ₁ turns on the devices M7 and M8 to transfer a high voltage to the heat at the data input D ₁ .

If the operation is a write, for a column associated with a cell that is not to be written, its voltage is taken to ground along the same row as the other cells to be written by holding the data input (ie, D ₁ , D ₂ , ... D _N ) to ground. maintain.

The column select transistor block 40 and sense amplifier block 30 are used to read the flash memory. In particular, a column enable signal connected to the gates of the transistors 41 (1), 41 (2), ..., 41 (N)} is manifested, thus turning on the transistors to The voltage can be sensed by the sense amplifier block 30. The sense amplifiers 30 (1), 30 (2), ... 30 (N)} provide a logic high level for the circuit (e.g. 3.3 volts) for the circuit when the column is 1 volt. Amplify). When heat is grounded through the memory cell transistors, the output of the sense amplifier is at ground.

Care must be taken to ensure that the transistors 41 (1), 41 (2), ... 41 (N) are not subjected to over-voltage stress during writing or erasing. If the column select transistors {41 (1), 41 (2),... 41 (N)} in the column select block 40 are low voltage transistors, their gates {COLEN input 42} have a column voltage greater than or equal to VDD. It must be set to the VDD level (eg 3.3 volts) before rising to. Otherwise, the gate-drain voltage will go to a high voltage and there is a possibility of damaging the gate oxide of the transistor. With the gate at VDD and the column elevated high, the inputs of the sense amplifiers N ₁ , N ₂ ..., N _n will be at VDD-Vt. The voltage VDD-Vt will not over-stress any transistor in the sense amplifier. Alternatively, the column select transistors 41 (1), 41 (2), ... 41 (N) in the column select transistor block 40 may be high voltage transistors. In this case, the COLEN input 42 can be set to ground, which blocks conduction through the device.

The precharge transistors 51 (1), 51 (2), ... 51 (N)} are high voltage transistors made of thick oxide for processing high level write and erase voltages. High voltage transistors have a low gain due to the thick oxide. The use of the low gain transistors in the precharge block 50 increases precharge and cycle time, thereby limiting circuit performance. The characteristics of high voltage transistors also degrade with time when operating at high voltages. This degradation results in longer precharge time over time.

Write / erase data inputs D ₁ , D ₂ , ... D ₃ and read control signal input RC ₁ of write / erase data transfer gate block 60 must be at a high voltage level when asserted to perform write and erase functions. Therefore, the recording and / or transistor in the erase data transfer gate block 60 (e. g., transistors M7 and M8) are not only the high-voltage transistor with a thick oxide, off required to generate the high voltage signal on lines D ₁ pitch circuit ( off-pitch circuitry (not shown) should also include high voltage transistors. Since high voltage transistors are generally less reliable than low voltage transistors, using such a large number of high voltage transistors makes EEPROM operation less reliable.

In addition, there are quite a few capacitances associated with each heat. In particular, each memory cell has an associated capacitance. The larger the magnitude of the capacitance in the column, the slower the rate at which the column for the read operation is precharged and discharged.

In order to reduce the effective capacitance, it is known in the art to separate each row into segments that are individually precharged and discharged. 2 is a circuit diagram of a prior art flash EEPROM with segmented columns. 3 is a more detailed circuit diagram of the individual column segments of the circuit shown in FIG. Sense amplifier block 130, column select block 140, column precharge transistor block 150, and write erase block 160 are essentially identical to blocks 30, 40, 50, 60 in the circuit of FIG. Do.

For example, if a global column, for example 120 (1), contains 256 cells, then the entire column 120 (1) is divided into four column segments, COLSEG_1_1, COLSEG_2_1, ... COLSEG_4_1, The segment contains 64 cells. In this way, the effective capacitance during the read operation period can be divided by a factor of four. As shown in FIG. 3, each column segment includes memory cells 102 (1), 102 (2), ... 102 (N). As before, the control gates of the cells are individually connected to the rows, the source terminals of the cells are all connected together to the voltage source, and the drains of the cells are all connected to the column segments. The row segments are connected to the entire row via row segment selector switch 104. As can be seen in FIG. 2, each row segment is connected to the entire row through a switch, such as switch 104. Segment select signal line 110 and vice versa are connected to corresponding transistors of column segment select switch 104, respectively.

The switch 104 includes two complementary, high voltage, thick oxide, transistors 106 and 108. The transistor is a high voltage transistor because it needs to transfer a voltage of 7 volts with heat as much as 1/4 mA during the write operation. As two complementary transistors are known in the art, because n-channel transistors are pull-down wells but not pull-up wells, p-channel transistors are pull-up wells but not pull-down wells. , desirable. The column segment select switch 104 has an n-channel device that pulls the sense amplifier input most effectively in the direction of ground upon reading (when the accessed cell stores zero) and, when programming (ie, writing) or erasing, It has a p-channel device for high voltage memory operation (erasure and program) to most effectively pull up to the high voltage level required for the drain terminal of the cell.

The segmented column array architecture is well suited for high speed, low power read operations because only one column segment is precharged and discharged during a read cycle every column. Since the capacitance of one column segment is only part of the capacitance of the entire row, the precharge / discharge time and power are also reduced by the portion of what was needed to precharge / discharge the entire row.

However, the improvement in performance is somewhat reduced because high voltage transistors, such as transistors 106 and 108 of switch 104, have not only low gain but also relatively high parasitic capacitance. Thus, switch 104 adds undesirable parasitic capacitance to the column segment to reduce the read operation speed due to low gain in the sense and thermal precharge paths.

Moreover, the high voltage low gain transistors in the column precharge block 50 and the write / erase data transfer gate block 60 retain their inherent disadvantages in the circuit.

The present invention relates to a novel method and associated circuitry for applying the high thermal voltages required to erase and program (write) memory, in particular segmented thermal flash EEPROM memories. In contrast to the low gain high voltage transistors used in prior art read thermal precharge paths, data paths and column segment select switches, which are made of thick oxide, the present invention uses low voltage transistors.

According to the present invention, the high voltage required for high voltage memory operation in a flash EEPROM memory is provided through a high voltage path that is separate from the data and column segment precharge paths, while selecting transistors and column segments in the data sensing path and the column precharge path. The switch can be reduced in both number and rated voltage / current.

1 is a circuit diagram of a prior art flash EEPROM;

2 is a circuit diagram of a flash EEPROM having segmented columns of the prior art;

3 is a more detailed circuit diagram of an individual column segment of the circuit of FIG. 2;

4 is a circuit diagram for a segmented thermal flash EEPROM in accordance with the present invention;

5 is a circuit diagram of a column segment of a segmented thermal flash EEPROM in accordance with the present invention.

Explanation of symbols for the main parts of the drawings

10: EEPROM circuit

20: Flash EEPROM Memory Array

30: on pitch sense amplifier block

40: column select transistor block

50: high voltage thermal precharge transistor block

60: write / erase data transfer gate block

120: column segment array

130: sense amplifier block 140: column selection block

150: column precharge transistor block 160: write erase block

4 is a circuit diagram of a flash EEPROM according to the present invention in which the individual column segments of the flash EEPROM are comprised of the circuit shown in FIG. As shown in FIG. 4, a preferred embodiment of the flash EEPROM 200 according to the present invention includes a memory array 220 comprising entire columns GCOLUMN_1, GCOLUMN_2,... GCOLUMN_L. Each column contains M column segments. For example, GCOLUMN_1 includes column segments COLSEG_1_1, COLSEG_2_1, ... COLSEG_M_1. Each column segment contains N rows. For example, COLSEG_1_1 includes ROW_1_1, ROW_1_2, ... ROW_1_N. Thus, there are MxN rows and L columns for every column. Thus, there are a total of MxNxL memory cells in the example array. The flash EEPROM 200 further includes an on pitch sense amplifier block 230 and a column select transistor block 240. The on pitch sense amplifier block 230 and the column select transistor block 240 are conventional and do not constitute a novel subject per se. The precharge / write data transfer block 250 is a precharge transistor using low voltage CMOS transistors 250 (1), 250 (2), ... 250 (L) in accordance with the present invention, as described in more detail below. It integrates functionality and record / erase data transfer. Each column segment is connected to the entire column shown by terminal GCOL and also to the high voltage source VPP. In addition, each column segment receives a segment select signal SEGSEL_1, SEGSEL_2, ... SEGSEL_M, which, when asserted, selects the corresponding column segment of all the entire columns. Thus, for example, SEGSEL_1 selects COLSEG_1_1, COLSEG_1_2, ... COLSEG_1_M.

5 illustrates an exemplary thermal segment COLSEG_1_1 in more detail. Preferably, all the heat segments are essentially identical. As shown in FIG. 5, each memory cell includes a separate gate memory cell transistor. However, it should be understood that this is only a preferred embodiment and that the present invention can be applied to a memory including a type of electrically programmable memory cell different from a stacked gate memory cell. As in the prior art, the drain terminals of all cells are connected to the column segments, the gate terminals are connected to the rows, and the source terminals are all connected together to the source node. The segment select signal COLSEG_1_1 is connected to a column segment select transistor.

Each column segment includes an erase / program column segment boost latch 280. The erase / program column segment boost latch 280 is a path that connects the column to the voltage source VPP and provides the column segment with the high voltage (usually 7 volts) needed to erase and / or write (ie, program) the memory cell. The erase / program column segment boost latch 280 is connected in series with an n-channel high voltage transistor 284 of thick oxide and includes a p-channel high voltage transistor of thick oxide. The gates of the two transistors are connected to the column segments. The source of transistor 282 is connected to high voltage source VPP (eg, 7 volts). The drain of the transistor 284 is connected to the read control line 290 of the memory array. The third transistor 286, i.e., another p-channel high voltage transistor made of thick oxide, has a gate connected to the junction between the transistor 282 and the transistor 284. The source terminal is connected to VPP and the drain terminal is connected to the column segment.

The column segment select switch 270 includes a single low voltage n channel transistor 272 having a gate terminal connected to a corresponding SEGSEL signal line.

As discussed in the background of the above invention, in the operation of programming the flash memory, the memory array is first erased so that all values stored in the memory array are cleared. In general, an erased cell represents itself at a logic low level (ground). Thus, writing or (programming) the memory means leaving the cell to store logic 0 in the erased state and leaving only the cell in which the logic 1 value is stored in the " write " state. Those skilled in the art should understand that value logic 0 and logic 1 are arbitrary values and the values are simply two different voltages. In this specification, if not the most practical memory cell, logic 0 is labeled ground or 0 volts, and logic 1 is labeled high voltage, eg 3.3 volts.

As previously described, erasing a cell involves applying a sufficiently high voltage across the gate-drain path, causing electron tunneling from the drain to the floating gate, thereby setting the nominal voltage of the floating gate to a specific value. do. Its value causes the floating gate to be above the threshold voltage Vt of the transistor when a nominal high voltage (e.g. 3.3 volts) is applied to the fixed gate of the transistor (via the corresponding row terminal) to read the transistor. Is selected to turn on and the cell conducts the thermal segment to ground. Writing a cell involves applying a high voltage to both the cell's drain and a fixed gate terminal to cause thermal electron injection into the floating gate in the current path. When the row corresponding to that cell is asserted for reading (i.e. when the fixed gate rises to 3.3 volts), the floating gate remains below the threshold potential so that the cell does not turn on and does not conduct the column segment to ground. Sufficient electron injection can be generated to lower the nominal potential of the floating gate to a value that becomes. Thus, the precharge voltage on the column segment is maintained and the sense amplifier reads the cell as including logic one.

The operation of erasing and writing memory cells of a memory device in accordance with the present invention is described with reference to the exemplary embodiment of the invention illustrated in FIGS. 4 and 5, in particular with respect to column segment CLOSEG_1_1. In order to raise the column segment to VPP (7 volts) during the write or erase operation, the high voltage power supply terminal VPP is initially set equal to the low voltage power supply terminal voltage VDD (e.g., 3.3 volts). Further, ① read control input 290 is set to ground potential, ② data of the same voltage as VDD is applied to data input DATA-1, ③ WRITE-PRECHARGE input 152 is raised to VDD, and ④ SEGSEL_1 selects the column segment. It is asserted to turn on transistor 272 (FIG. 5). This sets the voltage on the column segment to VDD-Vt, where Vt is the n-channel threshold voltage of device 250 (1). Typical value of Vt is 1 volt. Thus, the column will "raise" to a value of 2 volts (ie 3 volts minus 1 volt is 2 volts). Within latch 280, transistors 282, 284 form an inverter that controls the on or off of transistor 286. However, inverter transistors 282, 284 can be conducted and the gain of transistor 284 is much greater than the gain of transistor 282 (usually five times larger). Thus, with 2 volts in the row segment and VPP set to 3 volts, the junction 288 of the inverter is close to ground and the pass transistor 286 is turned on. When transistor 286 is conducting, the transistor conducts when the gate of transistor 286 is lowered by its threshold voltage (VPP-V _th ) at its drain potential VPP below its drain potential, thereby draining its source (column). Since it rises to the potential VPP, heat is drawn to VPP at a medium thermal voltage of 2 volts. This completely turns off transistor 282 and keeps junction 288 at ground potential. At this point, VPP rises from VDD to the high voltage level needed to perform the write or erase operation, i.e., 7 volts. The high voltage is transferred as heat in transistor 286 and write or erase occurs in accordance with the voltage applied to the gate terminal of the cell (ie, according to the corresponding row input).

At the end of the write or erase operation, it is necessary to return the heat to the ground potential. The return is first made by lowering VPP to VDD and thus lowering the column to VDD. Next, read control input 290 is raised to VDD level, and node 288 is raised to as low as n channel thresholds in VPP. This reduces the conduction of transistor 286 but generally does not completely block conduction. In the state where only transistor 286 is weakly conducting, data input DATA_1 is lowered to ground, which discharges heat completely to ground and raises node 288 to VPP (which is now equal to VDD), thereby completely turning transistor 286 off. Turn off. Transistor 250 (1) must overcome any residual conduction of transistor 286. This is not difficult because transistor 286 is biased to a low gain state due to the gate-source voltage on transistor 286 only slightly above its threshold voltage.

As mentioned above, to prevent writing or erasing a given column, it is necessary to keep the column to ground while writing or erasing cells in other columns along the active row. To do this, the same procedure as described above is followed when raising the heat to high voltage, except that the data input corresponding to the heat that is not to be written is not held at ground potential during the write or erase operation. This maintains the column at ground potential, preventing the column from rising to VDD-Vt. In conclusion, junction 288 of latch 280 remains at VPP, thus blocking conduction through transistor 286.

During the write and erase operations described above, the VPP supply terminal is first raised from the lower VDD level to the higher voltage VPP and then lowered back to the level of VDD at the end of writing or erasing. If VPP is supplied from an off-chip supply, this is achieved by changing the off-chip voltage supply to a higher voltage VPP. Alternatively, VPP may be switched on-chip with a high voltage supply that is externally supplied or internally pumped from VDD. Such methods are well known to those skilled in the art.

Although not a preferred embodiment, it is also possible to write and erase while keeping VPP fixed at high voltage at all times. The same procedure follows as described above, except that VPP is fixed at a higher voltage, for example 7 volts. This is not a preferred mode of operation for two reasons. First, after the heat rises to VDD-Vt, the latch inverter (transistors 282, 284) is at node 288 because the p-channel transistor 284 is more conductive due to the larger gate-source voltage. It will be more difficult to lower the output of. To overcome this, the gain difference between transistors 282 and 284 is increased as discussed above, such that transistor 284 has a much higher gain than transistor 282. Secondly, during the write or erase termination period, the column will be lowered from high voltage to ground by transistor 250 (1) instead of from VDD to ground. At this time, DATA_1 is at ground, and the drain-source potential between both ends of transistor 250 (1) becomes a high voltage potential. In order to prevent punchthrough and degraded reliability of transistor 250 (1), its channel length must be increased. Increasing the channel length reduces the gain of transistor 250 (1), which in turn has the undesirable effect of increasing precharge and cycle time. However, designers may find the above embodiments useful for certain applications.

Since the high voltage for high voltage memory operation enters the column through the erase / program column segment boost latch 280, the data path transistor does not need to carry a high voltage across its gate-source terminal or gate-drain terminal. Likewise, the precharge transistor can be a low voltage device. This is possible because when the high voltage is on the column, the gate of the column precharge transistor is at VDD level rather than ground as in the prior art. Thus, oxide stress (drain-gate potential and source-gate potential) is reduced to the difference between the high voltage level and VDD (eg, 7 volts-3 volts = 4 volts). The use of low voltage transistors reduces precharge and cycle time, eliminating the prolongation of over time due to performance degradation of high voltage transistors. In fact, the prior art data path transistors and precharge transistors for each column may be combined into a single n-channel low voltage transistor 250 (1), 250 (2), ... 250 (N), as shown in FIG. Can be.

Moreover, the column segment select switch may be a single low voltage transistor 272 rather than two complementary high voltage transistors because it no longer needs to support a high gate-drain potential or gate-source voltage. As mentioned above, during the operation of the high voltage memory, the column segment select transistor 272 is turned on, so that a low voltage is transferred to the column segment through the column segment select transistor 272 in the entire column. The low voltage activates the erase / program column boost latch 280 to transfer the voltage from the high voltage source to the column segment for high voltage memory operation. The column segment select transistor is a low voltage transistor because the gate of the column segment select transistor 272 is at its nominal V _DD voltage (eg, 3.3 volts) when the high voltage is connected to the column segment via the column segment boost latch 280. Can be. If the difference between the gate and drain terminal voltages does not exceed the rated voltage of the column segment select transistor and the column segment select transistor channel length is long enough to support the high voltage drain-source potential, the column select transistor will not be damaged. .

The low voltage column segment select transistor 272 has higher gain and lower parasitic capacitive load than prior art high voltage column segment select transistors. As a result, the thermal precharge time is reduced. Since the transistor has a higher gain, the read access time is reduced. Moreover, eliminating large high voltage p-channel transistors in the column segment select switch significantly reduces the overall thermal capacitance, resulting in even more reduction in read access and thermal precharge time.

Moreover, read / erase data inputs DATA_1, DATA_2, ... DATA_L and read control signal 290 are at the VDD level when asserted. Thus, the circuit that generates the signal does not require a high voltage transistor, and therefore, higher chip reliability and lower column segment parasitic capacitance can be obtained.

Eliminating both high-voltage, unreliable and unstable devices from the timing-based data sensing and thermal precharge paths increases the reliability of the memory array.

While the principles of the invention have been described herein, those skilled in the art should understand that the description is merely an example and does not limit the scope of the invention. For example, the preferred embodiment shown in FIG. 5 illustrates a single transistor for every column, both for use as a write / erase transistor and a column precharge transistor, while two separate low voltage transistors to separate the function. Is used within the scope of the present invention. It is also possible to use column segment latches and associated paths to apply high voltages to the column segments only for programming or only for erase, while providing different paths for other functions. In other words, while using a column segment boost latch for both erase and programming operations is quite beneficial in most cases, it is certainly possible to use a column segment boost latch for just one of the functions. It is intended that the appended claims cover all modifications that fall within the spirit and scope of the invention.

As described above, according to the present invention, a novel method and associated circuitry are provided for applying the high thermal voltage required to erase and program (write) a memory, in particular a segmented thermal flash EEPROM memory.

Claims (39)

An integrated circuit having a segmented column electronically programmable memory, comprising: A plurality of memory cells connected to the column segments, A column segment select transistor connected between the column segment and the entire column of the memory; A column segment latch connected between a high voltage source and the column segment—high voltage is applied to the column segment via the column segment latch for high voltage memory operation associated with the memory cell Integrated circuit comprising a. The method of claim 1, And said column segment select transistor is a low voltage transistor. The method of claim 2, The program row segment latch is A first high voltage transistor having current flow terminals connected between said high voltage source and said column segment; And a control transistor coupled to control the first high voltage transistor to conduct during a high voltage memory operation. The method of claim 3, wherein And the control transistor comprises an inverter. The method of claim 3, wherein And the control transistor includes second and third high voltage transistors connected as inverters to control the first high voltage transistor. The method of claim 5, The second high voltage transistor includes a first current flow terminal connected to the high voltage source, a control terminal connected to the column segment, and a second current flow terminal connected to a control terminal of the first high voltage transistor, A third high voltage transistor is connected to a first current flow terminal connected to the control terminal of the first high voltage transistor, a control terminal connected to the column segment, and a signal indicating whether the memory is in a high voltage memory operating mode. And a second current flow terminal. The method of claim 6, The first high voltage transistor is a p-channel transistor, the second high voltage transistor is a p-channel transistor, and the third high voltage transistor is an n-channel transistor. The method of claim 2, And the low voltage column segment select transistor comprises a single transistor. The method of claim 8, And the low voltage column segment select transistor comprises an n channel transistor. delete delete delete The method of claim 9, The EEPROM is a flash EEPROM. An integrated circuit having segmented rows of electrically programmable memory, A plurality of memory cells arranged in rows and columns—the columns are segmented into smaller column segments each connected to an entire column—and, A column segment latch connected between a high voltage source and the column segment—a high voltage is applied to the column segment via the column segment latch for high voltage memory operation associated with the memory cell; Low voltage precharge and erase / programming transistors connected to each of the entire columns Integrated circuit comprising a. The method of claim 14, Wherein the low voltage precharge and erase / programming transistors comprise a single transistor used to precharge the column for a read operation and to write data to a memory cell in the column during programming. delete delete delete delete delete The method of claim 14, The column segment latch is First and second latch transistors connected to form an inverter having an output, the gain of the second transistor being greater than the gain of the first transistor; A third latch transistor connected to form a transfer transistor, the third latch transistor having a gate connected to an output of the inverter, a source connected to a power supply, and a drain connected to a column of the memory array. Integrated circuit comprising a. The method of claim 21, The voltage applied to the column segment via the column segment latch is controlled as a function of initial voltage on the column segment. A method of providing a high voltage to a column segment of the memory device for high voltage memory operation of a segmented column of electrically programmable memory device. The memory device includes a plurality of memory cells arranged in rows and columns and a precharge voltage to the column segment. And a data path for writing data to the memory cell, wherein the column is segmented into the column segments. Applying a high voltage to a latch connected to said column segment, said latch being outside of said read precharge path and said data path; Applying a low voltage to the column segment to turn on the latch so that the high voltage is connected to the column segment How to include. The method of claim 23, Wherein the read precharge path and the data path to the column segment are combined, and wherein applying the low voltage comprises applying the low voltage to the column segment through the combined path. The method of claim 24, The memory device further comprises a column segment select transistor connected between the column segment and the coupled path, and wherein applying the low voltage comprises applying the low voltage to the column segment through the combined path and the column segment select transistor. Applying a process. A method of performing high voltage memory operation in a segmented column of electrically programmable memory device—The memory device includes a plurality of memory cells arranged in columns and rows segmented into column segments, and a read that connects a precharge voltage to the column segment. A precharge path, a data path for writing data to the memory cell, and a high voltage path for connecting a high voltage to the column segment for high voltage memory operation outside the read precharge path and the data path and associated with the memory cell. And wherein the high voltage path comprises a latch and a read control line connected to the latch that indicates whether the memory device is in a read mode or a high voltage memory operating mode. 1) supplying a high voltage source to the latch; 2) setting the read control line to indicate a high voltage memory mode of operation; 3) applying a nominal voltage to the column via the read precharge path or the data path, 4) applying an appropriate voltage to the memory cell on the column segment such that the memory value is set to a desired value A high voltage memory operation method comprising a. The method of claim 26, The read precharge path and the data path are the same path, a control terminal connected to a write precharge signal rising to a nominal voltage for precharging and writing, a first current flow terminal connected to the data path, and A transistor having a second current flow terminal connected to the column segment; Step 3) 3.1) applying a nominal voltage to said control terminal of said transistor, 3.2) applying a nominal voltage to the first current flow terminal of the transistor. The method of claim 27, Step 1) 1.1) applying a nominal voltage to the latch; 1.2) increasing the nominal voltage to a high voltage between steps 3) and 4). The method of claim 28, Step 2) includes setting the read control line to a nominal voltage. delete delete delete delete The method of claim 28, 5) A method of performing a high voltage memory operation that returns a voltage on the column segment to ground. The method of claim 34, wherein Step 5) 5.1) applying a voltage to said read control line to indicate a read mode; 5.2) applying a ground voltage to the column via the read precharge path or the data path A high voltage memory operation method comprising a. delete delete delete delete