KR100373788B1 - Method for providing a etch stop layer in a multilayer interconnection structure - Google Patents
Method for providing a etch stop layer in a multilayer interconnection structure Download PDFInfo
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- KR100373788B1 KR100373788B1 KR10-2000-0020324A KR20000020324A KR100373788B1 KR 100373788 B1 KR100373788 B1 KR 100373788B1 KR 20000020324 A KR20000020324 A KR 20000020324A KR 100373788 B1 KR100373788 B1 KR 100373788B1
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 238000000231 atomic layer deposition Methods 0.000 claims abstract description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims description 11
- 229910003902 SiCl 4 Inorganic materials 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 39
- 239000011229 interlayer Substances 0.000 abstract description 8
- 239000012535 impurity Substances 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 18
- 239000010949 copper Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910020177 SiOF Inorganic materials 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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Abstract
본 발명은 반도체 다층 배선 구조의 식각 저지층 형성 방법에 관한 것이다.The present invention relates to a method for forming an etch stop layer of a semiconductor multilayer wiring structure.
본 발명은 반도체 기판상에 제 1 절연막을 형성하는 단계와; ALD(Atomic Layer Deposition) 기법을 기설정 회수 반복 수행하여 제 1 절연막상에 기설정 두께의 식각 저지층을 형성하는 단계와; 식각 저지층상에 제 2 절연막을 형성하는 단계와; 포토레지스트 패턴을 형성하고 비아 홀(via hole)을 식각하는 단계와; 포토레지스트로 트렌치 패턴(trench pattern)을 형성하는 단계와; 트렌치 패턴으로 식각 저지층을 사용하여 트렌치 구조를 형성하는 단계로 이루어진다. 따라서, 본 발명은 원자 단위의 두께 조절이 가능하고 불순물을 줄이므로써 우수한 막질을 형성할 수 있으며, 저온 공정이 가능하므로 열 공정에 대한 문제점을 해결할 수 있다. 클러스터 시스템(cluster system)의 경우, ALD 시스템에 인-라인으로 층간 절연막을 형성하므로써 대기에 노출되어 생기는 문제점을 최소화 할 수 있다. 또한, 저 유전율의 식각 저지층을 형성하게 되므로 전체적인 유전율 상승을 방지할 수 있는 효과가 있다.The present invention includes forming a first insulating film on a semiconductor substrate; Performing an ALD (Atomic Layer Deposition) method repeatedly to form an etch stop layer having a predetermined thickness on the first insulating film; Forming a second insulating film on the etch stop layer; Forming a photoresist pattern and etching via holes; Forming a trench pattern with the photoresist; Forming a trench structure by using an etch stop layer in the trench pattern. Therefore, the present invention can control the thickness of the atomic unit and can form an excellent film quality by reducing impurities, and can solve the problem of the thermal process because the low temperature process is possible. In the case of a cluster system, a problem caused by exposure to the atmosphere can be minimized by forming an interlayer insulating film in-line in the ALD system. In addition, since the etch stop layer of the low dielectric constant is formed, there is an effect of preventing the overall dielectric constant increase.
Description
본 발명은 반도체 다층 배선 구조의 제조 방법에 관한 것으로, 특히, 반도체다층 배선 구조의 식각 저지층 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor multilayer wiring structure, and more particularly, to a method for forming an etch stop layer of a semiconductor multilayer wiring structure.
최근, 전자 통신 분야에서 급격한 발전을 거듭함에 따라 반도체 소자의 미세화 및 고집적화 현상이 극명하게 드러나고 있으며, 이러한 반도체 소자의 미세화에 따른 여러 가지 문제점들도 함께 수반되고 있는 추세다.Recently, with the rapid development in the field of electronic communication, the miniaturization and high integration of semiconductor devices are clearly revealed, and various problems caused by the miniaturization of such semiconductor devices are also accompanied.
이러한 문제점들 중 신호 지연 문제는 반도체 소자 특성을 좌우할 수 있는 문제로서, 특히, 다층 배선 구조에서는 배선과 배선간의 거리 감소로 인해 같은 층 배선끼리의 정전 용량이 증가하여 신호 지연 문제가 더욱 심화되는 경향이 있다. 즉, 선폭이 작아질수록 배선에 의한 신호 지연이 소자의 동작 특성을 크게 좌우하게 되며, 따라서, 층내 배선 사이의 정전 용량을 줄이기 위해서 배선의 두께를 줄이고 층간 절연막의 두께를 늘여야만 하는 필요성이 대두되었다.Among these problems, the signal delay problem is a problem that can influence the characteristics of semiconductor devices. In particular, in a multilayer wiring structure, the capacitance of the same layer wiring increases due to the reduction in the distance between the wiring and the wiring, and thus the signal delay problem is intensified. There is this. In other words, the smaller the line width, the greater the signal delay caused by the wiring, and thus the greater the operating characteristics of the device. Therefore, the need to reduce the thickness of the wiring and increase the thickness of the interlayer insulating film in order to reduce the capacitance between the interlayer wirings has arisen. It became.
이와 같은 문제를 해결하기 위해서는 낮은 비저항을 갖는 배선 재료와 낮은 비유전율을 갖는 층간 절연막이 필요하다. 배선 재료로는 구리(Cu)가 사용되고 있고 층간 절연막은 다양한 물질이 제안되고 있다.In order to solve such a problem, a wiring material having a low specific resistance and an interlayer insulating film having a low dielectric constant are required. Copper (Cu) is used as the wiring material, and various materials have been proposed for the interlayer insulating film.
그러나, 구리는 식각 부산물의 낮은 증기압으로 인해 건식 식각의 어려움이 있으므로, 다층 배선 구조를 형성하기 위해서 홀을 형성하고 채우는 다마신(damascene) 공정을 사용하여 구리를 패터닝한다. 이러한 다마신 공정을 수행하기 위해서는 식각 저지층을 만들어야 하지만, 식각 저지층의 유전율이 커질 경우, 층간 절연막의 유전율을 감쇄시키는 결과를 초래하기 때문에, 얇은 막의 저 유전율을 갖는 물질, 예컨대, 실리콘 질화물을 사용해야 한다.However, copper suffers from dry etching due to the low vapor pressure of etch byproducts, so copper is patterned using a damascene process to form and fill holes to form a multi-layered interconnect structure. In order to perform the damascene process, an etch stop layer must be formed. However, when the dielectric constant of the etch stop layer is increased, the dielectric constant of the interlayer insulating film is attenuated. Should be used.
이와 같이, 층간 절연막의 유전율을 높이기 위해 얇은 막의 저 유전율을 갖는 물질을 사용해야 할 필요가 있는 바, 종래의 증착 방법에서는 불순물이 유입될 가능성이 많다는 문제가 있었다.As described above, in order to increase the dielectric constant of the interlayer insulating film, it is necessary to use a material having a low dielectric constant of a thin film, and there is a problem that impurities are likely to flow in the conventional deposition method.
또한, 기존의 증착 방법은 CVD(Chemical Vapor Deposition) 기법을 사용하고 있는데, 이 CVD 기법에서는 플라즈마를 이용할 뿐만 아니라 고온 공정이 수반되므로 후속 공정에서의 열적 예산(thermal budget)과 원자 단위의 두께 조절이 어렵다는 문제가 제기되었다.In addition, the conventional deposition method uses CVD (Chemical Vapor Deposition) technique, which not only uses a plasma but also involves a high temperature process, so that thermal budget and atomic thickness control in a subsequent process are controlled. The problem was raised.
따라서, 본 발명은 상술한 문제를 해결하기 위해 안출한 것으로, 가스를 순차적으로 용기 내부에 유입하는 ALD(Atomic Layer Deposition) 기법을 사용하므로써, 원하는 두께의 식각 저지층 및 저 유전율의 물질 형성이 가능하도록 한 반도체 다층 배선 구조의 식각 저지층 형성 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention has been made to solve the above-described problem, by using the ALD (Atomic Layer Deposition) technique to sequentially introduce the gas into the container, it is possible to form an etch stop layer and a low dielectric constant material of the desired thickness It is an object of the present invention to provide a method for forming an etch stop layer of a semiconductor multilayer wiring structure.
이러한 목적을 달성하기 위하여 본 발명은, 반도체 기판상에 제 1 절연막을 형성하는 단계와; ALD 기법을 기설정 회수 반복 수행하여 제 1 절연막 상에 기설정 두께의 식각 저지층을 형성하는 단계와; 식각 저지층상에 제 2 절연막을 형성하는 단계와; 포토레지스트 패턴을 형성하고 비아 홀(via hole)을 식각하는 단계와; 포토레지스트로 트렌치 패턴(trench pattern)을 형성하는 단계와; 트렌치 패턴으로 식각 저지층을 사용하여 트렌치 구조를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 다층 배선 구조를 제공한다.In order to achieve this object, the present invention comprises the steps of forming a first insulating film on a semiconductor substrate; Repeating the ALD technique a predetermined number of times to form an etch stop layer having a predetermined thickness on the first insulating film; Forming a second insulating film on the etch stop layer; Forming a photoresist pattern and etching via holes; Forming a trench pattern with the photoresist; It provides a semiconductor multilayer wiring structure comprising the step of forming a trench structure using an etch stop layer in a trench pattern.
도 1 내지 도 3은 본 발명의 바람직한 실시예에 따른 반도체 다층 배선 구조의 식각 저지층이 형성되기까지의 단계별 단면도,1 to 3 are step-by-step cross-sectional views of forming an etch stop layer of a semiconductor multilayer wiring structure according to a preferred embodiment of the present invention;
도 4는 본 발명에 따른 방법에 의해 식각 저지층과 반도체 다층 배선 구조를 형성하는 과정의 흐름도.4 is a flowchart of a process of forming an etch stop layer and a semiconductor multilayer interconnection structure by a method according to the present invention;
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
100 : 반도체 기판100: semiconductor substrate
102 : SiN층102: SiN layer
104 : 제 1 절연막104: the first insulating film
106 : 식각 저지층106: etching stop layer
108 : 제 2 절연막108: second insulating film
110 : 포토레지스트110: photoresist
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대하여 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
도 1은 본 발명의 바람직한 실시예에 따른 식각 저지층이 형성된 반도체 다층 배선 구조의 개략 단면도로서, 반도체 기판(100), SiN층(102), 제 1 절연막(104), 식각 저지층(106), 제 2 절연막(108) 및 산화물(110)로 형성되어 있다.1 is a schematic cross-sectional view of a semiconductor multilayer wiring structure in which an etch stop layer is formed in accordance with a preferred embodiment of the present invention, wherein the semiconductor substrate 100, the SiN layer 102, the first insulating film 104, and the etch stop layer 106 are formed. And the second insulating film 108 and the oxide 110.
도시한 바와 같이, 식각 저지층(106)은 바람직하게는 SiN, WN, TaN 등이 사용될 수 있으며, 더욱 바람직하게는 Si3N4가 사용될 수 있다.As shown, the etch stop layer 106 may be preferably SiN, WN, TaN and the like, more preferably Si 3 N 4 may be used.
제 1 및 제 2 절연막(104),(108)은 저 유전율 물질로 형성되어 있는데, 이러한 저 유전율 물질은 유기물과 무기물로 나뉠 수 있으며, 바람직하게는 SiOF, HSQ, MSQ, HOSP, 폴리머 등이 사용될 수 있다.The first and second insulating films 104 and 108 are formed of a low dielectric constant material, and the low dielectric constant material may be divided into organic and inorganic materials. Preferably, SiOF, HSQ, MSQ, HOSP, polymer, or the like may be used. Can be.
이하에서는, 도 1 내지 도 3의 단계별 단면도와 도 4의 흐름도를 참조하여 상술한 식각 저지층(106) 형성 과정을 보다 상세히 기술한다.Hereinafter, the process of forming the etch stop layer 106 described above will be described in detail with reference to the cross-sectional views of FIGS. 1 to 3 and the flowchart of FIG. 4.
즉, 도 4는 본 발명에 따른 방법에 의해 식각 저지층(106)과 반도체 다층 배선 구조를 형성하는 과정의 흐름도로서, 먼저, 도 1에 도시한 바와 같이, 반도체 기판상(100)에 제 1 절연막(104)을 형성한다(S200). 이러한 제 1 절연막(104)은 상술한 바와 같이 저 유전율 물질로 이루어진다.4 is a flowchart of a process of forming the etch stop layer 106 and the semiconductor multilayer wiring structure by the method according to the present invention. First, as shown in FIG. An insulating film 104 is formed (S200). The first insulating layer 104 is made of a low dielectric constant material as described above.
단계(S202)에서는 단계(S200)에서 형성된 제 1 절연막(104)상에 식각 저지층(106)을 형성한다. 이러한 식각 저지층(106) 형성 단계는 ALD(Atomic Layer Deposition) 기법을 사용하여 구현될 수 있다. ALD 기법이란 가스를 순차적으로 용기 내부에 유입하므로써 원하는 만큼의 두께로 증착이 가능하고 저 유전율의 물질 형성이 용이한 기법을 말하며, 이러한 ALD 기법을 이용한 식각 저지층(106) 형성 과정을 보다 상세히 기술한다.In step S202, an etch stop layer 106 is formed on the first insulating layer 104 formed in step S200. The etching stop layer 106 may be formed using an atomic layer deposition (ALD) technique. The ALD technique refers to a technique capable of depositing a desired thickness and easily forming a material having a low dielectric constant by introducing a gas into the container sequentially, and describes in detail the process of forming the etch stop layer 106 using the ALD technique. do.
먼저, 제 1 가스, 예컨대, SiCl4를 도시 생략된 챔버내로 유입시켜 화학 흡착시킨 후, 제 2 가스, 예컨대, N2를 챔버내로 1차 유입시켜 잔류물을 제거한다.First, a first gas, such as SiCl 4, is introduced into a chamber (not shown) for chemisorption, and then a second gas, such as N 2, is first introduced into the chamber to remove residues.
이후, 제 3 가스, 예컨대, NH3를 챔버내로 유입하여 화학 흡착시키고, 상술한 제 2 가스, 즉, N2를 챔버내로 2차 유입시켜 잔류물을 제거하는 과정으로 이루어진다.Thereafter, a third gas, for example, NH 3, is introduced into the chamber and chemisorbed, and the above-described second gas, that is, N 2 , is introduced into the chamber to remove the residue.
본 발명에서는 식각 저지층(106) 형성을 위한 이러한 ALD 기법을 순차적으로 반복 수행하므로써 원하는 두께의 막을 구현할 수 있도록 하였다. 즉, 본 발명에 따른 반도체 다층 배선 구조의 식각 저지층(106) 형성을 위해서 이러한 ALD 기법을 이용한 식각 저지층 형성 과정을 기설정 회수만큼 반복하도록 한 것이다.In the present invention, by repeatedly performing such an ALD technique for forming the etch stop layer 106, a film having a desired thickness can be realized. That is, in order to form the etch stop layer 106 of the semiconductor multilayer wiring structure according to the present invention, the etch stop layer formation process using the ALD technique is repeated by a predetermined number of times.
이때, 기설정 회수는 기설정 온도 영역에서 식각 저지층(106)이 기설정 두께로 형성될 때까지의 회수이며, 기설정 온도 영역은 바람직하게는 250℃ 내지 350℃로 설정될 수 있다(S204)(S206).In this case, the predetermined number of times is the number of times until the etch stop layer 106 is formed to a predetermined thickness in the predetermined temperature region, and the predetermined temperature region may be preferably set to 250 ° C. to 350 ° C. (S204). (S206).
한편, 상술한 공정들을 반복 수행하므로써 원하는 두께의 막이 형성되면, 단계(S208)로 진행한다.On the other hand, if the film of the desired thickness is formed by repeating the above-described process, the process proceeds to step S208.
단계(S208)에서는 이러한 식각 저지층(106)상에 저 유전율 물질인 제 2 절연막(108)을 형성한다.In operation S208, the second insulating layer 108, which is a low dielectric constant material, is formed on the etch stop layer 106.
또한, 단계(S210)에서는 제 2 절연막(108)상에 산화물(110)을 형성한다.In operation S210, the oxide 110 is formed on the second insulating layer 108.
이후, 단계(S212)에서는 도 2에 도시한 바와 같이, 포토레지스트 패턴을 형성하고 비아 홀(via hole)을 식각하며, 포토레지스트로 트렌치 패턴을 형성한다.Subsequently, in step S212, as shown in FIG. 2, a photoresist pattern is formed, via holes are etched, and a trench pattern is formed of the photoresist.
끝으로, 트렌치 패턴으로 식각 저지층(106)을 사용하여 트렌치 구조를 형성하므로써, 도 3과 같은 반도체 다층 배선 구조가 형성된다.Finally, by forming the trench structure using the etch stop layer 106 in the trench pattern, the semiconductor multilayer wiring structure as shown in FIG. 3 is formed.
이상 설명한 바와 같이, 본 발명은 반도체 다층 배선 구조 형성 과정에서의 식각 저지층 형성을 ALD 기법으로 순차 반복 수행하도록 구현하였다.As described above, the present invention was implemented to sequentially perform the etching stop layer formation in the process of forming the semiconductor multilayer interconnection structure by the ALD technique.
따라서, 본 발명은 원자 단위의 두께 조절이 가능하고 불순물을 줄이므로써 우수한 막질을 형성할 수 있으며, 저온 공정이 가능하므로 열 공정에 대한 문제점을 해결할 수 있다. 클러스터 시스템(cluster system)의 경우, ALD 시스템에 인-라인으로 층간 절연막을 형성하므로써 대기에 노출되어 생기는 문제점을 최소화 할 수 있다. 또한, 저 유전율의 식각 저지층을 형성하게 되므로 전체적인 유전율 상승을 방지할 수 있다.Therefore, the present invention can control the thickness of the atomic unit and can form an excellent film quality by reducing impurities, and can solve the problem of the thermal process because the low temperature process is possible. In the case of a cluster system, a problem caused by exposure to the atmosphere can be minimized by forming an interlayer insulating film in-line in the ALD system. In addition, since the low dielectric constant etch stop layer is formed, it is possible to prevent the overall dielectric constant increase.
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