KR100364838B1 - Processor for optimization of data transmission bandwidth and bandwidth optimization apparatus with the same - Google Patents

Abstract

The present invention is a data transmission bandwidth optimization dedicated processor and a bandwidth optimization device having the same. According to the present invention, in the compression operation, a frame of the HDLC type is received after compressing the remaining region except for the flag indicating the start, end, cancellation, and idle states through receiving one frame of the HDLC type used in the serial communication method on the network. Reconstruct to HDLC type frame after decompressing other area except for flag indicating start, end, cancel, dormant state by receiving HDLC type frame through other end. Once sent through.

As a result, it is installed between the data terminal equipment (DTE) and the data communication equipment (DCE) to compress and transmit the transmission data source of the DTE system to the DCE system side, and decompress the transmission data source of the DCE system to the DTE system side. This allows scaling to optimize channel bandwidth without the additional cost of conventional equipment replacement or channel expansion.

Description

PROCESSOR FOR OPTIMIZATION OF DATA TRANSMISSION BANDWIDTH AND BANDWIDTH OPTIMIZATION APPARATUS WITH THE SAME}

The present invention relates to an apparatus for optimizing a data transmission bandwidth, and more particularly, to an apparatus for optimizing a bandwidth optimization algorithm for a data frame on a network and having the same, thereby enabling a connection to a transmission path.

In order to transfer information generated by DTE (data terminal equipment) such as a computer or a terminal to a farther partner, the information must be converted into another type of signal, and a device that plays a role in converting the signal is DCE (Data Communication Equipment). ), And a typical example is a modem.

In general, there are two main methods of distinguishing existing implementation techniques for wide channel optimization.

The first is a built-in router device, which is a software form using a LZ-1 (LZ-1; Lempel-Ziv-1) -based dictionary-based lossless compression algorithm.

Next, the LZSS compression and decompression algorithm, which is a type of lossless compression algorithm, will be described with reference to the accompanying drawings.

1A is a flowchart illustrating a conventional LZSS compression algorithm.

Referring to FIG. 1A, first, the pre-buffer and the window buffer are initialized (step S110), and then a string to fill the window buffer is initialized (step S120).

Subsequently, the string is filled in the blank string (step S130), and it is checked whether the string exists in the dictionary buffer (step S140), and if the string exists, the feedback is fed back to step S130, and the string does not exist. In this case, the head information, for example, <1> is added to the compressed data having a length-position as a pair, and the head information, for example, <0> is added to the uncompressed data that outputs the original character. Output (step S150).

The window buffer is then shifted by compressed or uncompressed data bytes (step S160). According to this compression algorithm, the window buffer is always kept up to date, and the maximum length and position of the maximum string can be compressed according to whether the string filled in the window buffer and the string existing in the dictionary buffer match.

1B is a flowchart for explaining a conventional LZSS decompression algorithm.

Referring to FIG. 1B, after initializing the pre-buffer and the window buffer (step S210), it is checked whether the tag bit is <1> (step S220).

If the tag bit in the check of step S220 is not <1>, after performing the decompression operation, the original character is output, the window buffer is shifted by the decompressed length, and then fed back to step S250 (steps S230 and S250). If the tag bit is <1>, the decompression and the length-position are output as compressed data, and then the window buffer is shifted by the decompressed length and fed back to step S250 (steps S240 and S250).

Compared with the compression process, such a decompression process is omitted because the comparison process is omitted, and is easier to implement and easier to process in software than the compression process.

As described above, using the conventional compression algorithm has the advantage that complete recovery (decompression) of the compressed data is possible, and statistical knowledge of the source data is unnecessary.

However, after performing the compression or decompression (decompression) according to the procedure programmed with the algorithm described above, the data to be transmitted before performing the routing function is transmitted, and then the data is transmitted in synchronization with the fixed clock for transmitting and receiving. Existing resources such as CPU and memory have to be performed in parallel with basic operations such as routing and network-related processing.

Thus, dedicated hardware add-ons can be optionally used to support more robust compression / restoration, which is not very cost-effective in terms of cost / performance. The combination of the individual devices responsible for the function is dedicated to the decompression function of the data.

Such router-integrated type is dependent on router manufacturer's product because software or hardware method must exist in router product. Therefore, there is a problem in compatibility between different systems.

In addition, the second method for optimizing the wide channel is to solve the compatibility problem between the different systems in the router type, and the data terminal equipment (DTE) (for example, router, switch, gateway) and the data communication equipment (DCE) (For example, CSU, DSU, leased line modem).

The difference is that data that is properly programmed with the appropriate transport protocol (e.g. HDLC, PPP, etc.) is interpreted before being transmitted to the WAN or another LAN, and only the data within it is compressed and then reconstructed and transmitted according to the protocol. The receiver receives this, restores the compressed data in the frame, frames it with the corresponding protocol, and delivers it to the receiver router.

In order to perform such a function, a conventional device has a similar configuration to that of a router embedded hardware device, and a cost for implementing the same is higher than that of a router embedded product.

Accordingly, the present invention has been made in an effort to solve the above-mentioned problems, and an object of the present invention is to provide a single dedicated IC for an expensive hardware device, thereby facilitating a system configuration, and reducing a data transmission bandwidth. It is to provide a dedicated processor for optimization.

In addition, another object of the present invention is to provide a data transmission bandwidth optimization apparatus capable of connecting to a transmission path device such as a data terminal equipment (DTE) or a data communication equipment (DCE) by providing a processor for data transmission bandwidth optimization.

1A to 1B are flowcharts illustrating a conventional LZSS compression and decompression algorithm.

2 is a view for explaining a data transmission bandwidth optimization system according to the present invention.

3 is a diagram illustrating an apparatus for optimizing data transmission bandwidth connectable to a transmission path device according to an embodiment of the present invention.

4 is a diagram illustrating an example of a bandwidth optimization dedicated processor according to an embodiment of the present invention.

5 is a view for explaining a compression method using a data transmission bandwidth optimization method according to an embodiment of the present invention.

6 is a diagram for describing a decompression method using a data transmission bandwidth optimization method according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100: computer unit 200, 800: data terminal device (DTE)

300, 700: optimization device 400, 600: data communication device (DCE)

500: network 310: DTE connection

320, 350: differential amplifier 330: oscillator

340: dedicated processor 360: DCE connection

370: SRAM 3308, 3342, 3348, 3376: interface unit

3310 and 3350: first frame search unit 3320: clock generator

3330: Compression unit 3340, 3370: Frame generation unit

3360: decompression unit

A processor for optimizing data transmission bandwidth according to one feature for realizing the above object of the present invention,

In the compression operation, the HDLC type frame used for serial communication on the network is received through one end, and the remaining area is compressed except for the flags indicating start, end, cancellation, and idle states, and the other end is reconfigured into the HDLC type frame. Through the

In the decompression operation, the frame of the HDLC type is received through the other end, and the remaining region except for the flag indicating the start, end, cancellation, and idle states is decompressed, and then reconfigured into a frame of the HDLC type and transmitted through one end.

In addition, a data transmission bandwidth optimization device that can be connected to a transmission path device according to one feature for realizing another object of the present invention, is connected to the data terminal equipment (DTE) and data communication equipment (DCE), respectively, and compressed A data transmission bandwidth optimization device for receiving compressed or uncompressed data and compressing or decompressing the data using a predetermined compression or decompression algorithm to transmit the compressed or decompressed data.

In the compression operation, the HDTE-type frame used for serial communication in the network is received from the DTE through one end, and the remaining area is compressed except for the flags indicating start, end, cancellation, and idle states, and then reconstructed into an HDLC-type frame. To the DCE via the other end,

In the decompression operation, a frame of the HDLC type is received from the DCE through the other end, and after decompressing the remaining areas except for the flag indicating the start, end, cancellation, and dormancy states, the DLC is reconfigured into a frame of the HDLC type to perform the DTE through one end. To transmit.

Here, the apparatus for optimizing data transmission bandwidth includes a DTE connection unit for receiving uncompressed data from a DTE connected through one end and outputting the uncompressed data through the other end; A first differential amplifier receiving and amplifying uncompressed data from the DTE connection unit and outputting amplified uncompressed data; A DCE connection unit receiving compressed data from a DCE connected through one end and outputting the compressed data through the other end; A second differential amplifier receiving and amplifying the compressed data from the DCE connection unit and outputting the amplified compressed data; An oscillator for outputting a predetermined oscillation frequency; And in the compression operation, receives the amplified uncompressed data output from the first differential amplifier based on the oscillation frequency, losslessly compresses the output, outputs the lossless compressed data to the second differential amplifier, and decompresses the operation. Preferably, a bandwidth optimization processor is provided that receives amplified compressed data output from the second differential amplifier based on the oscillation frequency, and performs lossless decompression and outputs the lossless decompressed data to the first differential amplifier. .

In addition, the dedicated bandwidth optimization processor receives uncompressed bit-oriented serial data input from the outside and performs frame search operation to find and remove the position of '0' bit supplemented to separate data areas, A first frame search unit for converting and outputting the converted frame;

A clock generator for receiving a system clock and a reset signal input from the outside and outputting a clock signal for data flow control between the DTE and the DCE;

A compression unit configured to recompress and output a frame in the HDLC type after compressing all the regions except for the flag indicating the start, end, cancellation, and idle states in the HDLC type frame used in the serial communication method on the network; Receives compressed data provided from the compression unit, generates start and end flags, supplements '0' bits, generates CRC, converts the compressed parallel data into a frame that satisfies the bit-oriented protocol, and then converts the converted data. It is preferable to include a first frame generator for outputting data.

In addition, the dedicated bandwidth optimization processor divides the data area from the bit-oriented serial input, finds and removes the supplementary '0' bit position, and converts the bit-oriented data from which the '0' bit is removed into parallel data in bytes. A second frame search unit outputting the timing based on the timing;

A decompressing unit configured to decompress all remaining regions except for flags indicating start, end, cancellation, and dormancy in the HDLC type frame used for the serial communication method on the network, and then reconstruct and output the frame in the HDLC type; Receive the decompressed data from the decompressor based on the output timing, generate start and end flags, supplement '0', generate CRC, and convert the compressed parallel data into a frame that satisfies the bit-oriented protocol. After that, it is preferable to include a second frame generator for outputting the converted data.

According to such a processor dedicated to data transmission bandwidth optimization and an optimization apparatus having the same, it is installed between a data terminal equipment (DTE) and a data communication equipment (DCE) to compress and transmit a transmission data source of a DTE system to a DCE system side, and a DCE system. By decompressing and transmitting the data source to the DTE system side, it can be extended to optimize the channel bandwidth without additional cost for conventional equipment replacement or channel expansion.

Then, embodiments will be described so that those skilled in the art can easily implement the present invention.

2 is a view for explaining a data transmission bandwidth optimization system according to the present invention.

2, a data transmission bandwidth optimization system according to the present invention includes a plurality of computer units 100, a first data terminal device (DTE) 200 connected thereto, a first optimization device 300, and a first data communication. Device (DCE) 400, network 500, second DCE 600, second optimization device 700, second DTE 800, and multiple computer units 900, including DTE or DCE In order to transmit data to a farther partner, the data bandwidth is optimized and transmitted.

In this case, the data terminal equipment (DTE) may be implemented as a kind of router, switching, gateway, and the like, and the data communication equipment (DCE) that performs signal conversion may be implemented as a CSU, a DSU, a dedicated line modem, or the like.

The first and second optimization apparatuses 300 and 700 compress all the remaining regions except for flags indicating start, end, cancellation, and idle states in HDLC type or PPP type frames used in a serial communication method on a network. After that, a frame of HDLC type or PPP type is reconstructed and transmitted to DCE side or DTE side.

This frame reconstruction operation increases the DTE output synchronization clock according to whether or not the input data is compressible, thereby efficiently using the fixed bandwidth of the DCE side, thereby maximizing the bandwidth.

In addition, if the transmission bandwidth of the DCE side is T1 based on a lossless compression algorithm, for example, the average compression ratio of LZSS 150%, the DTE side operates at the E1 level.

Here, the transmission lines connected to the first and second DCE 400 (600) and the network 500 side are preferably wired or wireless transmission lines having a fixed bandwidth.

Next, the first and second data transmission bandwidth optimization apparatuses 300 and 700 mentioned in FIG. 2 will be described in more detail with reference to the accompanying drawings.

3 is a diagram illustrating an apparatus for optimizing data transmission bandwidth connectable to a transmission path device according to an embodiment of the present invention.

Referring to FIG. 3, a data transmission bandwidth optimization device connectable to a transmission path device according to an embodiment of the present invention includes a DTE connection unit 310, a first differential amplifier 320, an oscillator 330, and a bandwidth optimization dedicated processor 340. ), A second differential amplifier 350, a DCE connection 360, and an SRAM 370.

The DTE connection unit 310 is connected to the DTE 200 through one end, receives uncompressed data from the connected DTE 200, and outputs the uncompressed data to the first amplifier 320 through the other end.

The first differential amplifier 320 receives uncompressed data from the DTE connection unit 310 and amplifies the data using a predetermined amplification ratio, and outputs the amplified uncompressed data to the bandwidth optimization processor 350.

The oscillator 330 outputs a predetermined oscillation frequency G clk to the bandwidth optimization dedicated processor 340. The oscillation frequency output here is preferably an integer multiple of 8.192 MHz.

During the compression operation, the bandwidth optimization dedicated processor 340 receives the amplified uncompressed data output from the first differential amplifier 320 through the first stage based on the oscillation frequency, and losslessly compresses the data. Is output through the second stage.

In addition, during the decompression operation, the bandwidth optimization dedicated processor 340 receives the amplified compressed data output from the second differential amplifier 350 through the third stage based on the oscillation frequency, and performs lossless compression. The released data is output through the fourth stage.

In more detail, the bandwidth optimizing processor 340 outputs the first control signal R_TXC to the first differential amplifier 320 and, when the falling edge of the first control signal R_TXC falls, the first data ( When R_TXD is received from the first differential amplifier 320 and the compression operation is performed, when the second control signal D_TXC is applied from the second differential amplifier 350, the second data amplifier D_TXD is converted into a second differential amplifier ( To 350).

The second differential amplifier 350 receives the compressed data output from the bandwidth optimization processor 340 and amplifies the compressed data based on a predetermined amplification rate, and outputs the amplified compressed data to the DCE connector 360.

The DCE connector 360 receives compressed data provided from the second differential amplifier 350 and provides the compressed data to the DSU 400.

In the above description, the compression operation provided to the DCE 400 after being compressed using a lossless compression algorithm by receiving uncompressed data from the DTE 200 has been described. On the contrary, the compressed data is provided from the DCE 400. The decompression operation provided to the DTE 200 after the restoration is performed using a lossless restoration algorithm is easily understood by those skilled in the art, and thus description thereof will be omitted.

Meanwhile, in the exemplary embodiment of the present invention, the compressed or uncompressed data is output in real time as an example. However, when the data input from the DTE is compressed using the SRAM 370 illustrated in FIG. It acts as a buffer to prevent data expansion that can occur in LZSS, and can also temporarily save data and output it.

In more detail, in a compression operation, when the data input through the first differential amplifier 320 is compressed data, a first memory block (not shown) for storing the compressed data first, and If the data input via the first differential amplifier 320 is uncompressed data, the apparatus further includes a second memory block (not shown) for storing the uncompressed data for the second time. In this case, the second compression process is canceled to prevent expansion of the compressed data.

Next, an example of the bandwidth optimization dedicated processor mentioned in FIG. 3 will be described in detail with the accompanying drawings.

4 is a view for explaining an example of a bandwidth optimization dedicated processor according to an embodiment of the present invention, it is possible to perform a compression operation and a decompression operation on a single chip.

4, a bandwidth optimization processor according to an embodiment of the present invention includes a first interface unit 3308, a first frame seeker 3310, a clock generator 3320, and a compressor 3330. , A first frame maker 3340, a second interface unit 3332, a third interface unit 3348, a second frame search unit 3350, a decompressor 3360, and a second frame generation The unit 3370 and the fourth interface unit 3336 are included.

The first frame search unit 3310 includes a first frame searcher 3312 and a first receiving interface 3314, which is synchronized with a clock provided from the clock generator 3320 via the first interface unit 3308. The uncompressed data R_txd is received from the first differential amplifier 320 to perform a frame search operation, and then output to the compression unit 3330.

More specifically, the first frame finder 3312 separates the data area from the uncompressed data R_txd inputted as a bit-oriented serial type, finds and removes the supplementary '0' bit position, and then removes the '0' bit. The bit-oriented data is converted into parallel data in units of bytes and then output to the first receiving interface 3314.

The first receiving interface 3314 adjusts the output timing of the parallel data input from the first frame searcher 3312 and transmits the adjusted timing to the compression unit 3330.

The clock generator 3320 receives a system clock DTE Sync Clk and a reset signal Rst from an external source, and receives the clock signal from the first receiving interface 3314, the compressor 3330, and the decompressor 3360. The DTE Sync Clk is outputted to the DTE 200 connected to the outside.

More specifically, the clock generator 3320 may buffer the packet buffer (not shown) in the compression unit 3340 and the pre-buffer (not shown) in the decompression unit 3360 based on a system clock, for example, 16.384 MHz. By generating a synchronization clock for transmitting / receiving the DTE side which varies according to the progress, the division function is performed by the automatic call flow control function and the internal processing clock for decompression.

The compression unit 3330 recompresses the first frame by compressing all the remaining areas except for the flag indicating the start, end, cancellation, and idle state in the HDLC type frame used in the serial communication method on the network. Output to the generation unit 3340. The compression algorithm used here uses a Lempel-Ziv-Lempel-Ziv-Storer-Szymanski (LZSS) lossless compression scheme. Here, HDLC (High-level Data Link Control) is an international standard data link protocol used for transmission control over a point-to-point communication line. Typically, the data link protocol is widely used based on the HDLC standard. The HDLC protocol was an asynchronous data link control (SDLC) protocol developed for IBM's Systems Network Architecture (SNA) in the early 1970s. HDLC is a bit-oriented protocol in which data is transmitted one frame over the link.

The first frame generator 3340 includes a second receiving interface 3332 and a first frame generator 3344 to receive compressed data provided from the compression unit 3330 and pass through the second interface unit 3332. And output to the second differential amplifier 350.

In more detail, the second receiving interface 3332 receives the compressed data from the compressor 3330, adjusts the output timing, and outputs the compressed data to the first frame generator 3344.

The first frame generator 3344 receives the compressed data from the compression unit 3330 via the second receiving interface 3332, generates start and end flags, supplements '0', and cyclic redundancy check. ) And converts the compressed parallel data into a frame that satisfies the bit-oriented protocol, and outputs the converted data to the second differential amplifier 350 through the second interface 3346.

The second frame search unit 3350 is composed of a second frame searcher 3332 and a first transmission interface 3354, and provides compressed data provided from the second differential amplifier 350 via the third interface unit 3348. Receives and outputs to the decompression unit (3360).

In more detail, the second frame finder 3332 identifies and removes the zero bit position supplemented by dividing the data area from the bit-oriented serial input, and then converts the bit-oriented data from which the zero bit is removed as parallel data in bytes. After conversion, the data is output to the first transmission interface 3354.

The first transmission interface 3354 adjusts the output timing of the parallel data input from the second frame searcher 3332 and transmits the adjusted timing to the decompression unit 3360.

The decompressor 3360 decompresses all areas except the flags indicating start, end, cancel, and dormancy in the HDLC type frame used in the serial communication method on the network, and then reconstructs the frame using the HDLC type. Outputs to the two frame generator 3370. The decompression algorithm used at this time uses a lossless decompression method of Lempel-Ziv-1 series LZSS.

The second frame generator 3370 includes a second transmission interface 3372 and a second frame generator 3374, and receives the decompressed data provided from the decompressor 3360 to receive the fourth interface 3333. Output to the first differential amplifier 320 via.

More specifically, the second transmission interface 3372 receives the compressed data from the decompression unit 3360, adjusts the output timing, and outputs the compressed data to the second frame generator 3374.

The second frame generator 3374 receives the compressed data from the decompressor 3360 via the second transmission interface 3372, generates start and end flags, supplements '0', and generates a CRC. After converting the compressed parallel data into a frame satisfying the bit-oriented protocol, the converted data is output to the second differential amplifier 350 via the fourth interface 3374.

Next, the compression and decompression operations of the bandwidth-optimized processor, which is the core of the present invention, will be described in more detail with reference to FIGS. 5 and 6.

First, as an example of the compression operation according to the present invention, as shown in FIG.

5 is a view for explaining a compression method using a data transmission bandwidth optimization method according to an embodiment of the present invention.

As shown in Fig. 5, a window buffer is used to store new data and identify a new string of data that matches any data previously received and stored in the prior buffer. Thus, new data strings, which are typically alphanumeric characters and that match existing strings, can be identified simply by referring to the offset and length of the first point of the string sequence in the window buffer. As expected, the LZSS algorithm becomes more effective as the size of the window buffer increases and the repetition of the pattern of data characters in the window buffer increases.

The first task of the encoder is to find the longest prefix match where the string in the window buffer exactly matches the dictionary buffer. Here, the length of the longest match is part of the token provided by the encoder and the position or offset in the dictionary buffer where the match is located is another part of the token provided by the encoder.

Briefly describing the compression operation, since there are five 'B' words in the output buffer of the window buffer at the time '0', the first buffer is considered to be a match, and at the time '1', it is located at the output of the window buffer. Since there are 5 'e' words in the pre-buffer, the matching is also considered. Since the 't' word is located in the output of the window buffer at the time '2', the pre-buffer is considered to be the maximum. As the output code, '0', '3', and '1' are output as the start position (Cp) of the maximum string, the size of the maximum string (Cl), and the information bit (Ci), respectively. Since the word 'a' located at the output of the window buffer does not exist in the pre-buffer, it is considered not to be matched. Therefore, as the output code, the characters 'a' and '0' are used as the mismatch characters (Cu) and information bits (Ci), respectively. Exodus The.

Hereinafter, the compression operations from time '4' to time '8' also output 'B', '4', and '1' for Cp, Cl, and Ci through the same operation as described above. The above-mentioned information bit Ci is represented by one byte per eight output code units, and as a result, one information byte per eight output codes is output in advance.

The following is an example of the decompression operation according to the present invention. As shown in FIG. 6, a 16-word pre-buffer is used, and the LZSS algorithm is used.

6 is a diagram for describing a decompression method using a data transmission bandwidth optimization method according to an embodiment of the present invention.

Referring to FIG. 6, the decompression process begins with the reception of HDLC framed serial data of the packet generated during the compression process. Once the received data passes through the second frame searcher 3332 and the first transmission interface 3354, the first data searcher 3312 and the first reception interface 3314 mentioned in the compression process are performed. Same operation as The received string of each received code thus processed is delivered to the decompression unit.

The data string once passed to the decompressor is stored in the window buffer. When the window buffer fills at least 6 bytes, the data of the first address stored is read. Since the received data string is a character string compressed through the compression unit on the other side, the first byte after the flag indicating the final start is always an information byte. Based on this value, it is determined whether or not a string of 8 to 16 bytes is a compressed code, and the restored values are sequentially stored in the pre-buffer.

As described above, the present invention intends to more efficiently use the existing high-cost dedicated line. In other words, by installing the present invention without replacing the equipment operating on the existing dedicated line, the existing fixed band (for example, 56Kbps ~ T1 / E1, etc.) can be improved by up to 400% depending on the type of data transmitted. .

Therefore, the leased line can be effectively used at the same rental cost. In addition, the existing products of the above-described purpose is difficult to use the actual situation in terms of cost-effective because of its high price, the present invention can innovatively reduce the price by making the compression recovery function as a single processor.

In addition, as a core semiconductor used in the present invention, the point-to-point connection method can be used for the decompression necessary portion of all serial data of the HDLC type.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

As described above, according to the present invention, it is installed between the data terminal equipment (DTE) and the data communication equipment (DCE) to compress the transmission data source of the DTE system and transmit it to the DCE system side, and decompress the transmission data source of the DCE system. By transmitting to the DTE system side, it can be extended to optimize channel bandwidth without additional cost for conventional equipment replacement or channel expansion.

In addition, the compression or decompression method is implemented by adopting the hardware method rather than the software. Also, by developing a dedicated DSP core on a single chip, it can be easily used, system performance can be improved, and the price can be improved. In terms of performance, it may be competitive compared to conventional techniques implemented to optimize data transmission bandwidth.

Claims (10)

In the compression operation, the HDLC type frame used for serial communication on the network is received through one end, and the remaining area is compressed except for the flags indicating start, end, cancellation, and idle states, and the other end is reconfigured into the HDLC type frame. Through the In the decompression operation, the HDLC type frame is received through the other end, and after decompressing the remaining areas except for the flag indicating the start, end, cancellation, and idle states, the HDLC type frame is reconfigured into an HDLC type frame and transmitted through one end. Dedicated processor for data transfer bandwidth optimization. The method of claim 1, The dedicated processor for data transmission bandwidth optimization is a data transmission bandwidth optimization processor, characterized in that implemented in one chip. The method of claim 1, The dedicated processor for data transmission bandwidth optimization, A first method of receiving and compressing uncompressed bit-oriented serial data input from the outside to perform a frame search operation to find and remove a position of '0' bits supplemented to distinguish a data area, and to convert the data into byte-by-byte parallel data and output the same. A frame search unit; A clock generator for receiving a system clock and a reset signal input from an external device and outputting a clock signal; A compression unit configured to recompress and output a frame in the HDLC type after compressing all the regions except for the flag indicating the start, end, cancellation, and idle states in the HDLC type frame used in a serial communication method on a network; And Receives compressed data provided from the compression unit, generates start and end flags, supplements '0' bits, generates CRC, converts the compressed parallel data into a frame that satisfies the bit-oriented protocol, and then converts the converted data. First frame generator for outputting data Dedicated processor for data transmission bandwidth optimization comprising a. The method of claim 1, The dedicated processor for data transmission bandwidth optimization, By dividing the data area from the bit-oriented serial input, finding and removing the supplementary '0' bit position, and converting the bit-oriented data from which the '0' bit is removed into parallel data in units of bytes and outputting the data based on a predetermined output timing. A second frame search unit; A decompression unit configured to decompress and output a frame in the HDLC type after decompressing all the areas except for the flag indicating the start, end, cancellation, and dormancy in the HDLC type frame used in a serial communication method on a network; And Receive the decompressed data from the decompressor based on the output timing, generate start and end flags, supplement '0', generate CRC, and convert the compressed parallel data into a frame that satisfies the bit-oriented protocol. The second frame generator for outputting the converted data Dedicated processor for data transmission bandwidth optimization comprising a. Connected to the data terminal equipment (DTE) and the data communication equipment (DCE), respectively, and receive compressed or uncompressed data to compress or decompress using a predetermined compression or decompression algorithm to transmit the compressed or decompressed data. In the data transmission bandwidth optimization apparatus, In the compression operation, the HDTE-type frame used for serial communication in the network is received from the DTE through one end, and the remaining area is compressed except for the flags indicating start, end, cancellation, and idle states, and then reconstructed into an HDLC-type frame. To the DCE via the other end, In the decompression operation, a frame of the HDLC type is received from the DCE through the other end, and after decompressing the remaining areas except for the flag indicating the start, end, cancellation, and dormancy states, the DLC is reconfigured into a frame of the HDLC type to perform the DTE through one end. And a data transmission bandwidth optimization apparatus. The method of claim 5, The data transmission bandwidth optimization device, A DTE connection unit which receives uncompressed data from a DTE connected through one end and outputs it through the other end; A first differential amplifier receiving and amplifying uncompressed data from the DTE connection unit and outputting amplified uncompressed data; A DCE connection unit receiving compressed data from a DCE connected through one end and outputting the compressed data through the other end; A second differential amplifier receiving and amplifying the compressed data from the DCE connection unit and outputting the amplified compressed data; An oscillator for outputting a predetermined oscillation frequency; And In the compression operation, the amplified non-compressed data output from the first differential amplifier is received based on the oscillation frequency and losslessly compressed, and the lossless compressed data is output to the second differential amplifier, In the decompression operation, a bandwidth optimization dedicated processor receives lossless decompression received amplified compressed data output from the second differential amplifier based on the oscillation frequency and outputs lossless decompressed data to the first differential amplifier. Data transmission bandwidth optimization device comprising a. The method of claim 6, The bandwidth optimization dedicated processor is a data transmission bandwidth optimization device, characterized in that implemented in one chip. The method of claim 6, The bandwidth optimization dedicated processor, In the compression operation, when the data input via the first differential amplifier is compressed data, the first memory block for storing the compressed data first and the data input via the first differential amplifier are stored. In the case of uncompressed data, the data transmission bandwidth optimization apparatus further comprises a second memory block for storing the second uncompressed data, thereby preventing expansion of the data. The method of claim 6, The bandwidth optimization dedicated processor, A first method of receiving and compressing uncompressed bit-oriented serial data input from the outside to perform a frame search operation to find and remove a position of '0' bits supplemented to distinguish a data area, and to convert the data into byte-by-byte parallel data and output the same. A frame search unit; A clock generator for receiving a system clock and a reset signal input from the outside and outputting a clock signal for controlling data flow between DTE DCEs; A compression unit configured to recompress and output a frame in the HDLC type after compressing all the regions except for the flag indicating the start, end, cancellation, and idle states in the HDLC type frame used in a serial communication method on a network; And Receives compressed data provided from the compression unit, generates start and end flags, supplements '0' bits, generates CRC, converts the compressed parallel data into a frame that satisfies the bit-oriented protocol, and then converts the converted data. First frame generator for outputting data Apparatus for optimizing data transmission bandwidth comprising a. The method of claim 6, The bandwidth optimization dedicated processor, By dividing the data area from the bit-oriented serial input, finding and removing the supplementary '0' bit position, and converting the bit-oriented data from which the '0' bit is removed into parallel data in units of bytes and outputting the data based on a predetermined output timing. A second frame search unit; A decompression unit configured to decompress and output a frame in the HDLC type after decompressing all the areas except for the flag indicating the start, end, cancellation, and dormancy in the HDLC type frame used in a serial communication method on a network; And Receive the decompressed data from the decompressor based on the output timing, generate start and end flags, supplement '0', generate CRC, and convert the compressed parallel data into a frame that satisfies the bit-oriented protocol. The second frame generator for outputting the converted data Apparatus for optimizing data transmission bandwidth comprising a.