KR100361392B1 - Method for forming memory cells and device formed thereby, and method for forming a horizontal surface spacer and device formed thereby - Google Patents

Abstract

The preferred embodiment of the present invention overcomes the limitations of the prior art by providing a method of forming a source / drain diffuser that improves the uniformity of channel length in a vertical transistor structure. In one embodiment, the present invention is used to form source / drain and bitline diffusion structures for use in pillar memory cells. In another embodiment, the present invention is also used to form source / drain and plate diffusion structures in pillar-type memory cells. Both of these preferred embodiments deposit conforming photoresist on the pillar like structure and use an off-axis exposure process to sink the dopant source layer along the pillar to the appropriate depth. The recessed dopant source layer may then be used to form source / drain / bitline diffusers or source / drain / plate diffusers in the filler memory device.

The present invention also provides a method of forming self-aligned spacers on a horizontal surface while removing spacer material on the vertical surface. According to this preferred method, a resist is used which is insoluble in the developer by implanting ions. By consistently depositing a resist on a substrate having both a vertical surface and a horizontal surface, implanting the resist and then developing the resist, the resist on the vertical surface is removed while the resist on the horizontal surface remains. Thus, self-aligned spacers are formed on the horizontal surface while spacer materials on the vertical surface are removed. Such horizontal surface spacers can be used in subsequent manufacturing processes. This preferred method can be used in many different processes that need to treat the vertical and horizontal surfaces of the substrate 20 differently.

Description

TECHNICAL FOR FORMING MEMORY CELLS AND DEVICE FORMED THEREBY, AND METHOD FOR FORMING A HORIZONTAL SURFACE SPACER AND DEVICE FORMED THEREBY}

TECHNICAL FIELD The present invention generally relates to the field of semiconductor manufacturing, and more particularly, to a method of forming a filler memory cell.

In the manufacture of semiconductor devices, device densities of integrated circuits continue to increase in order to be competitive in cost and performance. In order to easily increase device density, new techniques are always needed to reduce the feature size of semiconductor devices.

Pressure to increase device density is particularly strong in the dynamic random access memory (DRAM) market. DRAM devices are widely used in computer applications, which require a large amount of memory that is cheap but relatively high performance. As more advanced applications are developed, the increased amount of RAM is required. This further increased the need for larger device densities and cheaper methods of manufacturing these devices.

A typical DRAM chip consists of millions of individual DRAM cells. Each cell includes a capacitor used to charge the memory, a switch used to access the capacitor, and several isolation regions around these devices. Each cell is accessed using multiple bit lines and word lines. By selecting the appropriate bitline and wordline, the memory controller can access the information contained within the desired DRAM cell.

The density of a DRAM chip is largely determined by the area required for each DRAM cell. One particular area of concern with DRAM designs is the storage capacitor required to store each memory cell. The density of a DRAM design is quite limited by the feature size of the storage capacitor. Literally, the capacitor stores the charge between the electrodes.

The charge stored in the storage capacitors is likely to leak into the current, which is why the DRAM must be refreshed periodically. The time allowed between refreshes without leakage of excess charge is the data retention time, which is determined by the amount of charge stored at the beginning of the storage cycle and the amount of leakage current through different types of leakage mechanisms. For various reasons, it is desirable to minimize the leakage mechanism in order to increase the time allowed between refresh cycles.

Several methods have been used to easily reduce cell feature size while maintaining sufficient capacitance. One such method is the use of pillar transistors in which stacked capacitors are placed on top of the transistor, which is often referred to as pillar DRAM cells. In one embodiment of the pillar type DRAM cell, the array channel device is bounded by an implant of the top of the pilar and a buried plate of the base of the pilar . In another embodiment, the array channel device is distinguished by an implanted bitline on top of the filler and a buried bitline. Today, these buried plates and bitlines are made by filling the filler structure with organic material and digging it out using a chemical etching process to form depressions. The degree of depression controls the channel length of the transfer device, thereby determining the depth of the buried plate or bitline. Unfortunately, methods of making depressions in materials usually result in loading effects with significant nonuniformity. This comprehensively large tolerance can result in a change in channel length, leading to timing problems.

Also, in DRAM devices, it is desirable to minimize the blocking current, so transfer devices are typically designed to have relatively long channels. In this way, the transmission device can be operated with a large difference from the threshold voltage. Unfortunately, due to current processes having non-uniform channel lengths, devices need to operate at a slower speed than their optimum speed.

Thus, conventional methods of forming plates and bitlines in pillar-type DRAM devices have serious non-uniformity problems, with the result that channel lengths undesirably change, severely degrading device performance.

In addition, one of the basic techniques in semiconductor manufacturing is the use of sidewall spacers. Typical sidewall spacers are formed by conformal deposition of spacer material on a structure, followed by directional etching, the disclosure of which is invented by Fogg and assigned to International Business Machines, Inc. US Patent No. 4,256,514 to "Method for Forming a Narrow Dimensioned Region on a Body." Directional etching removes all spacer material from the horizontal surface of this structure but leaves the spacer on the vertical surface. Spacer material is deposited conformally on the structure to form the sidewall spacers, covering the horizontal and vertical surfaces. Next, directional etching is performed. This directional etching removes the material on the horizontal surface, while the material on the sidewall remains intact to form sidewall spacers. This space is essentially self-aligned with the sidewalls. Sidewall spacers may be used in a variety of applications for a variety of reasons. For example, the use of sidewall spacers is particularly useful in the formation of FETs. In this application, sidewall spacers are formed on the sidewalls of the transistor gates and used to protect the gate to improve dopant control at the gate edge.

Unfortunately, sidewall spacers have some weaknesses. The most serious vulnerability is that sidewall spacers, as the name suggests, form only on the vertical surfaces or sidewalls of the structure. Thus, there is no simple way to form essentially self-aligned spacers on the horizontal surface while removing all of the spacer material from the vertical surface. Such horizontal surface spacers can be used in a variety of applications, for example, when the processing needs to be done selectively on the vertical surface while protecting the horizontal surface.

Thus, there is a need for a self-aligning spacer design that removes from the vertical surface while covering the horizontal surface.

Therefore, the present invention provides a method of forming a source / drain diffusion at the base of a pillar in a vertical transistor structure, thereby improving the uniformity of the channel length. In one embodiment, the present invention is used to form source / drain and bitline diffusion structures for use in pillar-type memory cells. Also as another embodiment, the present invention is used to form source / drain and plate diffusion structures in pillar-type memory cells. These two preferred embodiments deposit a matching photoresist on the filler structure and recess the dopant source layer to a suitable depth along the filler using an off-axis ion implantation process. The recessed dopant source layer may then be used to form source / drain / bitline diffusions or source / drain / plate diffusions in the filler memory device.

The present invention also provides a method of forming a self-aligning spacer on a vertical surface while removing the spacer material from the vertical surface. According to a preferred method, a resist is used which is insoluble in the developer by implanting ions. By conformally depositing resist on a substrate having vertical and horizontal surfaces, implanting the resist and then developing the resist, the resist on the vertical surface is removed while the resist on the horizontal surface remains. Thus, self-aligned spacers are formed on the horizontal surface while spacer materials on the vertical surface are removed. Such horizontal surface spacers can be used in subsequent manufacturing processes. This preferred method can be used in many different processes that need to treat the vertical and horizontal surfaces of the substrate 20 differently.

The preferred method of forming the horizontal surface spacers is done without making the processing too complex. Preferred methods of forming horizontal surface spacers can be used in many different processes where the vertical and horizontal surfaces of the substrate need to be treated differently.

As one application for the preferred method, the matching resist may include such as dopants, for example arsenic. After forming the horizontal surface spacers, the substrate is annealed to allow the dopant to diffuse to adjacent horizontal surfaces. This formation can then be used to selectively form conductive lines such as, for example, bit lines on this horizontal surface.

The above and other advantages of the present invention and the features of the present invention will become more apparent from the following detailed description of the preferred embodiment of the present invention as illustrated in the accompanying drawings.

1 is a flow diagram illustrating a preferred method of forming a source / drain / buried conductor diffusion;

2-9 are cross-sectional views of wafer portions during a process in accordance with a preferred embodiment of the present invention;

10 is a flow chart illustrating a preferred method of forming a horizontal surface spacer;

11-14 are cross-sectional views of portions of a wafer during processing in accordance with a preferred embodiment of the present invention;

15-16 are cross-sectional views of a portion of a wafer during formation of buried bitlines, in accordance with a preferred embodiment;

17 is a cross-sectional view of a portion of a wafer after forming a high performance MOSFET in accordance with a preferred embodiment.

Explanation of symbols for the main parts of the drawings

202, 1202: wafer

Filler: 208, 210, 212, 1208, 1210, 1212

302: dopant source layer 304, 1302: resist layer

602, 604, 1804, 1806: diffusion portion 702: gate electrode

704 source / drain / plate diffuser

801, 802, 803, 804: source / drain / bitline diffuser

902 gate / word line 1204, 1206 trench

1502: horizontal surface spacer 1601: diffusion barrier layer

1702, 1704: conductive bit line 1808: polysilicon gate

1810: Gate Insulator

Preferred embodiments of the invention will be described hereinafter with the accompanying drawings in which like reference numerals designate like elements.

The preferred embodiment of the present invention overcomes the limitations of the prior art, and provides a method of forming a source / drain diffuser that improves the uniformity of channel length in a filler memory cell. According to a preferred method, a dopant source layer is recessed along the filler to a suitable depth using a matching photoresist and a shadowing process. Thereafter, the recessed dopant source layer may be used to form source / drain diffusions in the transmission device.

In Embodiment 1, the pillar-type memory cell uses a buried plate to connect common sources / drains of all the memory cells. In this embodiment the buried plate is formed with a source / drain diffuser. In this embodiment, the bit lines form independent wiring levels at the top to connect one side of the storage capacitor to the other side connected to the top of the pillar.

In Embodiment 2, the pillar-type memory cells connect one row of memory cells together using buried bit lines. In this embodiment, the buried bitline is common to the source / drain diffusions. In this embodiment, the plate is used to connect one side of all storage capacitors together, with the other side of the storage capacitor connected to the corresponding source / drain on the top of the filler.

As those skilled in the art will appreciate, a bit line and a plate are both conductive paths that connect several memory cells, and the bit lines can be used to selectively access memory cells by connecting one row of memory cells, and the plates together all capacitors with a common reference voltage. You will notice that it connects to. Accordingly, the term buried conductor referred to herein is meant to include both the buried plate of Example 1 and the buried bit line of Example 2. Similarly, source / drain is a generic term for either source diffusion or drain diffusion.

Although preferred embodiments have been described with reference to forming source / drain diffusers, bit lines, and plates in a DRAM device, other types of memory devices, such as DRAM variants (extended data output DRAM, burst extended data output DRAM, synchronization) DRAM, etc.), and the formation of SRAM (Static Random Access Memory) and its variants (asynchronous SRAM, synchronous SRAM, pipelined burst SRAM, etc.). Also, the methods of the preferred embodiment can be used to form source / drain diffusions for transistors in non-memory cells, such as logic circuits, for example.

Referring now to FIG. 1, FIG. 1 illustrates a method 100 of forming a source / drain diffuser in accordance with a preferred embodiment. This method 100 will be illustrated in FIGS. 2-7 with reference to Embodiment 1, which, according to Embodiment 1, also defines a buried plate that connects the memory cells together.

The first step 102 is to provide a suitable semiconductor wafer. Preferably the wafer will comprise a suitably doped silicon substrate, but may include other semiconductor materials such as, for example, GaAs. SOI wafers are also available.

The next step 104 is to etch the trench in the wafer to define the filler. This is done using any suitable etching process. For example, as one method, forming a nitride pad layer after forming a thin oxide film on a wafer is mentioned. Next, a photoresist is deposited and patterned on this nitride. Thereafter, the nitride and oxide are etched using the patterned photoresist. Remove the resist. The remaining nitrides and oxides are now used as etching masks to etch the trenches using a suitable etchant. Of course, the foregoing is just one way in which trenches and fillers can be defined. As will be described in detail later, the width of the trench is one factor used to determine the channel length of the transistor device and the size of the source / drain diffusions.

Referring now to FIG. 2, a cross-sectional view of a portion of a wafer 202 is illustrated in FIG. 2, in which two exemplary trenches 204, 206 are etched to form pillars 208, 210, and 212.

Returning to FIG. 1, the next step 106 is to conformally deposit the dopant source layer. This dopant source layer is conformally deposited to cover the sidewalls of the filler and the bottoms of the trench. The dopant source layer will be used to provide the dopant for forming the buried bitline of the memory device. Therefore, the dopant source layer can be made of any suitable material containing the desired dopant. For example, arsenic doped glass (ASG), boron phosphorous doped glass (BPSG), and doped polysilicon may all be used as the dopant source layer.

The next step 108 is to conformally deposit the photoresist, which will then be used to pattern the dopant source layer beneath it. Preferably, the resist is a positive resist, in which the exposed portion of the resist is dissolved in the developer. Preferred methods of conformally depositing resists are using chemical vapor deposition (CVD) and suitable resists. By consistently depositing the resist, the resist is attached to the sidewalls and the horizontal surface of the trench. Thus, the resist covers the previously deposited dopant source layer.

One example of a suitable resist is a polysilane resist deposited from a plasma formed from methylsilane. This resist has some unique properties. First, this resist is available in both positive and negative resists when developed. Second, the resist can be conformally deposited using methylsilane in a chemical vapor deposition (CVD) process. Third, it can be activated by both types of exposure, ie by oxygen ion implantation or by irradiating UV light in an oxygen atmosphere. During one of the exposures described above, silicon-silicon bonds are broken and oxygen reacts with activated silicon atoms. As a result of this reaction, silicon dioxide is formed in the exposed areas, while polysilane remains in the unexposed areas. The development process utilizes chemistry in the form of solvents, vapors or plasma to selectively remove silicon (making a negative image) or silicon dioxide (making a positive image). Low pressure plasma and low temperature are used to reinforce the formation of inter-silicon bonds during deposition. Silicon-carbon bonds are generally not broken by exposure, but reduce resist reactivity. The deposition and development process of the resist film is commercialized by Applied Materials, Inc. of Santa Clara, California. An overview of this process can be found in, for example, R. L. Kostelak, T. W. Weidman, S. Vaidya. J. Vac. By O. Joubert, S. C. Palmateer, M. Hibbs. Sci. Tech. R, vol 13, 1995, p2994-2999, and Appl. By T. W. Weidman, A. M. Joshi. Phys. Lett. vol 62, 1993, available at p372-374.

In a preferred embodiment of the invention, polysilane resists are used in a positive form. In particular, after the resist is implanted with oxygen ions, the resist is developed with a hydrofluoric acid developer to remove only the portion implanted with oxygen in the resist.

Referring now to FIG. 3, an exemplary wafer portion 202 is illustrated, which is covered by a dopant source layer 302 and a uniform resist layer 304. According to a preferred embodiment, both the dopant source layer 302 and the uniform resist layer 304 cover the horizontal and vertical surfaces of this wafer portion.

The next step 110 of method 100 involves exposing the wafer at an angle that is not perpendicular to the surface of the wafer such that the top half of the uniform resist layer in the trench is exposed while the bottom half of the uniform resist layer is not exposed. will be. This exposure makes the resist soluble in the developer. Development can be done in several ways, depending on the resist combination in use. For example, in the case of using a preferable silane resist, exposure is preferably achieved by implanting oxygen ions at a predetermined angle. If it is a preferred resist, this exposure will allow the upper half of the resist in the trench to be soluble in the particular developer while the lower half will remain undissolved for this developer. Oxygen ion implantation is preferably performed using an ion implantation device that generates charged oxygen ions and accelerates the charged ions toward the surface of the wafer using an electric field. As a result, oxygen is injected into the resist and the resist becomes soluble in the hydrofluoric acid developer. Typically, this step requires at least two exposures, in which each side of the wafer will be processed one by one so that oxygen is injected into the resist on all sides of the filler.

In addition, in the case of silane and other resists, the exposure is made by irradiating light of a suitable wavelength at a predetermined angle, which is generally not preferable because of unnecessary diffraction effects.

Referring now to FIG. 4, an exemplary wafer portion 202 is illustrated, demonstrating the effect of angled exposure. In particular, by exposing the wafer at two non-vertical angles, the upper half of the resist (upper the line 404) on the sidewalls of the fillers 208, 210, 212 is exposed, while the lower half of the resist (under the line 404) Part) is covered by the side wall so that it is not exposed.

The depth exposed at the filler depends on two factors. That is, it depends on the exposure angle and the width of the trench opening. In particular, the exposure depth D is as shown in Equation 1 below.

Here, W is the width of the trench opening covered with resist, and θ is the off-axis angle, i.e., the tilt angle upon exposure. Since the depth of exposure depends entirely on these two factors, the depth can be strictly controlled. As shown, this will result in much less nonuniformity of the channel than other methods of making filler DRAM. In addition, since the same depressions are all formed by appropriately selecting the angles, the change in the trench width W generated in the manufacturing process can be corrected.

Returning to FIG. 1 again, the next step 112 is to develop and remove the exposed resist. This can be done using any suitable etching process that is compatible with the resist currently in use. The next step 114 is to remove the dopant source material exposed by resist development, which can be done using a compatible process. In a preferred embodiment using a silane resist and an ASG dopant source layer, steps 112 and 114 can be performed using a single hydrofluoric acid dissolution bath (HF bath). The HF solution will develop and remove the exposed resist while leaving the unexposed portions intact. The HF dissolution bath will also remove the dopant source layer underneath the portion from which the resist has been removed. 5, an exemplary wafer portion 202 is shown in which the exposed portion of resist layer 304 is removed while the unexposed portion remains. Likewise, the portion of the dopant source layer 302 that was underneath the removed resist portion was also removed, while the dopant source layer 302 underneath the portion where the resist layer 304 remained. Note that this process associated with the removal of the dopant source layer may result in somewhat undercutting of the dopant source layer at the top edges of the remaining resist. Such undercutting is acceptable if taken into account when determining the exposure angle up to its effect on the channel length.

Referring again to FIG. 1, the next step 116 in the method of the preferred embodiment is to anneal the wafer so that the dopant diffuses from the dopant source layer to the adjacent wafer source. As the dopant diffuses into the wafer, the source / drain and bit lines of the transfer transistor are formed in accordance with the present invention. The parameter of this annealing depends on what dopant profile the bitline wants to have and how much dopant source layer the dopant amount needs. As the dopant diffuses into the wafer, the remaining resist and dopant source layer can be stripped off using any suitable process. For example, the residual resist and the dopant source layer can be stripped off by performing a blanket exposure after the HF dissolution bath.

Referring now to FIG. 6, the dopant is annealed from the dopant source layer to the wafer to form diffusions 602 and 604 in the wafer, and the portion of the wafer 202 after the remaining dopant source layer and resist has been removed. Is illustrated. These diffusions correspond to the source / drain diffusions of the transmission device and also to the buried plates connecting the memory cells. In particular, diffusion 602 corresponds to the source / drain diffusions for two adjacent transmission devices, and also corresponds to a plate connecting these diffusions to the same diffusions on different memory cells. Similarly, diffuser 604 corresponds to the source / drain diffuser and plate for two other adjacent transmission devices.

Once the source / drain / plate diffusions are formed, the remaining portions of the device can be completed using standard filler DRAM processing. This standard filler DRAM processing involves forming a gate / wordline and connecting the various buried plates together. Referring to FIG. 7, a cross section of the completed device is shown on wafer portion 202. The completed device includes a gate electrode 702 corresponding to the word line for the memory device, and a diffusion 704 formed on the top of the pillar, which is a complementary source / drain diffusion for the transfer device. As can be seen in this figure, the channel length for the transmission device is the distance between the source / drain / plate diffusers 602 and 604 and the corresponding source / drain diffuser 704. Therefore, according to the preferred method of forming the source / drain / plate diffuser in which the source / drain / plate diffuser is more precisely controlled and arranged, the channel length of the transistor can be more precisely controlled. This results in a significant performance improvement over the prior art devices.

FIG. 7 illustrates a filler DRAM formed in accordance with Embodiment 1 in which the process of defining the source / drain also defines a buried plate, while Example 2 defines a buried bitline using a similar process. Referring now to FIGS. 8 and 9, Embodiment 2 of forming a buried bitline in accordance with a preferred method is illustrated. The initial steps of Example 2 are substantially similar to those of Example 1. In particular, trenches are formed, and after the source layer is consistently deposited, the resist is also consistently deposited. The resist is then exposed at a non-vertical angle so that the upper half of the trench is exposed while the lower half is not. Thereafter, the exposed resist and the dopant source layer underneath the resist are removed. The wafer is then annealed to allow the dopant to diffuse into the substrate from the remaining dopant source layer. Residual resist and dopant source layers may then be removed. This leaves a wafer similar to that illustrated in FIG. 6 referenced in Example 1. FIG.

However, in Example 2, the diffusion used to form the source / drain / plate will be used to form the source / drain bitline. To do this, the diffusion must be divided into two parts, so that two separate bit lines can be formed. This can be done by further etching the bottom of the trench using directional etching. Referring now to FIG. 8, a portion of a wafer 800 is illustrated where the bottom of the trench is further etched to separate the diffusion into four diffusions 801, 802, 803, and 804. These diffusions correspond to bit lines that connect various transmission devices as well as source / drain diffusions for the transmission device.

Once the source / drain / bitline diffusions are formed, the rest of the device can be completed using standard filler DRAM processing. This processing includes forming a gate / wordline. In this embodiment, the gate / wordline is formed to be substantially perpendicular to the trench already formed. This typically requires etching another trench in a direction perpendicular to the previously formed trench and forming gate / wordlines on the sides of the etched trench. 9, a portion of a wafer 800 is shown having a gate / wordline 902 formed to cross the wafer. Similar word lines will be formed in other trenches of different cross sections. The completed device includes a diffuser 904 formed at the top of the pillar, which corresponds to a complementary source / drain diffuser for the transmission device. Here again the channel length for the transmission device is the distance between the source / drain / bitline spreaders 801, 802, 803 and 804 and the corresponding source / drain diffuser 904. Therefore, according to the preferred method of forming the source / drain / bitline diffuser in which the source / drain / bitline diffuser is more precisely controlled and arranged, the channel length of the transistor can be more precisely controlled. This results in a significant performance improvement over the prior art devices. Although not shown in this figure, capacitors are formed and wiring is also formed to serve as a plate for connecting the devices together.

A notable variation in the preferred embodiment is the use of no separate dopant source layer. Instead, the silane resist is doped with a suitable dopant such that the silane resist itself acts as a dopant source layer. This variant is desirable because of its relative simplicity, although the amount of dopant that can diffuse from the resist to the substrate is limited.

Accordingly, a preferred embodiment of the present invention provides a method of forming a source / drain diffuser having a more uniform channel length in a pillar transistor. The present invention also provides a buried conductor to be used as a buried plate in some memory structures and as a buried bitline in another memory structure.

On the other hand, the preferred method of the present invention provides a method of forming a self-aligned spacer on a horizontal surface while removing the spacer from the vertical surface. According to a preferred method, a resist is used which is insoluble in the developer by implanting ions. By conformally depositing resist on a substrate having vertical and horizontal surfaces, implanting the resist and then developing the resist, the resist on the vertical surface is removed while the resist on the horizontal surface remains. Thus, self-aligned spacers are formed on the horizontal surface while spacer materials on the vertical surface are removed. Such horizontal surface spacers can be used in subsequent manufacturing processes. A general method of forming horizontal surface spacers will first be described, followed by a buried conductor line that is formed in a preferred manner.

Referring now to FIG. 10, a method 1100 of forming a horizontal surface spacer according to a preferred embodiment is illustrated. This method can be used in a variety of applications that wish to treat the vertical and horizontal surfaces of the device differently.

The first step 1102 is to provide a suitable substrate having a horizontal surface and a vertical surface. Such substrates may be silicon or other semiconductor wafers placed at various stages of manufacture. For example, the substrate may be a silicon wafer to be formed such that a number of devices are connected using a buried conductive layer. Thus, the substrate includes both a vertical surface to be left uncovered and a horizontal surface on which horizontal surface spacers are to be formed. The substrate may also include an etch stop layer, for example silicon dioxide, for use as a develop stop when the resist is developed.

Referring now to FIG. 11, a portion of wafer 1202 is illustrated, in which two exemplary trenches 1204, 1206 are etched to form pillars 1208, 1210, 1212. These features are exemplary types of features in which the horizontal surface spacer can be selectively covered according to a preferred embodiment. Trench and filler of the illustrated structure may be formed using any suitable method, such as conventional photoresist techniques.

Returning to FIG. 10, the next step 1104 is to conformally deposit a suitable implant-sensitive resist. Preferably, the resist is formulated such that the implanted areas become insoluble in the developer while the non-planted areas remain soluble in the developer. In addition, the resist is preferably made of a thin film to minimize the amount of energy required to pattern the resist.

One example of a suitable resist is a polysilane resist deposited from a plasma formed from methylsilane. As mentioned above, this resist has several unique properties. First, this resist is available in both positive and negative resists when developed. Second, the resist can be conformally deposited using methylsilane in a chemical vapor deposition (CVD) process. Third, it can be activated by both types of exposure, ie by oxygen ion implantation or by irradiating UV light in an oxygen atmosphere. During one of the exposures described above, silicon-silicon bonds are broken and oxygen reacts with activated silicon atoms. As a result of this reaction, silicon dioxide is formed in the exposed areas, while polysilane remains in the unexposed areas. The development process utilizes chemistry in the form of solvents, vapors or plasma to selectively remove silicon (making a negative image) or silicon dioxide (making a positive image). Low pressure plasma and low temperature are used to reinforce the formation of inter-silicon bonds during deposition. Silicon-carbon bonds are generally not broken by exposure, but reduce resist reactivity. The deposition and development process of the resist film is commercialized by Applied Materials, Inc. of Santa Clara, California. An overview of this process can be found in, for example, R. L. Kostelak, T. W. Weidman, S. Vaidya. J. Vac. By O. Joubert, S. C. Palmateer, M. Hibbs. Sci. Tech. R, vol 13, 1995, p2994-2999, and Appl. By T. W. Weidman, A. M. Joshi. Phys. Lett. vol 62, 1993, available at p372-374.

In a preferred embodiment of the present invention, polysilane resists are used in a negative form. In particular, the resist is implanted with oxygen ions and then developed with a chlorine or bromine developer to remove only the portion of the resist that is not implanted with oxygen ions. Moreover, in one embodiment, the resist is doped with a dopant and used to diffuse the dopant into adjacent portions of the substrate. Such features will be described in more detail later with reference to buried conductor applications.

Another material that can be used as an ion implantation reactive resist is polysilicon. Polysilicon may be conformally deposited using any conventional technique. Polysilicon is insoluble in potassium hydroxide / isopropyl alcohol developer when boron is properly ion implanted, while the non-ion implantation region remains soluble for this developer.

Referring now to FIG. 12, an exemplary wafer portion 1202 is illustrated after a matching resist layer 1302 is deposited to cover the wafer portion. According to a preferred embodiment, the matching resist layer 1302 covers both the horizontal and vertical surfaces of the wafer portion.

The next step 1106 is to inject ions of the kind on the horizontal surface of the resist layer at a vertical angle to prevent the resist layer from melting in the developer. The type of implanted ions therefore depends on the resist in use. The energy of the ion implantation is chosen so that it is completely implanted into the resist on the horizontal surface but not too far into the vertical surface. Ion implantation is preferably performed at an angle perpendicular to the top surface of the wafer so that ion implantation to the vertical surface is minimized.

For example, when using a preferable silane resist, oxygen ion implantation is preferably performed perpendicular to the horizontal surface on the substrate. With a preferred resist, this exposure prevents the horizontal surface of the resist from melting in the developer. Oxygen ion implantation is preferably performed using an ion implantation device that generates charged oxygen ions and accelerates the charged ions toward the surface of the wafer using an electric field. As a result, oxygen is injected into the resist. The ion implantation process described above is different from the conventional process in which the resist is exposed to actinic radiation (eg, light) in an oxygen atmosphere.

When using polysilicon resists, boron is implanted to render polysilicon on the horizontal surface insoluble in the developer. Such ion implantation is reliably performed using an ion implantation device that accelerates boron toward the surface of the wafer to inject ions into the polysilicon resist. Typically, in order to prevent the polysilicon resist from melting in the developer, it is preferable to perform BF ₂ ion implantation of 1 × 10 ^{15 to} 1 × 10 ¹⁸ [ions / cm ³ ] at 10 KeV.

Referring now to FIG. 13, a portion of wafer 1202 is illustrated to show implantation at a perpendicular angle to resist 1302. Since ion implantation is performed perpendicular to the horizontal surface, the ion implantation is completely implanted from the top to the bottom of this horizontal surface but does not affect the vertical surface of the resist. On the other hand, in selecting the ion implantation energy, it is easily made by selecting the energy such that only the thickness of the resist is penetrated, not the energy that the ion is implanted to the vertical portion of the resist. In this way, the horizontal surface becomes insoluble in the developer while the vertical surface is virtually unaffected. In addition, the dose is appropriately selected to fully react with the resist composition in use. Thus, the ion implantation energy and ion implantation amount are appropriately selected to fully react with the horizontal surface while minimizing ion collision to the vertical surface.

Returning to FIG. 10, the next step 112 is to develop the resist. This can be done using any suitable etchant that is compatible with the resist currently in use. For example, if a silane resist is used, the plasma chlorine etch will remove the non-ion implanted portion of the resist without affecting the oxygen ion implanted portion. Other resist compositions will use other development techniques.

Referring to FIG. 14, a portion of the wafer 1202 is illustrated after the ion implantation portion of the resist 1302 remains as it is while the non-ion implantation portion is removed. The remaining portion of the resist now includes a horizontal surface spacer 1502, which can be used to facilitate the differential treatment of the vertical surface as compared to the horizontal surface. Note that this process typically leaves a small amount of resist projecting over the edge of the trench. The amount of protrusion can be controlled by selecting the thickness of the resist.

Thus, the preferred embodiment can be used to form horizontal surface spacers that can be used in various process conditions. For example, a preferred method can be used to form buried leads. Buried wires are used to interconnect devices such as transistors without the use of separate conductive wires as usual. A buried lead is one example that is used in a filler DRAM. In particular, buried conductors can be used to form bit lines that connect several memory cells of a DRAM. Although the preferred embodiment is described with reference to the bit lines of DRAM devices, other types of memory devices, such as DRAM variants (extended data output DRAM, burst extended data output DRAM, synchronous DRAM, etc.), and static random access memory (SRAM) Access Memory) and its variants (asynchronous SRAM, synchronous SRAM, pipelined burst SRAM, etc.) are also applicable.

In order to form such a buried bitline, the preferred method is used in several variations. First, a diffusion barrier layer such as silicon dioxide or silicon nitride is formed on top of the filler. This is done by forming the diffusion barrier layer before the filler is etched. When the trenches defining the pillars are etched, the diffusion barrier layer remains on top of the formed pillars. Secondly, the conformally deposited resist is doped to include a suitable type of dopant to form a buried bitline. For example, preferred silane resists may be doped with arsenic during deposition. After a suitably doped ion implantation reactive resist is deposited consistently, the resist is patterned using the ion implantation technique described above and then developed. This leaves the doped resist on the horizontal surface while removing it from the vertical surface. The wafer is then properly annealed to allow the dopant to diffuse from the doped resist into the vertical surface of the substrate. At the bottom of the filler, conductive bit lines are formed in the substrate by dopant diffusion. At the top of the filler, the dopant diffuses into the diffusion barrier layer, which ultimately has no effect on the silicon underneath the diffusion barrier layer. In a variation of the above described application, a separate dopant source layer is formed before the resist is deposited, and patterned with the resist when the resist layer is patterned. Such a modification would be desirable if more dopant implantation is required.

Once the diffusion is formed, the remaining resist is removed. The diffusion can be divided into individual diffusions for use as individual conductors (eg, individual bit lines) on each side by further etching the bottom of the trench using a suitable process such as reactive utilization etching.

Referring now to FIG. 15, a suitable diffusion barrier layer 1601 is deposited, and a portion of the wafer 1602 patterned and etched to form two exemplary trenches 1604, 1606 and pillars 1608, 1610, 1612. This is illustrated. Referring now to FIG. 16, a portion of a wafer 1602 is illustrated after ion implantation reactive resist has been deposited, ion implanted, developed after appropriately doped, and after the dopant has diffused from the residual resist into the wafer portion 1602. have. Thereafter, the trench is further etched to divide this diffusion into separate leads. On the other hand, the dopant diffuses from the patterned resist to the bottom of trenches 1604 and 1606 to form conductive bitlines 1702 and 1704. Likewise, at the top of the filler, the dopant diffuses into the diffusion barrier layer where it is blocked from diffusing into the silicon substrate.

After the dopant is diffused into the substrate, the remaining resist can be removed using reactive ion etching, BHF, HF vapor, or other suitable process.

As another example, the preferred method can be used to easily doping vertical surfaces by exposing a wafer with horizontal surface spacers to a gaseous impurity source. This process could be used to form high performance logic MOSFETs. This involves making the silicon substrate have a suitable isolation region and doped N ⁺ and P ⁺ diffusions for the source and drain contacts. An etch barrier film, for example made of any suitable material, such as silicon nitride, is deposited and the wafer is patterned for trench formation. Next, horizontal surface spacers are formed using the preferred method. The exposed sidewalls are doped with a suitable dopant while spacer material is formed on the horizontal surface and removed from the vertical surface. This use of a suitable gaseous dopant (e. G., For the N ⁺ region for the AsH ₃ arsenic vapor, a P ⁺ region using diborane (diborane)), or a dopant source layer (e.g., ASG or BSG doped Oxidized oxide) and then annealed. Horizontal surface spacers protect the horizontal surface during this process. Sidewall doping connects the doped surface region to the transfer gate, causing the diffusion to overlap the gate channel region at the bottom of the trench.

As the sidewalls are doped, the residual resist is removed using a buffered HF, HF vapor, or fluorine plasma process and the wafer is cleaned. Next, a gate insulator is formed in the trench. This is preferably done by growing silicon dioxide in the trench. Due to the crystal orientation of the sidewall dopant and silicon, silicon dioxide will form thicker on the vertical sidewalls. The trench is then filled with polysilicon, polished and planarized. Thereafter, the contacts and wiring can be continued using any suitable technique. Referring now to FIG. 17, illustrated is a portion of a wafer 1802 in which a logic MOSFET is formed using a preferred method of selectively forming a diffusion 1808 on the sidewalls of a trench. This logic device includes a polysilicon gate 1808 and a gate insulator 1810. The diffusions 1804 are combined with the diffusions 1806 to form the source and drain of the device. On the other hand, by using a preferred method of selectively doping the sidewalls, it is possible for the diffusion to overlap the gate channel region of the trench bottom.

Conventional processes have used sidewall spacers to selectively dope sidewalls. Unfortunately, reactive ion etching used to directional etch sidewall spacers typically damages the bottom of the trench. In contrast, by using the preferred method of this embodiment to form horizontal surface spacers that facilitate different doping of the sidewalls, the necessary diffusion regions can be formed without damage by reactive ion etching.

Thus, the preferred embodiment described above is used to form a self-aligned spacer on a horizontal surface while removing spacer material from the vertical surface. Such horizontal surface spacers can be used in subsequent fabrication processes, including the formation of buried lead and sidewall diffusion regions.

Although the invention has been particularly shown and described with reference to exemplary embodiments for forming source / drain / embedded conductor diffusions in pillar-type DRAM cells, those skilled in the art can also use this process to form sources / drains in other devices. It will be recognized. In addition, although the invention has been specifically shown and described with reference to exemplary embodiments for forming bitline diffusions in pillar-type DRAM cells, those skilled in the art can also use this process to form source / drain and other diffusion structures. Will recognize. For example, those skilled in the art will appreciate that the present invention may be applied to other isolation techniques (eg, LOCOS, recessed oxide (ROX), STI, etc.), well and substrate techniques, dopant types, energy, and types. It will also be appreciated that the spirit of the present invention can be applied to other techniques based on silicon (eg, BiCMOS, bipolar, silicon on insulator (SOI), silicon germanium (SiGe)).

Therefore, according to the present invention, the uniformity of the channel length of the filler transistor is improved.

In addition, according to the present invention, there is provided a simple method of forming a self-aligned horizontal surface spacer on a horizontal surface while removing all of the spacer material on the vertical surface.

Claims (43)

A method of forming a feature on a semiconductor substrate, Forming a trench having sidewalls and bottoms in said substrate, Ⓑ forming a dopant source layer on the substrate covering the trench sidewalls and the trench bottom; Forming a resist layer on the dopant source layer to cover the dopant source layer on the trench sidewalls and the trench bottom; Exposing the resist layer, wherein the resist layer is exposed at a predetermined angle such that an upper end portion of the resist layer on the trench sidewalls is exposed while a lower end portion of the resist layer on the trench sidewalls is not exposed; Ⓔ removing the exposed portion of the resist layer and the dopant source layer below the exposed portion of the resist layer; Ⓕ diffusing a dopant from the unexposed portion of the dopant source layer to the substrate A method of forming a feature on a semiconductor substrate. delete delete delete delete delete delete delete delete delete delete delete delete delete A method of forming a buried bit line for connecting a memory cell on a semiconductor substrate, the method comprising: Forming a trench having sidewalls and bottoms in said substrate, (B) conformally depositing a dopant source layer on the substrate covering the trench sidewalls and the trench bottom; C) conformally forming a resist layer on the dopant source layer to cover the dopant source layer on the trench sidewalls and the trench bottom; Ⓓ expose the resist layer by implanting ions into the resist layer, wherein an upper end portion of the resist layer on the trench sidewall is exposed while a lower end portion of the resist layer on the trench sidewall is covered by the trench sidewall so as not to be exposed. Exposing the resist layer with Ⓔ removing the exposed portion of the resist layer and the dopant source layer below the exposed portion of the resist layer; Ⓕ diffusing a dopant from an unexposed portion of the dopant source layer to the substrate to form a diffusion region; Ⓖ further etching the bottom portion of the trench such that the diffusion is divided into two source / drain / bitline diffusions. How to form a buried bitline. delete delete delete delete delete In the method of forming a buried plate in a memory cell on a semiconductor substrate, Forming a trench having sidewalls and bottoms in said substrate, (B) conformally depositing a dopant source layer on the substrate covering the trench sidewalls and the trench bottom; C) conformally forming a resist layer on the dopant source layer to cover the dopant source layer on the trench sidewalls and the trench bottom; Ⓓ expose the resist layer by implanting ions into the resist layer, wherein an upper end portion of the resist layer on the trench sidewall is exposed while a lower end portion of the resist layer on the trench sidewall is blocked by the trench sidewall so as not to be exposed. Exposing the resist layer at an angle; Ⓔ removing the exposed portion of the resist layer and the dopant source layer below the exposed portion of the resist layer; Ⓕ diffusing a dopant from the unexposed portion of the dopant source layer to the substrate to form a buried plate diffusion region A method of forming a buried plate in a memory cell. delete delete delete A method of forming a horizontal surface spacer on a semiconductor substrate having a horizontal surface and a vertical surface, the method comprising: Conformally forming an ion implantation reactive resist layer on the horizontal surface and the vertical surface, (B) implanting ions into the ion implantation reactive resist layer, substantially ion implanting into the ion implantation reactive resist layer on the horizontal surface, and substantially ion implantation into the ion implantation reactive resist layer on the vertical surface, Implanting the ion implantation reactive resist layer substantially perpendicular to the horizontal surface; C) developing the ion implantation reactive resist layer such that the substantially non-implanted resist layer is removed from the vertical surface and the substantially implanted resist layer remains on the horizontal surface. Method for forming horizontal surface spacers. delete delete delete delete delete delete delete The method of claim 25, And doping the ion implantation reactive resist layer with a predetermined dopant prior to ion implantation into the ion implantation reactive resist layer. delete The method of claim 33, wherein After removing the ion implantation reactive resist layer from the vertical surface of the substrate, diffusing the predetermined dopant from the ion implantation reactive resist layer into the horizontal surface of the substrate. 36. The method of claim 35 wherein And a buried conductor is formed by the step of diffusing the predetermined dopant.
delete The method of claim 25, Diffusing a dopant into the exposed vertical surface to form a source / drain diffusion region. The method of claim 25, Diffusing a dopant into the exposed vertical surface to form a diffuser in a logic device. delete delete delete A method of forming a horizontal surface spacer on a semiconductor substrate having a horizontal surface and a vertical surface, the method comprising: Chemically vapor-depositing polysilane from plasma formed of methylsilane on the horizontal and vertical surfaces to conformally form an ion implantation reactive resist layer; B) oxygen is implanted into the ion implantation reactive resist layer, but substantially ion implanted into the ion implantation reactive resist layer on the horizontal surface, and substantially ion implantation into the ion implantation reactive resist layer on the vertical surface Implanting phenomena into the ion implantation reactive resist layer substantially perpendicular to the horizontal surface; Developing the ion implantation reactive resist layer with chlorine plasma such that the substantially non-implanted resist layer is removed from the vertical surface and the substantially implanted resist layer remains on the horizontal surface. doing Method for forming horizontal surface spacers.