KR100359762B1 - Method for manufacturing capacitor in semiconductor device - Google Patents
Method for manufacturing capacitor in semiconductor device Download PDFInfo
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- KR100359762B1 KR100359762B1 KR1019950046862A KR19950046862A KR100359762B1 KR 100359762 B1 KR100359762 B1 KR 100359762B1 KR 1019950046862 A KR1019950046862 A KR 1019950046862A KR 19950046862 A KR19950046862 A KR 19950046862A KR 100359762 B1 KR100359762 B1 KR 100359762B1
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- conductivity type
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- metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로 특히, 이온주입을 이용하여 좁은 면적에서도 대용량의 캐패시터를 구현하는데 적당하도록 한 반도체 소자의 캐패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device suitable for implementing a large capacity capacitor even in a small area using ion implantation.
일반적으로 캐패시터의 제조방법은 제 1 도 및 제 2 도에 도시한 바와 같이, 제 1 메탈층(1)과 제 2 메탈층(2) 사이에 산화막(3)(SiO2)을 형성하여 캐패시터를제작하는 방법과, 상기 메탈층들 중 한쪽면의 메탈층 대신에 n형 불순물 이온을 주입시켜 n+농도를 높이므로서 캐패시터를 제작하는 방법이 있다.In general, as shown in FIGS. 1 and 2, a method of manufacturing a capacitor includes forming an oxide film 3 (SiO 2 ) between a first metal layer 1 and a second metal layer 2 to form a capacitor. There is a manufacturing method and a method of manufacturing a capacitor by increasing the n + concentration by implanting n-type impurity ions in place of the metal layer on one side of the metal layer.
이때 상기의 캐패시터 제작방법들은 필요로 하는 캐패시턴스(Capacitance)를 얻기 위해서 산화막의 폭(Width)과 평판(메탈층)의 면적을 조절하게 된다.At this time, the above-mentioned capacitor fabrication methods adjust the width of the oxide film and the area of the plate (metal layer) in order to obtain the required capacitance.
이를 수식으로 표현하면 다음과 같다.If this is expressed as an expression, it is as follows.
여기서 Cox는 단위면적당 캐패시턴스, d : 평판 사이의 거리, εox는 평판 사이의 산화막의 유전율이다.Where Cox is the capacitance per unit area, d is the distance between the plates, and εox is the permittivity of the oxide film between the plates.
그러나 상기와 같은 종래 반도체 소자의 캐패시터 제조방법은 대용량의 캐패시턴스를 얻기 위해서는 유전체막으로 사용되는 산화막의 폭을 줄이거나 캐패시터의 면적을 증가시켜야 한다.However, in the conventional method of manufacturing a capacitor of a semiconductor device as described above, in order to obtain a large capacitance, the width of the oxide film used as the dielectric film or the area of the capacitor must be increased.
하지만 산하막의 폭을 감소시키는데는 한계가 있으며 또한 캐패시터의 면적을 증가시키면, 칩 사이즈가 커져서 집적도가 저하되는 문제점이 있었다.However, there is a limit in reducing the width of the sub-layer, and when the area of the capacitor is increased, there is a problem that the degree of integration decreases due to the increase in the chip size.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로서, 이온주입에 의한 복수개의 n+평판을 형성하여 좁은 면적하에서도 대용량의 캐패시터를 제작하는데 그 목적이 있다.The present invention has been made to solve the above problems, the object is to form a large capacity capacitor even in a small area by forming a plurality of n + plate by ion implantation.
상기의 목적을 달성하기 위한 본 발명의 반도체 소자의 캐패시터 제조방법은 제 1 도전형 반도체 기판상에 제 2 도전형 불순물 이온을 선택적으로 주입하여 복수개의 제 2 도전형 불순물 영역을 형성하는 제 1 단계, 상기 복수개의 제 2 도전형 불순물 영역 사이에 각각 절연막을 형성하는 제 2 단계, 상기 복수개의 제 2 도전형 불순물 영역에 전기적으로 연결되도록 선택적으로 제 1, 제 2 메탈층을 형성하는 제 3 단계를 포함하여 이루어짐을 특징으로 한다.A capacitor manufacturing method of a semiconductor device of the present invention for achieving the above object is a first step of forming a plurality of second conductivity type impurity regions by selectively implanting the second conductivity type impurity ions on the first conductivity type semiconductor substrate And a second step of forming an insulating film between the plurality of second conductivity type impurity regions, and a third step of selectively forming first and second metal layers to be electrically connected to the plurality of second conductivity type impurity regions. Characterized in that comprises a.
이하, 첨부도면을 참조하여 본 발명의 반도체 소자의 캐패시터 제조방법을 설명하면 다음과 같다.Hereinafter, a capacitor manufacturing method of a semiconductor device of the present invention will be described with reference to the accompanying drawings.
제 3 도 (a)∼(d)는 본 발명의 반도체 소자의 캐패시터 제조방법을 나타낸 공정단면도이다.3 (a) to 3 (d) are process cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device of the present invention.
먼저, 본 발명의 반도체 소자의 캐패시터 제조방법은 제 3 도 (a)에 도시한 바와 같이, P형 반도체 기판(11)상에 제 1 감광막(12)을 도포한 후, 제 1 감광막(12) 패턴을 통해 n+평판 영역을 정의한다.First, in the method of manufacturing a capacitor of the semiconductor device of the present invention, as shown in FIG. 3 (a), after the first photosensitive film 12 is coated on the P-type semiconductor substrate 11, the first photosensitive film 12 is applied. The pattern defines n + plate area.
그리고, 상기 제 1 감광막(12) 패턴을 마스크로 이용하여 n형 불순물 이온(예를들어 B+, P+, As+)을 주입하여 다수개의 n+평판(13)을 형성한다.The n-type impurity ions (eg, B + , P + , As + ) are implanted using the first photoresist layer 12 as a mask to form a plurality of n + plates 13.
이때, n+평판 영역의 수 및, 폭(Width), 그리고 n+평판 사이의 산화막 폭(Width)은 필요로 하는 캐패시턴스를 고려하여 임의로 조절할 수 있다.At this time, the number of n + plate regions, the width (Width), and the oxide film width (Width) between the n + plate can be arbitrarily adjusted in consideration of the required capacitance.
이어 제 3 도 (b)에 도시한 바와 같이, 상기 제 1 감광막(12)을 제거한 후 유전체막으로 사용될 산화막 영역을 정의하기 위해 상기 n+평판(13)이 형성된 반도체 기판(11)상에 제 2 감광막(14)을 도포한다.Subsequently, as illustrated in FIG. 3B, the first photosensitive film 12 is removed and then the semiconductor substrate 11 on which the n + plate 13 is formed to define an oxide region to be used as a dielectric film. 2 Photosensitive film 14 is applied.
상기 제 2 감광막(14)을 노광 및 현상공정을 통해 패터닝 하여 산화막 영역을 정의한다.The second photoresist layer 14 is patterned through an exposure and development process to define an oxide layer region.
이어서, 상기 제 2 감광막(14)을 마스크로 이용하여 산소(O2) 이온을 주입한다.Subsequently, oxygen (O 2 ) ions are implanted using the second photosensitive film 14 as a mask.
따라서, 상기 반도체 기판(11)의 실리콘(S1)과 주입된 산소(O2)가 결합하여 산화막(SiO2) (15)이 형성된다.Therefore, silicon (S 1 ) of the semiconductor substrate 11 and the injected oxygen (O 2 ) are bonded to form an oxide film (SiO 2 ) 15.
이어서 상기 제 2 감광막(14) 패턴을 제거하면 캐패시터 제작을 완료하게 되는데 이에 상기 n+평판(13)에 바이어스를 인가하기 위해 제 3 도 (c)에 도시한 바와 같이, 전면에 제 1 절연막(16)을 증착한 후 상기 제 1 절연막(16)상에 제 3 감광막(도시하지 않음)을 도포하여 포지티브(Positive) 바이어스 인가를 위해 선택적으로 n+평판(13)에 콘택홀을 형성한다.Subsequently, when the second photoresist layer 14 pattern is removed, the capacitor fabrication is completed. Accordingly, in order to apply a bias to the n + flat plate 13, as shown in FIG. 16), a third photoresist layer (not shown) is applied on the first insulating layer 16 to form a contact hole in n + plate 13 selectively for positive bias application.
이어, 상기 콘택홀을 포함한 전면에 제 1 메탈층(17)을 형성하고, 상기 제 1 메탈층(17) 전면에 제 2 절연막(18)을 증착한다.Subsequently, the first metal layer 17 is formed on the entire surface including the contact hole, and the second insulating layer 18 is deposited on the entire surface of the first metal layer 17.
그리고 상기 제 2 절연막(18)상에 제 4 감광막(19)을 도포하여 노광 및 현상공정으로 네가티브(Negative) 바이어스 인가를 위해 상기 n+평판(13)에 형성될 영역을 정의한다.The fourth photoresist film 19 is coated on the second insulating film 18 to define a region to be formed in the n + plate 13 for applying a negative bias through an exposure and development process.
이어서, 제 3 도 (d)에 도시한 바와 같이, 상기 제 4 감광막(19)을 마스크로이용한 식각공정을 통해 선택적으로 n+평판(13)에 콘택홀을 형성한 후 상기 콘택홀을 포함한 전면에 제 2 메탈층(20)을 형성하면 바이어스 인가를 위한 메탈층 형성공정이 완료된다.Subsequently, as shown in FIG. 3 (d), a contact hole is selectively formed in n + plate 13 through an etching process using the fourth photoresist film 19 as a mask, and then the front surface including the contact hole. When the second metal layer 20 is formed on the metal layer forming process for applying the bias is completed.
따라서, 제 3 도 (d)에 도시한 바와 같이, 상기 제 1 메탈층(17)에 포지티브 바이어스를, 그리고 제 2 메탈층(20)에 네가티브 바이어스를 인가하면 동일한 사이즈의 캐패시터가 다수개 형성된다.Therefore, as shown in FIG. 3 (d), a plurality of capacitors having the same size are formed by applying a positive bias to the first metal layer 17 and a negative bias to the second metal layer 20. .
즉, ㉯는 ㉮와 ㉰, ㉱는 ㉰와 ㉲, ㉳는 ㉲와 각각 캐패시터를 구성하게 된다.That is, ㉯ is ㉮ and ㉰, ㉱ is ㉰ and ㉲, ㉳ is to form a capacitor, respectively.
결과적으로 평판의 넓이가 A, 평판과 평판과의 거리를 d라고 가정하면 하나의 평판에 대한 캐패시턴스(Capacitance)는 다음과 같은 수식으로 표현된다.As a result, assuming that the width of the plate is A, the distance between the plate and the plate is d, the capacitance of one plate is expressed by the following equation.
따라서 n개의 캐패시터를 병렬로 구성하면 전체 캐패시턴스 Ctox = nCox가 된다.Therefore, when n capacitors are configured in parallel, the total capacitance Ctox = nCox.
이상 상술한 바와 같이, 본 발명의 반도체 소자의 캐패시터 제조방법은 이온주입 공정을 통해 좁은 면적에 다수의 n+평판을 구현할 수 있으므로 대용량의 캐패시터 제작이 용이한 효과가 있다.As described above, the capacitor manufacturing method of the semiconductor device of the present invention can implement a plurality of n + flat plate in a small area through the ion implantation process, it is easy to manufacture a large capacity capacitor.
제 1 도 및 제 2 도는 종래 반도체 소자의 캐패시터 제조방법에 따른 단면도1 and 2 are cross-sectional views according to a method of manufacturing a capacitor of a conventional semiconductor device
제 3도 (a)∼(d)는 본 발명의 반도체 소자의 캐패시터 제조방법을 나타낸 공정단면도3 (a) to 3 (d) are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device of the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
11 : P형 실리콘 기판 12, 14, 19 : 제 1, 제 2, 제 4 감광막11: P-type silicon substrate 12, 14, 19: 1st, 2nd, 4th photosensitive film
13 : n+불순물 영역 15 : 산화막13: n + impurity region 15: oxide film
17 : 제 1 메탈층 20 : 제 2 메탈층17: first metal layer 20: second metal layer
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019950046862A KR100359762B1 (en) | 1995-12-05 | 1995-12-05 | Method for manufacturing capacitor in semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019950046862A KR100359762B1 (en) | 1995-12-05 | 1995-12-05 | Method for manufacturing capacitor in semiconductor device |
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| Publication Number | Publication Date |
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| KR970053927A KR970053927A (en) | 1997-07-31 |
| KR100359762B1 true KR100359762B1 (en) | 2003-03-26 |
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| KR1019950046862A KR100359762B1 (en) | 1995-12-05 | 1995-12-05 | Method for manufacturing capacitor in semiconductor device |
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| KR (1) | KR100359762B1 (en) |
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