KR100357182B1 - Redundancy circuit in semiconductor memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundancy circuit of a semiconductor memory device capable of increasing the relief efficiency, wherein a plurality of rows are arranged as one unit Xmat in the X direction and a plurality of columns are arranged in the Y direction. A semiconductor memory device having a relief function as a unit (Ymat), comprising: a fuse unit including a fuse set having Xmat information for row failing and a fuse set having address bit information Ymat information; An address comparator for outputting a determination signal HITmBi for judging whether a given address is a low fail bit or comparing Ymat information and determining whether an input address is a fail bit; Redundant paths are divided to control normal word line drivers, respectively, and the redundancy paths are used to input and output main amplifiers. It includes a control unit for controlling the position, and both the normal and the redundancy is loaded on the local input and output line through the corresponding bit line, so that only one of the two data output according to the determination signal (HITmBi) has one redundancy word line Ymat It's about doing star relief.

Description

Redundancy circuit in semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a redundancy circuit of a semiconductor memory device capable of increasing the relief efficiency.

In general, in a semiconductor memory device, when a bad cell occurs in any one of a plurality of memory cells existing in a normal memory cell array, the entire memory may not be used.

Improvements in the design and fabrication of semiconductor memory devices result in more cells being placed on a single chip and producing larger integrated circuits. As a result, it is almost impossible for all memory cells to be in good condition in one chip, and in high-density memory, the ability of the defective cell to play a very important role in determining chip yield.

To this end, semiconductor memory devices have been designed and manufactured in such a manner that redundant memory cells are installed in addition to the number of basic memory cells on the same chip and replaced with defective normal memory cells.

As a means of improving the redundancy capability, first, a method of increasing the number of redundancy memory cells and the number of fuse boxes and second, a method of sharing a certain number of redundancy cells and fuse boxes by several memory cell blocks.

Hereinafter, a redundancy circuit of a semiconductor memory device of the related art will be described with reference to the accompanying drawings.

1 is a configuration diagram of a semiconductor memory device of the prior art, and FIG. 2A is a circuit diagram of a fuse unit and a comparison unit of the semiconductor memory device of the prior art.

2B is a circuit diagram of a control unit of the semiconductor memory device of the related art.

If MAT is composed of 8 mats in the X direction and 4 mats in the Y direction, 9 row addresses are required to enable one word line.

In the semiconductor memory device of the related art defined as above, the redundancy circuit in the X direction is largely composed of a fuse part, an address comparison part, and a control part.

In FIG. 1, reference numeral 1 denotes a Y-decoder, and a redundancy word line occurs when a row fail occurs in one normal sub word line 3 to sub word lines connected to one main word line driver block (MWD) 2. Repair using (4).

FIG. 2A shows a circuit configuration of the fuse unit and the address comparison unit 21 configured in the redundancy block of the main word line driver block 2, wherein respective fuses in the fuse unit 21a correspond to the word line fail bits. Has information.

The MAT defined in FIG. 1 requires 10 fuses to save one fail word line.

That is, nine address fuses and one enable fuse are required.

When the X-address is input through the buffer by the active command, the fail bit information of the fuse and the input address are compared.

BX2Ri, BX3Ri, ..., BX8Ri input to the fuse section and the address comparison section 21 are X-address signals.

When the input address coincides with the fail word line information of the fuse, HITmBi (a signal for determining whether the input address is a fail bit) is enabled.

When the HITmBi signal is enabled as described above, the redundancy word line is enabled through the XREi (signal for controlling the redundancy word line driver) path of the control circuit 22 and the XDEi (signal for controlling the normal word line driver) path is performed. By failing the normal word line along, the fail word line is saved.

Such a redundancy circuit of a conventional semiconductor memory device has the following problems.

Redundancy of one fail word line replaces all of the sub word lines connected to the main word line including the fail word line, thereby reducing the rescue efficiency.

That is, when a word line failure occurs in Xmat3-Ymat1, the sub word lines of Xmat3-Ymat0, 2, and 3 that are normally operated are simultaneously replaced, which is disadvantageous in terms of rescue efficiency.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem of the redundancy circuit of the prior art, and an object thereof is to provide a redundancy circuit of a semiconductor memory device capable of increasing the relief efficiency.

1 is a configuration diagram of a conventional semiconductor memory device

2A is a circuit diagram illustrating a fuse unit and a comparison unit of a conventional semiconductor memory device.

2B is a circuit diagram of a control unit of a semiconductor memory device of the related art.

3 is a configuration diagram of a semiconductor memory device according to the present invention.

4A is a circuit diagram illustrating a fuse unit and a comparison unit of a semiconductor memory device according to the present invention.

4B is a circuit diagram illustrating a control unit of a semiconductor memory device according to the present invention.

5 is a detailed configuration diagram of a fuse of a semiconductor memory device according to the present invention.

Explanation of symbols for the main parts of the drawings

41a. Fuse part 41b. Address comparator

42. Control part 43. Fail bit judgment signal output terminal

In order to achieve the above object, a redundancy circuit of a semiconductor memory device according to the present invention includes a plurality of rows as one unit Xmat in the X direction and a plurality of columns as one unit in the Y direction. A semiconductor memory device having a rescue function (Ymat), the semiconductor memory device comprising: a fuse unit including a fuse set having Xmat information for a low fail and a fuse set having address bit information Ymat information; an address input by comparing X-address information An address comparison unit for outputting a determination signal HITmBi for determining whether or not a low address bit is a low fail bit and comparing Ymat information to determine whether an input address is a fail bit; a normal path and a redundancy path by an output signal of the address comparison unit; Each of them controls the normal word line driver, and the redundancy path controls the input / output switch of the main amplifier. The control unit includes a control unit, and both normal / redundancy are loaded on the local I / O line through the corresponding bit line, and only one of the two data is output according to the determination signal HITmBi, thereby having one redundancy word line and relieving for Ymat. Characterized in that.

Hereinafter, a redundancy circuit of a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a configuration diagram of a semiconductor memory device according to the present invention, and FIG. 4A is a circuit configuration diagram of a fuse unit and a comparison unit of the semiconductor memory device according to the present invention.

4B is a circuit diagram of a control unit of the semiconductor memory device according to the present invention, and FIG. 5 is a detailed diagram of a fuse of the semiconductor memory device according to the present invention.

The redundancy block according to the present invention includes a fuse unit 41a having information on a low fail, an address comparison unit 41b for determining whether an input address is a low fail bit, and the address comparison unit ( The normal signal and the redundancy path are distinguished by the output signal of 41b), and the control unit 42 controls the normal word line driver and the input / output switch of the main amplifier by the redundancy path, respectively. It is configured by.

Here, the fuse portion is composed of a fuse set 41a having Xmat information for low fail and a fuse set 41c having address bit information Ymat information.

The address comparison section 41b compares not only the X-address information but also the Ymat information for the row fail.

The control unit 42 of the redundancy block enables the normal and the redundancy word lines at the same time by the X-command, that is, the activation signal, and uses the input / output control signal IOSW after the Y-command, that is, the read / write signal input. Determines whether data input to the main amplifier is normal or redundant.

An output address of the fuse unit and the address comparison unit 41 includes NOR gates for NOR operation on the output signals of the plurality of fuse units and the address comparison unit, and NAND gates for NAND operation on the output signals of the NOR gates. A fail bit decision signal output stage 43 for outputting a decision signal HITmBi for determining whether is a fail bit or not is configured.

The control unit 42 outputs a control signal XDEi for controlling a normal word line driver and an input / output switch control signal IOSW, and the fuse unit 41c outputs a control signal XREi for controlling a redundancy word line driver. ) Is output.

In addition, X-address signals XMS0, XMS1, ..., XMS7 are input to the gates of the NMOS transistors in which one electrode is connected to one side of the fuses of the fuse part 41c, and the gate of the PMOS transistor configured on the other side of the fuse. An activation signal (X-command) for inputting an X address is input thereto, and a redundancy enable signal is applied to a gate of another NMOS transistor to which the other electrodes of the NMOS transistors are all connected.

In the semiconductor memory device having the redundancy block as described above, the MAT is defined as eight mats in the X direction and four mats in the Y direction. The word line is configured to rescue different row fail.

That is, as many Ymats as configured (4 Ymats x 2 = 8) can be saved.

In the semiconductor memory device according to the present invention as defined above, the redundancy circuit in the X direction is largely composed of a fuse part, an address comparison part, and a control part.

In FIG. 3, reference numeral 31 denotes a Y-decoder, and a redundancy word line occurs when a row fail occurs in one normal sub word line 33 to sub word lines connected to one main word line driver block (MWD) 32. Repair using (34).

The redundancy operation is described as follows.

When the X-address is input by the activation signal X-command, the normal word line and the redundancy word line are enabled at the same time.

The redundancy fuse (in FIG. 5) used at this time determines whether the input address information is Xmat where the low fail is located.

When the Y-address is input by the Y-command (Read / Write), the fuse unit and the address comparison unit 41 having the low fail bit and the Ymat information are compared and the determination signal HITmBi is enabled. do.

In addition, if both Y / command inputs have normal / redundancy, the data is loaded on the local I / O line through the corresponding bit line, and if the determination signal (HITmBi) is enabled in the I / O switch block, the redundancy data is transmitted to the main amplifier. Is delivered to the main amplifier.

This redundancy data output has Ymat with one redundancy word line because fuse has both low fail bit information and Ymat information, and both normal and redundancy data are loaded on local I / O line and one of them is output by switch control. Star relief is possible.

Such a semiconductor memory device according to the present invention has the following effects.

According to the present invention, one redundancy word line is provided to enable Ymat-specific relief, and when the same redundancy word line and the number of fuses are provided, the relief efficiency is increased.

In other words, in order to remedy four low fail, four redundancy word lines and 40 fuses are required. Thus, the present invention has one redundancy word line and 44 fuses, thereby increasing redundancy efficiency.

Claims (3)

A semiconductor memory device having a rescue function in which a plurality of rows in a X direction is one unit Xmat and a plurality of columns in a Y direction are one unit Ymat, A fuse unit including a fuse set having Xmat information for a row fail and a fuse set having address bit information Ymat information; An address comparison unit for comparing the X-address information to determine whether or not the input address is a low fail bit and for comparing the Ymat information to output a determination signal HITmBi for determining whether or not the input address is a fail bit; The normal path and the redundancy path are divided by the output signal of the address comparison unit, and the control unit controls the normal word line driver and the input / output switch of the main amplifier by the redundancy path, respectively. Both normal and redundancy are loaded on the local I / O line through the corresponding bit line, and according to the determination signal HITmBi, only one of the two data is output so that one redundancy word line has a Ymat-specific relief. Redundancy circuit in memory device. The method of claim 1, wherein the control unit simultaneously enables the normal and the redundancy word lines by an activation signal (X-command) for inputting an X address, Control signal (XDEi) and input / output switch control signal (IOSW) for controlling the normal word line driver by judging whether data input to the main amplifier is normal or redundancy using the input / output control signal (IOSW) after the read / write signal is input. Outputting a redundancy circuit of the semiconductor memory device. The fuse set according to claim 1, wherein the fuse set having the Xmat information on the low fail in the fuse part includes an X-address signal (XMS0, XMS1, ..., XMS7) at a gate of each NMOS transistor having one electrode connected to one side of the fuses. Is entered, An activation signal (X-command) for inputting an X address is input to a gate of the PMOS transistor configured at the other side of the fuse, A redundancy enable signal is applied to a gate of another NMOS transistor to which the other electrodes of the NMOS transistors are all connected.