KR100357152B1 - apparatus for saving electricity in digital monitor - Google Patents

Abstract

It is to provide a power saving device for digital monitors to satisfy the energy 2000 standard of 3W or less in DPM (Display Power Management) mode, and to provide a Transition Minimized Differential Signal receiver that receives data signals from the video card of the PC. A power saving device for a digital monitor having a digital / analog converter, comprising: a signal amplifier for amplifying a signal received through a predetermined signal channel among R, G, B, and clock signal channels received from a video card of the PC to a predetermined level; And a control unit for outputting a signal for controlling power according to the signal amplified by the signal amplifying unit, and converting an operation mode according to the signal output from the TMDS receiving unit, and a TMDS receiving unit according to the control signal output from the control unit. And a power switch unit for turning on / off the power supplied to the digital / analog conversion unit. Display power by controlling the power supplied to the differential optimization signal receiver and the digital / analog converter according to a signal received through a predetermined channel among the signals received through the R, G, B and clock signal channels, that is, the four signal channels. In Management mode, it has the effect of satisfying the energy 2000 standard of 3W or less.

Description

Apparatus for saving electricity in digital monitor}

The present invention relates to a digital monitor, and more particularly, to a power saving device of a digital monitor.

Hereinafter, a digital monitor according to the prior art will be described with reference to the accompanying drawings.

1 is a diagram illustrating an example of a digital monitor according to the prior art, in which compressed R, G, B, and clock signal channels received from a PC video card (not shown), that is, four signal channels TX0 ±, TX1 ±, TX2. A differential optimization signal (hereinafter abbreviated as TMDS) receiver 1 for extending ±, TcX ±) into 8-bit RGB data and horizontal and vertical synchronization signals (H-Sync) (V-Sync); And a digital / analog converter 2 for converting the RGB data extended by the TMDS receiver 1 into an analog RGB signal corresponding thereto, and the analog RGB signal converted by the digital / analog converter 2 in a predetermined band. A video preamplifier (3) for amplifying a video RGB signal, a video output part (4) for outputting a video RGB signal amplified by a predetermined band by the video preamplifier (3) through a CDT (5); Horizontal and vertical synchronization signals (H-Sync) (V-Sync) extended from the TMDS receiver 1 Therefore, the control unit 6 converts the DPM mode off to the normal mode, and the horizontal and vertical synchronizing signal processing unit generating horizontal and vertical synchronizing signal clock signals according to the horizontal and vertical synchronizing signals output from the control unit 6. It consists of (7).

The operation of the digital monitor according to the prior art configured as described above will be described in detail with reference to the accompanying drawings.

First, the TMDS receiver 1 performs 8 bits on the compressed R, G, B and clock signal channels, that is, four signal channels TX0 ±, TX1 ±, TX2 ±, TcX ±, received from a PC video card (not shown). It expands and outputs RGB data and horizontal and vertical synchronization signals (H-Sync) (V-Sync).

The R, G, and B signal channels TX0 ±, TX1 ±, TX2 ± are transmitted over 350 MHz, the clock signal channel TcX ± is about 65 MHz, and data is enabled through the clock signal channel TcX ±. The signal, data clock, and synchronization signal are combined and transmitted.R, G, B, and clock signal channels, that is, four signal channels (TX0 ±, TX1 ±, TX2 ±, TcX ±), have two lines of + and-as one signal channel. In order to cancel and minimize the noise generated during transmission, one line is composed of a pair of inversion potentials.

Then, the digital / analog converter 2 converts the RGB data extended by the TMDS receiver 1 into an analog RGB signal corresponding thereto and outputs the analog RGB signal.

The video preamplifier 3 then amplifies and outputs the analog RGB signal converted by the digital / analog converter 2 into a video RGB signal of a predetermined band.

The video output unit 4 then outputs the video RGB signal amplified by the video preamplifier 3 to a predetermined band through the CDT 5.

In addition, the controller 6 operates in the normal mode according to the horizontal and vertical synchronization signals (H-Sync) (V-Sync) extended by the TMDS receiver 1.

In addition, when the DPM mode is off, the controller 6 converts to the normal mode according to the horizontal and vertical synchronization signals (H-Sync) (V-Sync) extended by the TMDS receiver (1).

In addition, the horizontal / vertical synchronizing signal processing unit 7 generates horizontal and vertical synchronizing signal clock signals according to the horizontal and vertical synchronizing signals output from the control unit 6.

However, in the conventional digital monitor, about 2.6W of power is generated in the DPM mode, and the power is continuously supplied to the TMDS receiver and the digital / analog converter to convert from the DPM mode to the normal mode. Because the power consumption of about 2W occurs in the negative, there is a problem that does not satisfy the DPM 3W SPEC.

As such, when the power supply to the TMDS receiver and the digital / analog converter is cut off to satisfy the DPM 3W SPEC by reducing the power consumption generated by the TMDS receiver and the digital / analog converter, the horizontal / vertical synchronization signal is not output from the TMDS receiver. Therefore, the controller may not return to the normal mode in the DPM mode.

Accordingly, an object of the present invention is to provide a power saving device of a digital monitor for satisfying the energy 2000 standard of 3W or less in the display power management (DPM) mode.

1 is a view showing an example of a digital monitor according to the prior art;

2 is a view showing an embodiment of a power saving device of a digital monitor according to the present invention;

Explanation of symbols for main parts of the drawings

101: signal amplification unit 102: control unit

103: power switch unit 104: TMDS receiver

105: digital / analog converter 106: video preamplifier

107: video output unit 108: CDT

A feature of the power saving device of a digital monitor according to the present invention for achieving the above object is a digital monitor having a TMDS (Transition Minimized Differential Signal) receiving unit and a digital / analog conversion unit for receiving a data signal from a video card of a PC. A power saving device, comprising: a signal amplification unit for amplifying a signal received through a predetermined signal channel among R, G, B and clock signal channels received from a video card of the PC to a predetermined level, and a signal amplified by the signal amplifying unit Outputs a signal for controlling the power according to the control unit, converts an operation mode according to the signal output from the TMDS receiver, and supplies power supplied to the TMDS receiver and the digital / analog converter according to the control signal output from the controller. It is configured to include a power switch to turn on / off.

The predetermined signal channel is another feature of the clock signal channel TcX ±.

The signal amplifying unit includes a capacitor C1 for removing a DC component of a signal received through the predetermined signal channel, and an amplifier for amplifying a signal from which the DC component is removed from the capacitor C1 according to a predetermined gain. To have other features.

The predetermined gain is another feature of R4 / R3.

The power switch unit includes first and second transistors Tr1 and Tr2 that are turned on / off according to a control signal output from the controller.

The first and second transistors Tr1 and Tr2 are cascade-coupled.

The present invention controls the power supplied to the differential optimization signal receiver and the digital / analog converter according to a signal received through a predetermined signal channel among R, G, B, and clock signal channels, that is, four signal channels. In Power Management mode, energy 2000 standard of 3W or less can be satisfied.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, a preferred embodiment of a power saving device for a digital monitor according to the present invention will be described with reference to the accompanying drawings.

2 is a view showing an embodiment of a power saving device of a digital monitor according to the present invention, through an image (R, G, B) received from a video card of a PC and a clock signal channel, that is, a clock signal channel among four signal channels. Signal amplification unit 101 for amplifying the received signal to a predetermined level, and outputs a signal for controlling the power in accordance with the signal amplified by the signal amplification unit 101, horizontal, vertical synchronization signal (H-Sync) From the control unit 102 for switching the operation mode according to (V-Sync), the power switch unit 103 for turning on / off the power according to the control signal output from the control unit 102, and the video card of the PC. Extend the received compressed R, G, B, and clock signal channels (TX0 ±, TX1 ±, TX2 ±, TcX ±) into 8-bit RGB data and horizontal and vertical sync signals (H-Sync) (V-Sync) The TMDS receiver 104 and the RGB data extended by the TMDS receiver 104 correspond to analog RGB signals. A digital / analog converter 105 for converting, a video preamplifier 106 for amplifying an analog RGB signal converted by the digital / analog converter 105 into a video RGB signal of a predetermined band, and the video preamp It comprises a video output unit 107 for outputting a video RGB signal amplified in a predetermined band in the unit 106 through the CDT 108, the present invention is not limited by the illustration here.

The signal amplifier 101 includes a capacitor C1 for removing a DC component of a signal received through the predetermined signal channel, and an amplifier for amplifying a signal from which the DC component is removed from the capacitor C1 according to a predetermined gain ( 101a).

The power switch 103 includes first and second transistors Tr1 and Tr2 that are turned on and off according to a control signal output from the controller 102. Tr1) (Tr2) is cascaded.

The operation of the power saving device of the digital monitor according to the present invention configured as described above will be described in detail with reference to the accompanying drawings.

First, the signal amplifier 101 amplifies a signal received through a clock signal channel TcX ± among the images R, G, and B received from a video card (not shown) of a PC and a clock signal channel to a predetermined level. After that, the result signal is output.

The R, G, and B signal channels TX0 ±, TX1 ±, TX2 ± are transmitted over 350 MHz, the clock signal channel TcX ± is approximately 65 MHz, and the data enable signal and data are used as the clock signal channel. Clock and sync signals are combined and transmitted, and R, G, B and clock signal channels, that is, four signal channels (TX0 ±, TX1 ±, TX2 ±, TcX ±), generate two signal lines, + and-. One line is composed of a pair of inversion potentials to cancel and minimize noise.

The R, G, B, and clock signal channels, i.e., the four signal channels TX0 ±, TX1 ±, TX2 ±, TcX ±, are the R, G, B, and clock signal channels, i.e., the four signal channels TX0 ±, TX1 in the normal mode. ±, TX2 ±, TcX ±) with a 0.5V swing width that varies from 3.3V to 2.8V. In DPM mode, R, G, B and clock signal channels, that is, 4 signal channels (TX0 ±, TX1 ±, TX2 ±, TcX ±) will be transmitted as 3.3V high signal.

That is, the capacitor C1 in the signal amplifying unit 101 is 0.5V in which the signals received through the R, G, B and clock signal channels received from the video card (not shown) of the PC are varied to 2.8V in the normal mode. 0.5V received through the clock signal channel TcX ± of the R, G, B, and clock signal channels, that is, the four signal channels TX0 ±, TX1 ±, TX2 ±, TcX ±, if the signal has a swing width. After the DC component included in the signal having the swing width is removed, the resultant signal is output.

Then, the amplifier 101a in the signal amplifier 101 amplifies a signal having a 0.5V swing width from which the DC component is removed from the capacitor C1 according to a predetermined gain (β = R4 / R3). The resultant signal is output through the resistor R5.

Accordingly, the controller 102 operates the TMDS receiver 104 and the digital / analog converter 105 in a normal mode when a signal having a swing level of a predetermined level amplified by the signal amplifier 101 is input. Outputs a power supply control signal for

That is, the controller 102 outputs a high signal through the PD terminal in the normal mode when a signal having a swing level of a predetermined level amplified by the signal amplifier 101 is input to the SCDT terminal.

Then, the power switch 103 supplies the power supplied to the TMDS receiver 104 and the digital / analog converter 105 according to the hi signal output from the controller 102.

That is, the first and second transistors Tr1 and Tr2 in the power switch unit 103 are turned on in accordance with the high signal output from the control unit 102 so that the TMDS receiver 104 and the digital / analog converter are turned on. The power supply (+ 5V) is supplied to 105.

Accordingly, the TMDS receiving unit 104 receives the R, G, B and clock signal channels, i.e., 4 signal channels TX0 ±, received from the video card (not shown) of the PC according to the power supplied through the power switch 103. , TX1 ±, TX2 ±, TcX ±) are extended by 8-bit RGB data and horizontal and vertical sync signal (H-Sync) (V-Sync).

Then, the control unit 102 performs an operation in the normal mode according to the horizontal and vertical synchronizing signal (H-Sync) (V-Sync) extended by the TMDS receiving unit 104.

In addition, the digital / analog converter 105 converts 8-bit RGB data extended by the TMDS receiver 104 into analog RGB signals corresponding to the power supplied through the power switch 103. .

Then, the video preamplifier 106 amplifies and outputs the analog RGB signal converted by the digital / analog converter 105 into a video RGB signal of a predetermined band.

Accordingly, the video output unit 107 outputs the video RGB signal amplified by the video preamplifier 106 to a predetermined band through the CDT 108.

In addition, the capacitor C1 in the signal amplifying unit 101 has a 3.3V high signal in the DPM mode when signals received through the R, G, B and clock signal channels received from the video card (not shown) of the PC. If the signal has a 0.5V swing width received through the clock signal channel TcX ± of the R, G, B and clock signal channels, that is, four signal channels TX0 ±, TX1 ±, TX2 ±, TcX ±. After the DC component included in the signal is removed, the result signal is output.

Therefore, since the DC voltage received from the capacitor C1 through the clock signal channel TcX ± is removed from the capacitor C1, the signal 101 outputs no signal through the resistor R5.

Then, the controller 102 outputs a low signal for cutting off the power supply (+ 5V) because no signal is output from the signal amplifier 101.

Accordingly, the first and second transistors Tr1 and Tr2 in the power switch unit 103 are turned off according to the low signal output from the control unit 102, and the TMDS receiver 104 and the digital / analog are turned off. The power supply (+ 5V) supplied to the converter 105 is cut off.

Accordingly, since the TMDS receiving unit 104 does not perform an operation, the control unit 102 does not receive the horizontal and vertical synchronization signals (H-Sync) (V-Sync) extended from the TMDS receiving unit 104 and thus the DPM. The operation is performed in the mode.

In this state, a 3.3V high signal in the DPM mode is converted into a signal having a 0.5V swing width that is varied from 3.3V to 2.8V in the normal mode from the video card of the PC. The capacitor C1 in the signal amplifying unit 101 is connected to the clock signal channel TcX ± among the R, G, B and clock signal channels, that is, the four signal channels TX0 ±, TX1 ±, TX2 ±, and TcX ±. The DC component included in the signal having the received 0.5V swing width is removed and the resultant signal is output.

Then, the amplifier 101a in the signal amplifier 101 amplifies a signal having a 0.5V swing width from which the DC component is removed from the capacitor C1 according to a predetermined gain (β = R4 / R3). The resultant signal is output through the resistor R5.

Accordingly, the controller 102 may operate the TMDS receiver 104 and the digital / analog converter 105 according to an input of a signal having a swing level of a predetermined level amplified by the signal amplifier 101. Output the power control signal.

That is, the controller 102 outputs a high signal through the PD terminal when a signal having a swing level of a predetermined level amplified by the signal amplifier 101 is input to the SCDT terminal.

Then, the power switch 103 supplies the power supplied to the TMDS receiver 104 and the digital / analog converter 105 according to the high signal output from the controller 102.

That is, the first and second transistors Tr1 and Tr2 in the power switch unit 103 are turned on in accordance with the high signal output from the control unit 102 so that the TMDS receiver 104 and the digital / analog converter are turned on. The power supply (+ 5V) is supplied to 105.

Accordingly, the TMDS receiving unit 104 receives the R, G, B and clock signal channels, i.e., 4 signal channels TX0 ±, received from the video card (not shown) of the PC according to the power supplied through the power switch 103. , TX1 ±, TX2 ±, TcX ±) are extended by 8-bit RGB data and horizontal and vertical sync signal (H-Sync) (V-Sync).

Then, the control unit 102 performs an operation in the normal mode according to the horizontal and vertical synchronizing signal (H-Sync) (V-Sync) extended by the TMDS receiving unit 104.

In addition, the digital / analog converter 105 converts 8-bit RGB data extended by the TMDS receiver 104 into analog RGB signals corresponding to the power supplied through the power switch 103. .

Then, the video preamplifier 106 amplifies and outputs the analog RGB signal converted by the digital / analog converter 105 into a video RGB signal of a predetermined band.

Accordingly, the video output unit 107 outputs the video RGB signal amplified by the video preamplifier 106 to a predetermined band through the CDT 108.

As described above, the power saving device of the digital monitor according to the present invention includes a differential optimization signal receiving unit and a digital / digital signal according to a signal received through a predetermined signal channel among R, G, B, and clock signal channels. By controlling the power supplied to the analog converter, DPM (Display Power Management) mode has the effect of satisfying the energy 2000 specification of 3W or less.

From the above description, those skilled in the art can appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Claims (6)

In the power saving device of a digital monitor provided with a TMDS (Transition Minimized Differential Signal) receiver and a digital / analog converter for receiving data signals from a video card of a PC, A signal amplifier for amplifying a signal received through a predetermined signal channel among R, G, B, and clock signal channels received from the video card of the PC to a predetermined level; A control unit for outputting a signal for controlling power according to the signal amplified by the signal amplifying unit and converting an operation mode according to the signal output from the TMDS receiving unit; And a power switch unit for turning on / off the power supplied to the TMDS receiver and the digital / analog converter according to the control signal output from the controller. The method of claim 1, And the predetermined signal channel is a clock signal channel (TcX ±). The method of claim 1, The signal amplification unit And a capacitor (C1) for removing the DC component of the signal received through the predetermined signal channel, and an amplifier for amplifying the signal from which the DC component is removed from the capacitor (C1) according to a predetermined gain. Power saver for the monitor. The method of claim 3, And said predetermined gain is R4 / R3. The method of claim 1, The power switch unit And a first and second transistors (Tr1) (Tr2) turned on / off according to a control signal output from the controller. The method of claim 5, The first and second transistors (Tr1) (Tr2) is a power saving device of a digital monitor, characterized in that the cascade (cascade) coupled.