KR100356949B1 - Method of Separating ATM Cell and MPLS Cell - Google Patents

Abstract

The present invention relates to a method for separating an ATM cell and an MPLS cell. In particular, the matching board defines an extra bit in addition to the ATM cell format to indicate whether an ATM cell is present, and determines the corresponding bit in a forwarding engine (F / E) board. The present invention relates to an ATM cell and an MPLS cell separation method for separating an ATM cell and an MPLS cell.

In the MPLS system based on the conventional ATM switch, a cell delay occurs while several steps are unnecessary until a pure ATM cell is transmitted to the F / E, and the CPU controlling the SAR transmitter / receiver in the F / E I did unnecessary processing.

According to the present invention, in a MPLS system based on an ATM exchanger, the LIC or LIC MUX stores a range that a VPI / VCI value of a pure ATM cell can have, and tags each input cell as a pure ATM cell or an MPLS cell. By examining the corresponding tag bits at the input ICB interface of the F / E, it is possible to minimize delays and improve the quality of pure ATM service when a pure ATM cell passes through an MPLS node or network.

In addition, by reducing the load on the SAR chips and CPU in the F / E, it is possible to increase the service performance associated with MPLS.

Description

Method of Separating ATM Cell and MPLS Cell

The present invention relates to an Asynchronous Transfer Mode (ATM) cell and a Multi-Protocol Label Switching (MPLS) cell separation method. In particular, a matching board defines an extra bit in addition to the ATM cell format to indicate whether an ATM cell is present and F / E (Forwarding Engine) This method relates to a method of separating an ATM cell and an MPLS cell in which a corresponding bit is determined by a board to separate an ATM cell and an MPLS cell.

In general, an Asynchronous Transfer Mode-Multi-Protocol Label Switching (ATM-MPLS) exchange provides an ATM-based MPLS service, which is being standardized in the MPLS Working Group (WG) of the Internet Engineering Task Force (IETF). It is a proven standard technology to speed up network traffic flow and make it easy to manage. MPLS is involved in establishing a specific path for a given packet sequence, where each packet has a label, which saves the router the time it takes to see the address of the node to which the packet should be forwarded. MPLS is called multiprotocol because it works with IP, ATM, and frame relay network protocols. In terms of the OSI standard reference model of the network, MPLS allows most packets to be delivered at the second layer of switching, not at the third layer (routing).

The ATM-MPLS switch provides MPLS services by adding an MPLS control processor board and forwarding engine (FE) to the existing ATM switch. It provides MPLS IP service while directly interworking with router through ATM / frame relay interface. Especially, if PPP control software block is installed in ATM-MPLS exchange to provide PPP service, it accepts IP service by directly accepting subscriber terminal. It is responsible for the distributed reception of subscribers in ATM-MPLS exchanges.

As described above, the MPLS Label Edge Router (MPLS_LER) system based on an Asynchronous Transfer Mode (ATM) exchange, as shown in Fig. 1, includes a switch 1, a main control unit 2, and a line interface card unit ( Line Interface Card: LIC, 4)

The switch 1 plays a role of exchanging ATM cells, and the main control unit 2 performs software related parts such as call processing, maintenance, billing and statistics.

The LIC (4) performs the function of matching with the external link, distinguishes ATM data flow through VPI / VCI, and controls each ATM data flow to each switch to control the traffic type and characteristics for each ATM data flow. Perform the function of passing.

As shown in Fig. 2, the LIC 4 includes a line physical interface unit 8, a port control unit 10, and an ICB interface 11, and each device includes a CPU control unit 7. Will control. In the case of the LIC MUX, the multiplexing / demultiplexing unit 9, the port control unit 10, and the ICB interface 11 are included.

As shown in FIG. 3, the ICB interface 11 inside the LIC 4 includes a cell transmitter / receiver 12, a cell format converter 13, and an internal cell transmitter / receiver 14. Each control device is controlled by the CPU control unit 7.

The cell transmitter / receiver 12 performs a function of exchanging cells with the port controller 10.

The cell format converter 13 changes the format of the port controller 10 and the ICB interface 11 when the cell formats are different.

The internal cell transmitter / receiver 14 plays a role of exchanging cells which have been reformatted into internal cells.

Meanwhile, the parts related to the MPLS function include an IP / MPLS control unit 3 and an F / E 6, and the IP / MPLS control unit 3 includes an Internet protocol, a routing protocol, and a GSMP. (General Switch Management Protocol) and LDP (Label Distribution Protocol) software is performed, and the F / E (6) assembles IP packets at the MPLS network entrance, analyzes the corresponding IP header, and labels ( After generating and attaching a label, the label is segmented into an ATM cell and then transmitted to a next node (eg, a switch or a router).

The F / E 6 is a hardware board that performs a function of processing various types of traffic such as IP packets, PPP packets, and MPLS packets input to the ATM-MPLS switch at high speed and transmitting them to an appropriate output interface. As shown, the input terminal ICB interface 15, the SAR (Segmentation) receiver 16, the lookup control unit 17, the FIB / LIB 23, the SAR transmitter 18, and the SAR receiver 16 The control memory 20, the packet memory 21, the control memory 24, the packet memory 25, and the output terminal ICB interface 19 of the SAR transmitter 18 are included.

The control memory units 20 and 24 are memories for storing SAR control information, and the packet memory unit 21 is a memory for storing received packets.

In the MPLS system structure based on the ATM switch, MUX (Multiplexing, 5) has multiple LIC data when the data processing speed of one port, which is the basic unit of the corresponding switch (1), is greater than one data processing speed of the LIC. It binds streams and turns them into one Switch Port-Size Data Stream.

As described above, the LIC (4) of the MPLS system based on the ATM exchanger does not distinguish whether it is a pure ATM cell or an MPLS cell, and processes the same ATM cell and transmits the same ATM cell to the next stage F / E (6). Then, in the next stage F / E 6, the SAR receiver 16 collects the packet data received in the packet memory and stores the packet data in its own packet memory. Then, the header information of the packet is checked and the connection information is checked and determined. If the cell corresponds to the cell, the cell is transmitted to the SAR transmitter 18 without passing through the look-up controller 17. The SAR transmitter 18 receives the packet, stores the packet in the packet memory unit 25, and then checks and determines the connection information of the packet, and transmits the packet to the switch 1.

However, when the SAR receiver 16 checks the header information of the received packet and checks and determines the connection information, if the packet is an MPLS cell, the header information of the packet is transferred to the lookup controller 17 for use in the MPLS network. The label information is attached to the packet and transmitted to the switch 1.

Therefore, in the MPLS system based on the conventional ATM exchanger, cell delay occurs while several steps are unnecessary until a pure ATM cell is transmitted to the F / E 6, and a SAR in the F / E 6 is generated. The CPU controlling the transmitter 18 and the SAR receiver 16 performed unnecessary processing.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned general problems, and its object is to provide a pure ATM cell and an unnecessary cell delay experienced by a pure ATM cell when MPLS cells are transmitted to a switch port in an ATM-based MPLS system. To reduce the load on the associated SAR chip and the CPU.

1 is a diagram illustrating a structure of an MPLS system based on a general ATM switch.

2 is a diagram illustrating a LIC in an MPLS system based on a typical ATM switch.

3 is a diagram illustrating the ICB interface structure inside a LIC in an MPLS system based on a general ATM switch.

4 is a diagram showing F / E in an MPLS system based on a general ATM switch.

FIG. 5 illustrates an input ICB interface inside the F / E in an MPLS system based on a general ATM switch. FIG.

6 is a diagram illustrating an ICB interface structure inside a LIC in an MPLS system based on an ATM switch according to an embodiment of the present invention.

FIG. 7 illustrates an input ICB interface structure in an F / E in an MPLS system based on an ATM switch according to an embodiment of the present invention. FIG.

8 is a flowchart illustrating an operation of tagging at an ATM cell tagging control unit in an ICB interface of LIC or LIC_MUX in a method of separating an ATM cell and an MPLS cell according to an embodiment of the present invention.

9 is a flowchart illustrating an operation of determining and processing a tag bit in an ATM cell tag bit check unit inside an F / E input terminal ICB interface in an ATM cell and MPLS cell separation method according to an embodiment of the present invention.

* Description of Symbols for Drawings *

1: switch 5: MUX / DMUX

2: Main control unit 6: F / E

3: IP / MPLS control unit

4: LIC

The ATM cell and MPS cell separation method of the present invention for achieving the above object has a range that the call connection management function can have the VPI / VCI value of the pure ATM cell and the VPI / VCI value of the MPLS cell Assigning a range to the matching function; Upon receipt of the cell, checking the header's VPI / VCI value by the matching function and tagging the additional spare bit in the case of a pure ATM cell; Checking and determining a VPI / VCI value of a header of the cell at a cell input terminal of an F / E; In the case of a pure ATM cell, the method includes transmitting the cell to an output terminal of the F / E.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

In the MPLS system based on the ATM switch according to the present invention, the corresponding F / E is similar to that of a general F / E. Hereinafter, the ATM in the MPLS system based on the ATM switch according to the present invention will be described with reference to FIG. The cell and MPLS cell separation method will now be described.

In the MPLS system based on the ATM switch according to the embodiment of the present invention, the ICB interface inside the LIC or the LIC is, as shown in FIG. 6, the CPU controller 10, the ATM cell tagging controller 20, and the cell transfer / A receiver 30, a cell format converter 40, and an internal cell transmitter / receiver 50 are included.

The CPU controller 10 controls devices such as the ATM cell tagging controller 20, the cell transmitter / receiver 30, the cell format converter 40, and the internal cell transmitter / receiver 50. In charge.

The ATM cell tagging control unit 20 is responsible for controlling the ATM cell tag bit check unit 70 which checks the ATM cell bits and transmits the cells or packets determined to be pure ATM cells to the output terminal ICB interface 19.

Since the cell transmitter / receiver 30, the cell format converter 40, and the internal cell transmitter / receiver 50 are the same as in the prior art, description thereof will be omitted.

In the MPLS system based on the ATM exchange system according to the embodiment of the present invention, the input ICB interface inside the F / E is shown in FIG. 7, by the CPU control unit 10, the ATM cell tag bit check unit 70, The cell transmitter / receiver 80, the cell format converter 90, and the SAR interface 100 are included.

The CPU control unit 10 is responsible for controlling devices such as the ATM cell tag bit check unit 70, the cell transmitter / receiver unit 80, the cell format converter 90, and the SAR interface 100. do.

The ATM cell tag bit check unit 70 checks the ATM cell bits and transmits the cells or packets determined to be pure ATM cells to the output terminal ICB interface 19.

Since the cell transmitter / receiver 80, the cell format converter 90, and the SAR interface 100 are the same as in the prior art, description thereof will be omitted.

In the ATM cell and MPLS cell separation method according to an embodiment of the present invention, the tagging operation in the ATM cell tagging control unit in the ICB interface of LIC or LIC_MUX will be described with reference to the flowchart of FIG. 8.

First, when the cell is received by the cell transmitting / receiving unit 30 (step S81), the ATM cell tagging control unit 20 compares whether the VPI / VCI value of the received cell is included in a predetermined range by higher software (step S81). Step S82). As a result of the comparison, the ATM cell tagging control unit 20 determines whether the received cell is an ATM cell (step S83), and if the received cell is not a pure ATM cell (Untagging) (step S84), the received cell If this is a pure ATM cell, tagging (step S85). Thereafter, the cell is transmitted to the cell format converter 40 (step S86).

Determining and processing tag bits in the ATM cell tag bit check unit inside the F / E input terminal ICB interface in the method for separating ATM and MPLS cells according to an embodiment of the present invention will be described with reference to the flowchart of FIG. Same as

First, when the cell is received by the cell transmitting / receiving unit 80 (step S91), the ATM cell tag bit check unit 70 checks the tag bits of the cell (step S92), and then the result of the check is that the cells are tagged. It is judged whether or not it is (step S92). If the cell is not tagged, the cell is transmitted to the cell format converter 90 (step S93). Thereafter, the corresponding IP packet is transmitted to the SAR transmitter / receiver 16 and 18 of the F / E through the SAR interface 100 again.

However, if the cell is tagged, the ATM cell is transmitted to the output terminal ICB interface 60 (step S94).

Although the preferred embodiments of the present invention have been described in detail above, it will be understood by those skilled in the art that the present invention may be modified or modified in various ways. Therefore, changes of the embodiments of the present invention will not be able to escape the technical scope of the present invention.

As described above, according to the present invention, in the MPLS system based on the ATM exchanger, each cell inputted by specifying a range that the VPI / VCI value of the pure ATM cell can have in the LIC or LIC MUX is a pure ATM cell, By tagging the acknowledgment and checking the corresponding tag bits at the input ICB interface of the F / E, it is possible to minimize delays when a pure ATM cell crosses an MPLS node or network and improve the quality of pure ATM service. Can be.

In addition, by reducing the load on the SAR chips and CPU in the F / E, it is possible to increase the service performance associated with MPLS.

Claims (4)

Assigning, by the call connection management function, to the matching function a range that the VPI / VCI value of the pure ATM cell can have and a range of the VPI / VCI value of the MPLS cell; Upon receipt of the cell, checking the header's VPI / VCI value by the matching function and tagging the additional spare bit in the case of a pure ATM cell; Checking and determining a VPI / VCI value of a header of the cell at a cell input terminal of an F / E; In the case of a pure ATM cell, AMT cell and MPS cell separation method comprising the step of transmitting the cell to the output terminal of the F / E. The method according to claim 1, In the case of the pure ATM cell, the AMT cell and MPS cell separation method characterized in that it further comprises the step of tagging the additional extra bits, and transmitting the cell to the cell format converter. The method according to claim 1, If it is not the pure ATM cell, untagged and transmitting the cell to the cell format conversion unit, characterized in that the ATM cell and MPS cell separation method characterized in that it further comprises. The method according to claim 1, Inspecting and determining a VPI / VCI value of a cell header at a cell input terminal of the F / E, checking a tag bit when a cell is received; If a corresponding cell is tagged at the cell input terminal of the F / E, transmitting the cell to the output terminal ICB interface of the F / E terminal; If the corresponding cell is not tagged at the cell input terminal of the F / E, the method comprising the step of transmitting the cell to the cell format conversion unit characterized in that it further comprises a cell.