KR100351954B1 - Ethernet Repeating Circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to Ethernet repeating circuits, and more particularly, to Ethernet repeating circuits connected to fast Ethernet logic to accommodate high speed data.

The present invention provides an Ethernet repeating circuit including a MAC (Media Access Control) for connecting to a higher layer, a plurality of jacks for connecting to a terminal device through a line, and a plurality of transformers for transmitting and receiving data with the terminal device through a corresponding jack. A plurality of Fast Ethernet repeaters that sense the speed of input data by the automatic sensing function and repeat the high speed data or the low speed data to be transmitted to another port of the jack or to another repeater through the mutual repeating backplane interface. Wow; A logic circuit unit for converting corresponding data according to signal level and timing for data transmission and reception between the MAC and the Fast Ethernet repeater; A bridge controller for converting the low speed data into the high speed data or converting the high speed data into the low speed data using a media independent interface (MII); And converting the high speed data into the low speed data, wherein the memory unit buffers the high speed data for a while. Alternatively, each Fast Ethernet repeater is internally connected to each other via a first mutual repeating backplane interface for transmitting the low speed data to another repeater and a second mutual repeating backplane interface for transmitting the high speed data to another repeater. And a built-in bridge control function instead of the bridge control unit to convert the low speed data into the high speed data or the high speed data into the low speed data.

Description

Ethernet Repeating Circuit {Ethernet Repeating Circuit}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to Ethernet repeating circuits, and more particularly, to Ethernet repeating circuits connected to Fast Ethernet Logic to accommodate high speed data.

As shown in FIG. 1, a typical 10 Mbps Ethernet repeater circuit includes a MAC 11, a 10 Mbps transceiver 12, and a plurality of 10 Mbps repeaters 13-1 to 13. -n), a plurality of transformers 14-1 to 14-n, and a plurality of RJ45 modular jacks 15-1 to 15-n.

The MAC 11 may use a central processing unit (CPU) having a built-in MAC function. The MAC 11 transmits data received from the transceiver 12 to a higher layer or transmits data received from an upper layer to the transceiver 12. ) Here, the MAC is a layer inherent to a local access network (LAN) that exists on a property in which multiple nodes share the same medium as part of a data link layer of an Open Systems Interconnection (OSI) reference model.

The transceiver 12 performs a physical conversion process of data corresponding to the first layer of the OSI 7 layer and transfers the processed data to the MAC 11 or a CPU having a MAC function or the MAC The data applied from (11) is transferred to the repeaters 13-1 to 13-n.

Two or more components are used for the repeaters 13-1 to 13-n according to the number of ports to be provided, and data received from each port or received from the transceiver 12 Sends data back to each port. In addition, the repeaters 13-1 to 13-n are connected to each other through an inter-repeating backplane of 10 (Mbps).

The transformers 14-1 to 14-n are optimally selected according to the number of ports to be provided, and each of the repeaters 13-1 to 13-n and the jacks 15-1 to 15-n. Located between) performs isolation between internal circuit logic and external line.

The jacks 15-1 to 15-n are Ethernet LAN ports connected to the outside, and connect terminals using a LAN, such as a PC, a notebook, or a printer.

The operation of the Ethernet repeater circuit configured as described above is as follows. Here, for convenience of explanation, the description is divided into two parts, one of which has a circuit related to repeating transmission data and the other has a MAC related circuit which is responsible for filtering or forwarding data. .

The repeating-related circuit corresponds to the physical layer of the first layer among the OSI 7 layers, and data applied through the RJ45 modular jacks 15-1 to 15-n and the transformers 14-1 to 14-n are included. The repeaters 13-1 to 13-n are retransmitted to the remaining ports of the corresponding jacks 15-1 to 15-n or transmitted to the transceiver 12. In this case, an attachment unit interface (AUI) is generally used for the connection between the transceiver 12 and each repeater 13-1 to 13-n.

Accordingly, the transceiver 12 converts data applied from the repeaters 13-1 to 13-n into data corresponding to a first layer, that is, a physical layer, and converts the converted data into the MAC 11. It plays a role to deliver. At this time, the interface between the transceiver 12 and the MAC 11 is usually composed of seven signals, such as a clock (Clock), data, a transmit enable signal (Transmit Enable Signal). Here, for the corresponding signal interface, the transceiver 12 converts an analog signal applied from each repeater 13-1 to 13-n into a digital signal and generates a clock signal accordingly. Transfer to the MAC (11).

Then, the MAC 11 is the MAC layer of the second layer among the OSI 7 layers, and should analyze the header of the data applied from the transceiver 12 and forward it to a higher layer or Discard. It acts as a filter to decide what to do.

On the contrary, the packet received from the upper layer, that is, the third layer, is transmitted to the MAC 11, and data is transmitted in the reverse order as described above, so that the transceiver 12 and each repeater 13-1 to 13- are transmitted. After passing through n), the data can be transmitted to all ports so that the terminal device having the corresponding address can receive the corresponding data.

In this way, the flow of data applied from the terminal of one port of the jacks 15-1 to 15-n is transmitted to the terminal or the device connected to the other port, and through the conversion of the packet even if not the same segment The data can be delivered.

As described above, in the conventional Ethernet repeater circuit, by limiting the data transmission speed of a terminal or hub connected to each port to a maximum of 10 (Mbps), a transmission speed of 100 (Mbps), which is currently popularized, is limited. Difficult to accept Therefore, transmission delay occurs in a situation where there is a large amount of data traffic, causing problems in efficient and rapid data processing, which becomes a obstacle of the network, and it is a cause for costly to solve it.

In order to solve the above problems, the present invention converts the Ethernet repeater circuit to be connected to the 10 and 100 (Mbps) Fast Ethernet logic by utilizing the existing 10 (Mbps) MAC interface, If you don't need many LAN ports such as home or small office space, the goal is to improve the transmission speed and make the most of the resources you have at a low cost.

1 is a block diagram illustrating a conventional Ethernet repeater circuit.

2 is a block diagram illustrating an Ethernet repeating circuit according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

20: MAC (Media Access Control)

30: PLD (Programmable Logic Device)

40: Random Access Memory

50: bridge controller

60-1 to 60-n: repeater

70-1 to 70-n: Transformer

80-1 ~ 80-n: Jack

The present invention for achieving the above object is a media access control (MAC) for connecting to the upper layer, a plurality of jacks for connecting to the terminal device via a line, and a plurality of transmitting and receiving data with the terminal device through the corresponding jack In an Ethernet repeating circuit having two transformers, an automatic sensing function senses the speed of input data and repeats the high speed data or the low speed data and transmits it to another port of the jack again or through a mutual repeating backplane interface. A plurality of Fast Ethernet repeaters for transmitting to the repeater; A logic circuit unit for converting corresponding data according to signal level and timing for data transmission and reception between the MAC and the Fast Ethernet repeater; A bridge controller for converting the low speed data into the high speed data or converting the high speed data into the low speed data using a media independent interface (MII); And converting the high speed data into the low speed data, wherein the memory unit buffers the high speed data for a while.

Alternatively, each Fast Ethernet repeater is internally connected to each other via a first mutual repeating backplane interface for transmitting the low speed data to another repeater and a second mutual repeating backplane interface for transmitting the high speed data to another repeater. A bridge control function is built in place of the bridge control unit to convert the low speed data into the high speed data or the high speed data into the low speed data.

Preferably, the logic circuit unit converts a 7-wire interface signal applied from the MAC to a mutually repeating backplane interface signal and transmits the signal to the Fast Ethernet repeater, and transmits the mutually repeating backplane interface signal applied from the fast Ethernet repeater. The signal is converted into a 7-wire interface and transmitted to the MAC.

The present invention allows a 10 and 100 (Mbps) Fast Ethernet LAN configuration system to be connected to a 7 wire interface MAC, and provides a programming method for accessing the 7 wire interface MAC. Mbps) interface between Fast Ethernet repeaters. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 2, the Ethernet repeating circuit according to an embodiment of the present invention includes a MAC 20, a PLD 30, a RAM 40, a two-port bridge controller 50, and a plurality of 10. And 100 (Mbps) Fast Ethernet repeaters (60-1 to 60-n), multiple transformers (70-1 to 70-n), and multiple RJ45 modular jacks (80-1 to 80-n) Is done.

The MAC 20 delivers data authorized from the PLD 12 to a higher layer, or transmits data authorized from a higher layer to the PLD 12.

Since the PLD 30 can program simple logic devices therein according to the intention of the developer, the PLD 30 is connected to the MAC 20 after conversion according to the signal level and timing.

The RAM 40 temporarily buffers the data due to the speed difference in the process of converting 100 (Mbps) data into 10 (Mbps) in the bridge controller 50 or the repeaters 60-1 to 60-n. Therefore, it is connected to the bridge control unit 50. In this case, in general, a direct connection interface is provided, and when the repeaters 60-1 to 60-n have a built-in bridge control function, the RAM 40 is directly connected to the repeaters 60-1 to 60-n. Is connected to.

The bridge controller 50 is a module for exchanging data with 10M terminal devices and 100M devices, and converts 10 (Mbps) data into 100 (Mbps) data or converts 100 (Mbps) data. Converts to 10 (Mbps) data. Here, when the repeaters 60-1 to 60-n have a built-in bridge control function, the bridge controller 50 is not necessary.

The repeaters 60-1 to 60-n may have a built-in bridge control function, and may detect a speed of input data by an auto-sensing function and process 10 (Mbps) data. There is a part that handles 100 (Mbps) data, and 10 (Mbps) first mutual repeating backplane interface and 100 (Mbps) second mutual repeating backplane interface to internally connect each other when using a large number Equipped with. Here, the first mutual repeating backplane interface is connected to the PLD 30 again.

The transformers 70-1 to 70-n allow the terminal device to be connected through a line (usually a twisted pair line), and the repeater 60-1 to 60-n or a transceiver ( For convenience of description, it is determined by the characteristic of (not shown in the drawing), and the data applied through the jacks 80-1 to 80-n is transferred to the repeaters 60-1 to 60-n or The data applied from the repeaters 60-1 to 60-n is transferred to the jacks 80-1 to 80-n.

The jacks 80-1 to 80-n allow the terminal device to be connected through a line, and receive data from the terminal device and apply the data to the transformers 70-1 to 70-n or the transformer 70 -1 ~ 70-n) receives the data from the terminal device.

Referring to the operation of the Ethernet repeating circuit according to an embodiment of the present invention configured as described above are as follows.

First, referring to the process of processing the received data, the data input through one of the plurality of RJ45 modular jacks (80-1 to 80-n) through the transformer (70-1 to 70-n) each 10 ( Mbps) and 100 (Mbps) Fast Ethernet Repeaters (60-1 to 60-n). At this time, the speed of the data is automatically detected by the automatic sensing function of the repeater (60-1 ~ 60-n).

Thus, if 10 (Mbps) data is repeated through the repeating circuit inside the repeaters (60-1 ~ 60-n) is transmitted to another port of the jack (80-1 ~ 80-n) or It is transmitted to other repeaters 60-1 to 60-n via a 10 Mbps first mutual repeating backplane interface.

On the other hand, even in the case of 100 (Mbps) data, the repeater repeats through a repeating circuit inside the repeaters 60-1 to 60-n and transmits the data to another port of the jacks 80-1 to 80-n. Or to another repeater 60-1 to 60-n via a 100 Mbps second mutual repeating backplane interface.

Meanwhile, in order to convert 10 (Mbps) data into 100 (Mbps) data or convert 100 (Mbps) data into 10 (Mbps) data, a bridge control function is required, and the repeaters 60-1 to 60-n A bridge control function is provided therein to perform a corresponding operation or a bridge controller 50 is separately provided to perform the corresponding operation.

Here, the interface connected to the bridge control unit 50 uses a media independent interface (MII), and the MII exists in the bridge control unit 50 and the repeaters 60-1 to 60-n.

In addition, since the port of the bridge controller 50 has an internal MAC function when 10 (Mbps) data is input, the 10 (Mbps) data may be converted into 100 (Mbps) data and output to the opposite port. In order to convert 100 (Mbps) data into 10 (Mbps) data when 100 (Mbps) data is input, a buffer to temporarily store data must exist because of speed difference. In this case, the buffer 40 is used by connecting the RAM 40 to the bridge controller 50.

That is, the bridge controller 50 temporarily stores the 100 (Mbps) data in the RAM 40, converts the data into 10 (Mbps) data, and outputs the 10 (Mbps) data transmission equipment and 100 (Mbps). Communication between transmission equipment becomes possible.

On the other hand, the repeater to transmit the data applied from the repeater (60-1 ~ 60-n) to the corresponding MAC 20 in order to determine the forwarding or disk through the MAC level data analysis in the MAC (20) Direct connection between the 60-1 to 60-n and the corresponding MAC 20 is not made, so that the PLD 30 is required, and the PLD 30 performs signal conversion.

At this time, the signal conversion of the PLD 30 is a signal of a 10 (Mbps) first mutual repeating backplane interface and a signal of a 7 wire interface (or a 10 (Mbps) Ethernet interface, referred to as GPSI). Here, the signals of the 7-wire interface include the transmit enable signal (/ TxE), the receive enable signal (/ RxE), the transmit clock (TxC), the receive clock (RxC), the collision signal (Collision Signal (/ COL), and the transmit signal. Data (TxD) and received data (RxD), the signals of the first mutually repeating backplane interface of 10 (Mbps) are MAC active signal (MAC Active; MACATIV), mutual repeating backplane enable signal (/ IRBEN). , Mutually repeating backplane clock (IRBCLK), mutually repeating backplane collision signal (/ IRCOL), and mutually repeating backplane data (IRBDAT).

Then, the logical transformation of the signal is defined as Equation 1 below, and thus Equation 2 below.

RE_TxE = / TxE wait until TxC = '1'

S_IRBCLK = '0' wait until IRBCLK = '1'

/ TX_EN = / TxE * / COL

/ TX_DAT_EN = COL * / ST_ENA * / TxD

/ TxE = MACATIV

/ IRBEN = ST_ENA when / COL = '1'

RxE + / IRBE + S_IRBCLK

IRBCLK = TxC when / TxEN = '0'

RxC = IRBCLK

/ COL = / IRBCOL

IRBDAT = TxD when / TX_DAT_EN = '1'

RxD = IRBDAT

Here, when the equations (1) and (2) are programmed in the HDL or the like and applied to the PLD 30, logical signals are converted.

Therefore, the MAC 20 can accommodate both 10 (Mbps) data and 100 (Mbps) data even with the existing 10 (Mbps) interface, and the MAC level data processing can be performed.

On the contrary, the data transmitted from the upper layer to the MAC 20 is converted into a mutually repeating backplane signal in the PLD 30 and transmitted to the repeaters 60-1 to 60-n, and the bridge controller ( 50), either 10 (Mbps) or 100 (Mbps) terminal can be delivered to the device having the corresponding address.

As described above, the present invention can accommodate up to 100 (Mbps) of data even with a 10 (Mbps) MAC interface, thereby making the most of network speed improvement and resource performance. When there is a lot of data exchange on the segment, it can be enough to improve the performance of the network at a low cost and can accommodate not only the existing 10 (Mbps) terminal device but also a high speed device of 100 (Mbps) level.

Claims (4)

In an Ethernet repeating circuit comprising a MAC (Media Access Control) for connecting to a higher layer, a plurality of jacks for connecting to a terminal device through a line, and a plurality of transformers for transmitting and receiving data with the terminal device through a corresponding jack, A plurality of Fast Ethernet repeaters which sense the speed of the input data by an automatic sensing function and repeat the high speed data or the low speed data to be transmitted to another port of the jack or to another repeater through the mutual repeating backplane interface; A logic circuit unit for converting corresponding data according to signal level and timing for data transmission and reception between the MAC and the Fast Ethernet repeater; A bridge controller for converting the low speed data into the high speed data or converting the high speed data into the low speed data using a media independent interface (MII); And a memory unit which buffers the high speed data for a short time when the high speed data is converted into the low speed data. delete The method of claim 1, Each Fast Ethernet repeater is internally connected to each other through a first mutual repeating backplane interface for transmitting the low speed data to another repeater and a second mutual repeating backplane interface for transmitting the high speed data to another repeater. And converting the low speed data into the high speed data or converting the high speed data into the low speed data by incorporating a bridge control function in place of the bridge control unit. The method of claim 1, The logic circuit unit converts a signal of a 7-wire interface applied from the MAC to a mutually repeating backplane interface signal and transmits the signal to the Fast Ethernet repeater, and transmits the mutually repeating backplane interface signal applied from the fast Ethernet repeater to the 7-wire interface. Ethernet repeating circuit, characterized in that for converting the signal and transmitting to the MAC.