KR100343453B1 - Mult-laminated type memory module - Google Patents
Mult-laminated type memory module Download PDFInfo
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- KR100343453B1 KR100343453B1 KR1019990047139A KR19990047139A KR100343453B1 KR 100343453 B1 KR100343453 B1 KR 100343453B1 KR 1019990047139 A KR1019990047139 A KR 1019990047139A KR 19990047139 A KR19990047139 A KR 19990047139A KR 100343453 B1 KR100343453 B1 KR 100343453B1
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- 238000003780 insertion Methods 0.000 claims abstract description 11
- 230000037431 insertion Effects 0.000 claims abstract description 11
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- 239000010410 layer Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/074—Stacked arrangements of non-apertured devices
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
본 발명은 다중 적층형 메모리 모듈에 관한 것으로, 마더보드의 양쪽에 다수개의 전도핀이 수직으로 길게 구비되고, 그 마더보드의 전도핀이 각각 삽입되는 다수개의 핀삽입공이 도터보드의 양쪽에 구비되어 상기 도터보드가 마더보드의 상하 양측에 층층이 적층되도록 구성함으로써, 하나의 마더보드에 수개의 도터보드가 적층되어 메인보드에 실장되므로 메모리 모듈의 실장면적에 대비하여 많은 패키지를 일괄적으로 실장시킬 수 있게 되어 실장공간의 축소는 물론 실장작업이 용이하여 제품비용이 절감되는 효과가 있다.The present invention relates to a multi-layered memory module, wherein a plurality of conductive pins are vertically provided on both sides of the motherboard, and a plurality of pin insertion holes into which the conductive pins of the motherboard are inserted are provided at both sides of the daughter board. By configuring the daughter board so that the layers are stacked on both sides of the motherboard, several daughter boards are stacked on one motherboard and mounted on the main board, so that many packages can be packaged in preparation for the memory module mounting area. Since the mounting space is reduced, as well as the mounting work is easy, there is an effect that the product cost is reduced.
Description
본 발명은 컴퓨터에 실장되는 메모리 모듈에 관한 것으로, 특히 다중으로 적층할 수 있는 다중 적층형 메모리 모듈에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to memory modules mounted in computers, and more particularly, to multiple stacked memory modules that can be stacked in multiple layers.
일반적으로 컴퓨터 등에 실장되는 메모리 모듈이나 메모리 카드의 인쇄회로기판에는 다수개의 패키지가 각각 낱개로 실장되거나 또는 수개씩 적층되어 실장되는데, 이러한 종래의 메모리 모듈은 주로 마더보드(Mother Board)와 도터보드 (Daughter Board)를 도 1에 도시된 바와 같이 플렉시블 케이블로 연결하는 것이었다.In general, a plurality of packages are mounted individually or stacked on a printed circuit board of a memory module or a memory card mounted in a computer. Such a conventional memory module is mainly a mother board and a daughter board ( Daughter Board) was connected with a flexible cable as shown in FIG.
즉, 상기 마더보드(1)의 일측에 전기단자(미도시)가 구비되고, 이 마더보드(1)의 전기단자(미도시)에 대향되는 도터보드(2)의 일측에도 역시 전기단자(미도시)가 구비되는 동시에 상기 도터보드(2)의 중앙측에는 다수개의 패키지(P)가 실장되어 상기한 마더보드(1)의 전기단자(미도시)와 도터보드(2)의 전기단자(미도시)가 플렉시블 케이블(3)에 의해 일대일로 서로 연결되는 것이었다.That is, an electrical terminal (not shown) is provided on one side of the motherboard 1, and an electrical terminal (not shown) is also provided on one side of the daughter board 2 facing the electrical terminal (not shown) of the motherboard 1. At the same time a plurality of packages (P) is mounted on the center side of the daughter board (2) and the electrical terminal (not shown) of the motherboard (1) and the electrical terminal (not shown) of the daughter board (2) ) Were connected to each other one-to-one by a flexible cable (3).
그러나, 상기와 같은 종래의 메모리 모듈에 있어서는, 하나의 마더보드(1)에 하나의 도터보드(2)가 플렉시블 케이블(3)에 의해 직접 연결되므로, 실장면적 대비 메모리 모듈의 용량증가에 한계가 있게 되는 것이었다.However, in the conventional memory module as described above, since one daughter board 2 is directly connected to one motherboard 1 by the flexible cable 3, there is a limit to the increase in capacity of the memory module relative to the mounting area. It was to be.
이를 감안하여, 상기 도터보드(2)에 장착되는 패키지(P)를 각각 필요한 만큼 적정량 적층하여 메모리 모듈의 용량을 증가시키고 있으나, 이를 위하여는 각각의패키지(P)에 다른 패키지를 각각 적층시켜야 하므로 작업이 번거롭고 비용이 상승하게 되는 문제점이 있었다.In view of this, the capacity of the memory module is increased by stacking the package P mounted on the daughter board 2 as necessary, respectively. In order to do this, different packages must be stacked on each package P, respectively. There was a problem that the work is cumbersome and the cost increases.
본 발명은 상기와 같은 종래 메모리 모듈이 가지는 문제점을 감안하여 안출한 것으로, 실장면적을 대비하여 용량을 용이하면서도 저렴하게 증가시킬 수 있는 다중 적층형 메모리 모듈을 제공하려는데 그 목적이 있다.The present invention has been made in view of the above problems of the conventional memory module, and an object thereof is to provide a multi-layered memory module that can easily and inexpensively increase a capacity in preparation for a mounting area.
도 1은 종래 적층 메모리 모듈을 보인 사시도.1 is a perspective view showing a conventional stacked memory module.
도 2는 본 발명 다중 적측형 메모리 모듈을 보인 사시도.Figure 2 is a perspective view of the present invention multiple red-type memory module.
도 3a 및 도 3b는 본 발명 다중 적층형 메모리 모듈에 대한 정면도 및 측면도.3A and 3B are front and side views of the present invention's multiple stacked memory module.
도 4는 본 발명 다중 적층형 메모리 모듈의 조립과정을 보인 사시도.Figure 4 is a perspective view showing the assembly process of the present invention multiple stacked memory module.
도 5는 본 발명 다중 적층형 메모리 모듈의 변형예를 보인 종단면도.Figure 5 is a longitudinal cross-sectional view showing a modification of the present invention multi-layered memory module.
** 도면의 주요 부분에 대한 부호의 설명 **** Description of symbols for the main parts of the drawing **
10 : 마더보드 11 : 전도핀10: motherboard 11: conduction pin
20 : 도터보드 21 : 핀삽입공20: daughter board 21: pin insertion hole
30 : 히트스프레드 P : 패키지30: heat spread P: package
본 발명의 목적을 달성하기 위하여, 마더보드의 양쪽에 일정한 강도를 갖는 다수개의 전도핀이 수직으로 길게 구비되고, 그 마더보드의 전도핀이 각각 삽입되어 전기적으로 연결되는 다수개의 핀삽입공이 도터보드의 양쪽에 구비되어 상기 도터보드가 마더보드의 상하 양측에 층층이 적층되는 것을 특징으로 하는 다중 적층형 메모리 모듈이 제공된다.In order to achieve the object of the present invention, a plurality of conductive pins having a constant strength on both sides of the motherboard is provided vertically long, a plurality of pin insertion holes are electrically connected by inserting the conductive pins of the motherboard, respectively It is provided on both sides of the daughter board is provided with a multi-layered memory module, characterized in that the layer layer is stacked on both sides of the motherboard.
이하, 본 발명에 의한 다중 적층형 메모리 모듈을 첨부도면에 도시된 일실시예에 의거하여 상세하게 설명한다.Hereinafter, a multi-layered memory module according to the present invention will be described in detail with reference to an embodiment shown in the accompanying drawings.
도 2는 본 발명 다중 적측형 메모리 모듈을 보인 사시도이고, 도 3a 및 도 3b는 본 발명 다중 적층형 메모리 모듈에 대한 정면도 및 측면도이며, 도 4는 본 발명 다중 적층형 메모리 모듈의 조립과정을 보인 사시도이다.2 is a perspective view showing a multi-red memory module according to the present invention, FIGS. 3A and 3B are front and side views of the multi-layered memory module according to the present invention, and FIG. 4 is a perspective view showing the assembling process of the multi-layered memory module according to the present invention. to be.
이에 도시된 바와 같이 본 발명에 의한 다중 적층형 메모리 모듈은, 그 보드몸체의 일측에 일정한 강도를 갖는 다수개의 전도핀(11)이 길게 부착되는 마더보드(10)와, 그 마더보드(10)의 전도핀(11)에 층층이 삽입되어 전기적으로 연결되도록 각각 핀삽입공(21)이 형성되어 다층으로 적층되는 도터보드(20)로 구성된다.As shown therein, the multi-layered memory module according to the present invention includes a motherboard 10 having a plurality of conducting pins 11 having a certain strength on one side of the board body, and a length of the motherboard 10. A pin insertion hole 21 is formed to be electrically connected to the conductive layer by inserting a layer layer into the conductive pins 11, respectively.
상기 마더보드(10)는 전술한 바와 같이 그 보드몸체의 상하 양측면에 다수개의 전도핀(11)이 복열로 배치되어 수직으로 길게 부착되는 동시에 그 타측에는 통상의 골드 핑거(Gold Finger)(12)가 형성된다.As described above, the motherboard 10 has a plurality of conducting pins 11 arranged in a double row on both upper and lower sides of the board body, and are vertically attached to the other side thereof. Is formed.
상기 도터보드(20)는 마더보드(10)의 전도핀(11)에 대향되도록 각각 양측에 핀삽입공(21)이 복열로 형성됨과 아울러 그 양측 핀삽입공(21)의 사이에 패키지(P)가 단층으로 실장된다.The daughter board 20 has a plurality of pin insertion holes 21 formed on both sides of the daughter board 20 so as to face the conductive pins 11 of the motherboard 10, and a package (P) between the pin insertion holes 21. ) Is mounted in a single layer.
여기서, 상기 각 도터보드(20)의 사이에는 각 층의 도터보드(20)에 실장된 패키지(P)와 그 패키지(P)에 대향되는 타층 도터보드(20)의 패키지(P') 사이에 히트스프레드(30)가 개재되는 것이 바람직하다.Here, between the daughter boards 20, a package P mounted on the daughter boards 20 of each layer and a package P ′ of another layer daughter board 20 opposite to the package P may be provided. It is preferable that the heat spread 30 is interposed.
도면중 종래와 동일한 부분에 대하여는 동일한 부호를 부여하였다.In the drawings, the same reference numerals are given to the same parts as in the prior art.
상기와 같이 구성되는 본 발명에 의한 다중 적층형 메모리 모듈은 다음과 같이 조립된다.The multiple stacked memory module according to the present invention configured as described above is assembled as follows.
즉, 상기 마더보드(10)의 전도핀(11)에 도터보드(20)의 핀삽입공(21)이 대향되도록 하여 삽입시켜 상기한 마더보드(10)의 양측에 도터보드(20)를 수개씩 적층시킨 다음에, 상기 마더보드(10)의 전도핀(11)을 맨 나중 도터보드(20)의 상면에서 절곡하여 각각의 도터보드(20)가 마더보드(10)에 견고하게 고정되도록 한다.That is, the daughter board 20 may be placed on both sides of the motherboard 10 by inserting the pin insertion holes 21 of the daughter board 20 to face the conductive pins 11 of the motherboard 10. After stacking, the conductive pins 11 of the motherboard 10 are bent on the upper surface of the last daughter board 20 so that each daughter board 20 is firmly fixed to the motherboard 10. .
이때, 상기 각 도터보드(20)를 적층시키는 과정에서 그 각각의 도터보드(20) 사이에는 상기한 히트스프레드(30)를 개재시킨다.In this case, in the process of stacking the respective daughter boards 20, the heat spread 30 is interposed between the daughter boards 20.
한편, 상기 도터보드(20)를 적층시키는 방법으로는 전술한 바와 같이 마더보드(10)에 먼저 전도핀(11)을 부착시킨 다음에 그 전도핀(11)에 도터보드(20)의 핀삽입공(21)을 삽입시키면서 도터보드(20)를 나중에 하나씩 적층시키는 것과, 이와는 반대로 상기 마더보드(10)의 양측에 수개씩의 도터보드(20)를 미리 적층시킨 다음에 그 마더보드(10)와 도터보드(20)에 구비된 핀삽입공(21)을 전도핀(11)으로 관통시켜 그 전도핀(11)의 양끝을 절곡 고정시킬 수도 있다.Meanwhile, as the method of stacking the daughter board 20, as described above, the conductive pin 11 is first attached to the motherboard 10, and then the pin insertion of the daughter board 20 is inserted into the conductive pin 11. Later, the daughter boards 20 are stacked one by one while inserting the balls 21, and on the contrary, several daughter boards 20 are laminated in advance on both sides of the motherboard 10, and then the motherboard 10 is stacked. The pin insertion hole 21 provided in the daughter board 20 may be penetrated by the conductive pins 11 to bend and fix both ends of the conductive pins 11.
이렇게, 상기 마더보드의 양측에 수개씩의 도터보드를 후조립하여 적층시키게 되면, 상기 도터보드의 패키지에 또다른 패키지를 여러 층으로 실장하지 않고도 모듈의 용량을 극대화할 수 있게 된다.In this way, by assembling and stacking several daughter boards on both sides of the motherboard, it is possible to maximize the capacity of the module without mounting another package in multiple layers in the package of the daughter board.
본 발명에 의한 다중 적층형 메모리 모듈은, 마더보드의 양쪽에 다수개의 전도핀이 수직으로 길게 구비되고, 그 마더보드의 전도핀이 각각 삽입되는 다수개의 핀삽입공이 도터보드의 양쪽에 구비되어 상기 도터보드가 마더보드의 상하 양측에 층층이 적층되도록 구성함으로써, 하나의 마더보드에 수개의 도터보드가 적층되어 메인보드에 실장되므로 메모리 모듈의 실장면적에 대비하여 많은 패키지를 일괄적으로 실장시킬 수 있게 되어 실장공간의 축소는 물론 실장작업이 용이하여 제품비용이 절감되는 효과가 있다.In the multi-layered memory module according to the present invention, a plurality of conductive pins are vertically provided on both sides of the motherboard, and a plurality of pin insertion holes into which the conductive pins of the motherboard are inserted are provided at both sides of the daughter board. By configuring the boards to be stacked on both sides of the motherboard, several daughter boards are stacked on one motherboard and mounted on the main board, so that many packages can be packaged in preparation for the memory module mounting area. As well as the reduction of the mounting space, the mounting work is easy, thereby reducing the product cost.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990047139A KR100343453B1 (en) | 1999-10-28 | 1999-10-28 | Mult-laminated type memory module |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990047139A KR100343453B1 (en) | 1999-10-28 | 1999-10-28 | Mult-laminated type memory module |
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| Publication Number | Publication Date |
|---|---|
| KR20010038948A KR20010038948A (en) | 2001-05-15 |
| KR100343453B1 true KR100343453B1 (en) | 2002-07-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990047139A KR100343453B1 (en) | 1999-10-28 | 1999-10-28 | Mult-laminated type memory module |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100343453B1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020028038A (en) * | 2000-10-06 | 2002-04-15 | 마이클 디. 오브라이언 | Stacking structure of semiconductor package and stacking method the same |
| KR100513422B1 (en) * | 2003-11-13 | 2005-09-09 | 삼성전자주식회사 | Mounting structure in integrated circuit module |
| KR100590477B1 (en) | 2004-12-22 | 2006-06-19 | 삼성전자주식회사 | Interface between memory module and motherboard edge, and related structure of memory module |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990037491A (en) * | 1997-10-30 | 1999-05-25 | 가네꼬 히사시 | Substrate for stacked module and stacked module for making the wiring part for chips select in common |
-
1999
- 1999-10-28 KR KR1019990047139A patent/KR100343453B1/en not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990037491A (en) * | 1997-10-30 | 1999-05-25 | 가네꼬 히사시 | Substrate for stacked module and stacked module for making the wiring part for chips select in common |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010038948A (en) | 2001-05-15 |
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