KR100340204B1 - Link holding circuit of rs-485 communication system and method thereof - Google Patents

Abstract

PURPOSE: A link holding circuit of an RS-485 communication system and a method thereof are provided to prevent the collision of data on sending/receiving data by adding a link control circuit that generates a link control signal. CONSTITUTION: A data transmitting/receiving unit(70) is comprised of an interface unit for converting a parallel transmitted data signal from a CPU(Central Processing Unit) into a serial transmitted data signal to apply it to a first flip-flop(40a), the first flip-flop(40a) for receiving and inversing the transmitted data, and a data converting unit(71) for receiving an inversed signal from the first flip-flop(40a) to inverse it again, outputting to a communication circuits(10a,10b), and restoring a received signal from the communication circuits(10a,10b) to output it. A link holding unit(80) includes a second flip-flop(40b) for receiving a link holding requirement signal and a holding cancel signal of the CPU and a link control signal generating unit(81) for receiving a driving signal from the second flip-flop(40b) to output a holding or cancel signal.

Description

Line control circuit and method of RS-485 communication system

The present invention relates to a circuit control circuit for transmitting and receiving data by controlling a communication line shared by an RS-485 communication system and a method thereof, and in particular, to prevent data collisions during data transmission and reception to a communication device to be transmitted. The present invention relates to a circuit control circuit of a RS-485 communication system capable of securing a communication line and a method thereof.

RS-485 communication system is a system in which all communication devices share a single communication line and perform mutual communication. In particular, the characteristic of this communication system is that communication is performed in the same position without distinguishing master and slave in the communication protocol. In such a system, as shown in FIG. 1, since several communication devices 20a, 20b, ..., 20z are connected on one communication line 10a, 10b, one communication device transmits data. Other communication devices shall remain in the receiving state. Therefore, in order to implement such a communication system, a sophisticated communication protocol is required to avoid data collision on a communication line. Communication protocol can be implemented by hardware or software.

In the general RS-485 communication system, since there is no separate hardware means necessary to secure the line, such a communication protocol had to be implemented only by software means. Therefore, the burden of software was great, and there was a limit to fully implement "Peer To Peer Protocol" which is a characteristic of RS-485 communication system.

Accordingly, an object of the present invention has been made to overcome the above-mentioned problems, by introducing the hardware means necessary for line control to faithfully implement the original characteristics of the RS-485 communication system to prevent data from colliding on the communication line. To provide a circuit control circuit of the RS-485 communication system.

Another object of the present invention is to provide a line securing method of an RS-485 communication system for securing a common communication line so that data can be transmitted through a communication line in a communication device to be transmitted using hardware means.

The line securing circuit of the RS-485 communication system according to the present invention for achieving the above object comprises an interface unit for converting a parallel transmission data signal from the CPI into a serial transmission data signal and applying it to the first flip-flop, and transmission data. A first flip-flop that receives a signal and inverts the signal and outputs the inverted signal output from the first flip-flop and inverts it again to be output to a communication line, and recovers the received signal inputted from the communication line to its original state. A data transmission and reception unit having data conversion means is provided. A second flip-flop that receives the CSI's line take request signal or a release control signal and outputs the signals opposite to each other so that the data transmitting / receiving unit can transmit and receive data through a public line; and a drive signal from the second flip-flop And a line securing section including line control signal generating means for outputting the grasping or releasing signal opposed to the control line.

In addition, the line securing method of the RS-485 communication system according to the present invention for achieving another object has a step of initializing the line control signal of the communication device to be driven. And reading the line state signal to determine whether the communication line is in use. And if the communication line is determined to be empty in the determining step, generating a line securing request signal to secure the communication line. And reading the line state signal again to detect whether the communication line is secured. And if it is determined in the detecting step that the line is secured, it is provided with a step of transmitting data through the communication line. And reading the transfer buffer to determine whether the transfer has been completed. And notifying the circuit control line of the completion of transmission when the transmission is completed, and determining the end of transmission.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram of a communication device incorporating a line securing circuit according to the present invention. The communication device includes an interface unit 30 for transmitting and receiving data signals of other components with a central processing unit (not shown; CPU). The parallel signal input from the CPI via the interface unit 30 is converted into a serial signal and transmitted to the first flip-flop 40a, and the received data signals transmitted from the first transmission terminal 50a are also converted into parallel signals. It is input to Cifi. In particular, the serial transmission data signal is input to the preset input terminal PRE of the first flip-flop 40a via the interface unit 30. The transmission data signal that enters the preset input terminal PRE is inverted and output according to the clock. The signal output from the first flip-flop 40a is input to the data transmission control terminal TE of the first transmission terminal 50a. The first transmission terminal 50a is slotted when a low signal is input and no output is output. Accordingly, the upper communication line 10a is connected to the output side by connecting pull-up / pull-down resistors 60a and 60b to the output side. High signal and the lower communication line (Ob) produce a low signal. Of course, when the high signal enters the data transmission control terminal TE of the first transmission terminal 50a, the low signal entering the data transmission terminal TD is output as it is. In this way, a signal similar to the original data signal is output on the first communication line 10a. However, such a signal is mixed with some noise, which is differentially amplified and eliminated by a receiver (not shown) of the first transmitting end 50a. Therefore, the received data signal output through the first transmission terminal 50a becomes the same signal as the original signal and is transmitted to the CPI via the interface unit 30. In this manner, the first transmission stage 50a and the pull-up / pull-down resistors 60a and 60b which mutually convert data between the communication device and the communication line to exchange transmission and reception signals are referred to as data conversion means 71.

Of course, when transmitting data, the communication line should be controlled only by the communication device to be transmitted. Therefore, in the present invention, in addition to the data transmission / reception section 70 described above, the circuit securing section 80 to be described later is constituted by a circuit.

The line securing unit 80 stores a control signal input from the CPI for a while and then clocks the storage unit 90 for transmitting through the corresponding line, and the line securing request signal REQ outputted through the storage unit 90. A second flip-flop 40b is inputted to the input terminal CLK side and the line release signal REL is inputted to the clear input terminal CLR side. In addition, the second transmission stage 50b is configured to send a line securing signal to the line control lines 110a and 110b according to the drive signal output from the second flip-flop 40b. The second transmission terminal 50b inverts and outputs an input signal input to the data transmission control terminal TE. That is, when a high signal enters the data transmission control terminal (TE) side, a low signal, which is a ground enable signal, enters the data transmission terminal (TD) side and is output as it is. Slotted signals input to the data transmission terminal (TD) side are not output. However, at this time, the pull-up resistor 100a on the output side of the second transmission terminal 50b outputs a high signal to the first line control line 110a. In addition, since the pull-down resistor 100b is connected to the second line control line 110b, a low signal that is an inverted signal is output to the output signal of the first line control line 110a. The second transmission stage 50b and the pull-up / pull-down resistors 100a and 100b that generate and supply control signals to the line control lines 110a and 110b are referred to as the line control signal generating means 81. On the other hand, the above-described storage unit 90 is composed of a general-purpose latch and buffer, such as LS175, LS541.

SN75176 is used as the first and second transmission terminals 50a and 50b. A detailed description thereof will be added with reference to FIG.

3 is a circuit diagram of the SN75176 used as the first and second transmission stages.

Inside the transmission stage 50, a driver 51 for transmitting data and a receiver 52 for receiving data are configured. The driver 51 has a data transmission terminal TD and a data transmission control terminal TE at an input side, data is input to the data transmission terminal TD, and a transmission control signal is input to the data transmission control terminal TE. Output data. For example, when a high signal is input to the data transmission control terminal (TE), the buffer is opened and the input signal input to the data transmission terminal (TD) side is output as it is, and when a low signal is input to the transmission control signal, the buffer is closed to close the driver ( Slot 51) will not output. At this time, the same signal as the input signal is output to the upper output terminal Out1, and the input signal is inverted and output to the lower output terminal Out2.

The receiver 52 outputs a signal input through the input terminals In1 and In2 connected to an external communication line—a communication line or a rotation control line when the enable signal is applied to the data reception control terminal RE on the output side. . That is, when the low signal is input as the enable signal, the buffer is opened to output the received data. When the high signal is input, the buffer 52 is closed to close the buffer. Therefore, when the low signal is applied as the enable signal, the receiver 52 is activated in the reception state. As the receiver 52, a differential amplifier is used, and the signal returned to the original state is subtracted by subtracting the signal input to the two input terminals and output.

4 is a flowchart illustrating a line securing method of the RS-485 communication system according to the present invention. The operation of the present invention will now be described in detail with reference to the above-mentioned drawings.

The line release signal REL is applied to the clear input terminal CLR of the second flip-flop 40b to input a low signal to the data transmission control terminal TE of the second transmission terminal 50b. As a result, the second transmission terminal 50b is slotted and the low signal input to the data transmission terminal TD is not output. Accordingly, pull-up / pull-down resistors 100a and 100b on the output side of the second transmission stage 50b operate to send a high signal to the first line control line 110a and a low signal to the second line control line 110b. It becomes. After initializing the communication line as described above, the line state signal LST input through the second transmission terminal 50b is read to determine whether the communication lines 10a and 10b are used. In other words, if the line state signal LST is high, the communication lines 10a and 10b are unused, and if it is low, it is determined that the line is in use. (200, 201, 202) At this time, if the line state signal LST is high, the CPU is stored. Through line 90, the line lock request signal REQ is applied to the second flip-flop 40b. (Step 203) This signal is input to the clock input terminal CLK of the second flip-flop 40b. The high signal input through the terminal D is triggered to output the high signal to the output terminal Q. The second transmission terminal 50b receives this signal as the data transmission control terminal TE and transmits a low signal, which is a ground enable signal input to the data transmission terminal TD, to the first line control line 110a through the output terminal. The inverted high signal is sent to the second line control line 110b. Accordingly, the communication device to be transmitted displays the communication line control through the line control lines 110a and 110b, and all other communication devices read the signals on the line control lines 110a and 110b to read the communication line 10a. (Ob). (Step 204) After the control signal is sent to the line control lines 110a and 110b, the signal of the line control lines 110a and 110b is transmitted through the second transmission terminal 50b. Read it to see if she is in line. That is, the low signal of the first line control line 110a and the high signal of the second line control line 110b are input to the receiver of the second transmission terminal 50b and differentially amplified and output. At this time, the output signal becomes a line state signal LST, and a low signal is output. (Step 205) CFIU transmits a first transmission to the data receiving control line 91 through the storage unit 90 after confirming the state of the line control. The enable signal is applied to the stage 50a so that the transmitted data is not returned. This operation is performed by closing the buffer and switching to a state where reception is impossible by giving a high signal as an enable signal to the receiver output side of the first transmission terminal 50a. As described above, the first transmission terminal 50a drives the driver in a state where the receiver is closed to transmit data.

Data transmission is a parallel signal output by the CPI is serialized via the interface unit 30 is input to the preset input terminal PRE of the first flip-flop (40a), the input signal is inverted It is output and input to the data transmission control terminal (TE) side of the first transmission terminal 50a. The inputted transmission signal is inverted and outputted to the output terminal side by the transmission enable signal inputted to the data transmission terminal TD. At this time, if the transmission signal is high, the first transmission terminal 50a is activated, and the transmission enable signal of the row entering the data transmission terminal TD is output as it is. If the transmission signal is low, the first transmission terminal 50a is slow. No signal is output. Then, the pull-up / pull-down resistors 60a and 60b are driven to output a high signal on the first communication line 10a and a low signal on the second communication line 100b. Therefore, a signal similar to the original signal is output and transmitted on the communication lines 10a and 10b.

In transmission, the CPI reads the transmission buffer from time to time to determine whether the transmission is completed. If the transmission buffer is empty, it is determined that the transmission is completed and the line release signal REL is determined to be the clear input terminal of the second flip-flop 4Ob. (CLR). The second flip-flop 40b outputs a low signal by this signal. The output low signal is input to the data transmission control terminal TE of the second transmission terminal 50b. Accordingly, the second transmission terminal 50b is slotted so that no output occurs. Then, the pull-up / pull-down resistors 100a and 100b are driven to output a high signal to the first line control line 110a and a low signal to the second line control line 110b. Therefore, the communication device that has been transmitted will display the release of the communication lines 10a and 10b on the line control lines 110a and 110b. If it is determined that the transmission is not terminated, the process returns to step 201 to feed back the previous step.

As described above, the present system has an advantage that the characteristics of the RS-485 communication system can be more faithfully realized by adding a line control circuit that generates a line control signal to secure the communication line in hardware. In addition, since the implementation of the communication protocol for circuit control is performed in hardware, it has the effect of reducing the burden of software to maintain a stable system.

1 is a schematic configuration diagram of a general RS-485 communication system,

2 is a circuit diagram of a communication device incorporating a line securing circuit according to the present invention;

3 is a circuit diagram of the SN75176 used as the first and second transmission stages,

4 is a flowchart illustrating a line securing method of the RS-485 communication system according to the present invention.

* Explanation of symbols for main parts of the drawings

1Oa, lOb: Communication line 30: Interface part

40a, 40b: first and second flip-flops 50a, 50b: first and second transmission ends

51 driver 52 receiver

60a, 60b: Pull up / pull down resistance 70: Data transmitter / receiver

71: data conversion means 80: circuit control unit

81: circuit control signal generating means 90: storage unit

100a, 100b: pull up / pull down resistance 110a, 110b: line control line

REQ: Line securing request signal REL: Line release signal

LST: Line status signal RE: Data transmission control terminal

RD: Data transmission terminal RE: Data vibration control terminal

RD: Data receiving terminal

Claims (13)

In the RS-485 communication system in which a plurality of communication devices each having a first transmission end for transmitting and receiving data from the CAPIU to send and receive data through a common line, An interface unit for converting the parallel transmission data signal from the CPI into a serial transmission data signal and applying it to the first flip flop, a first flip flop that receives the inversion of the transmission data signal and outputs it, and outputs the first flip flop. A data transmission / reception unit having data conversion means for receiving the inverted signal and inverting it again and outputting it to the communication line, restoring and outputting the received signal inputted from the communication line to its original state; And A second flip-flop that receives the CSI's line take request signal or a release control signal and outputs the signals opposite to each other so that the data transmitting / receiving unit can transmit and receive data through a public line; and a drive signal from the second flip-flop A line securing circuit of an RS-485 communication system, comprising a line securing section having a line control signal generating means for outputting a grasping or releasing signal opposed to a control line. 2. The line securing circuit according to claim 1, wherein the line securing section further comprises a storage unit for storing the control signals from the CPI for a while and transmitting the second control signal to the second flip flop. 3. The line securing circuit according to claim 2, wherein the storage section comprises a general-purpose latch and a buffer. 4. The RS-485 device of claim 3, wherein the line lock request signal transmitted through the storage unit is input to the clock input terminal of the second flip-flop and outputs the D input signal, which is a high signal, in synchronization with a clock pulse. Circuit control circuit of communication system. 4. The circuit securing circuit according to claim 3, wherein the circuit release signal totally transmitted through the storage unit is input to the clear input terminal of the second flip-flop to output a low signal. 2. The data converting means of claim 1, wherein the data converting means outputs a high signal input from the first flip-flop to the data transfer control terminal by a ground enable signal input to the data transfer terminal, and outputs a low signal to the data transfer control terminal. A first transmission stage having a driver slotted upon application of a signal, a receiver receiving a data signal from the communication line and differentially amplifying and outputting the signal; and a high signal on the communication line when the driver of the first transmission stage is slotted and there is no output. Circuit control circuit of the RS-485 communication system, characterized in that consisting of a pull-up / pull-down resistor for outputting. The line control line of claim 1, wherein the line control signal generating means receives a high signal output from the second flip flop to a data transmission control terminal and receives a low signal by a ground in-ball signal input to a data transmission terminal. And a second transmission terminal having a driver slotted when a low signal is applied to the transmission control terminal, a receiver for differentially amplifying and outputting a signal input from a line control line, and the second transmission terminal being slotted and outputted. And a pull-up / pull-down resistor for outputting a high signal to the line control line if none is present. 8. The line securing circuit according to any one of claims 6 to 7, wherein SN75176 is used as the first and second transmission terminals. An RS-communication system for transmitting and receiving data by multiple communication devices sharing a communication line, the method for transmitting data by securing a common line in a communication device to be transmitted, Initializing a line control signal of a communication device to be driven; Reading a line state signal to determine whether a communication line is in use; If the communication line is determined to be empty in the determining step, generating a line securing request signal to secure the communication line; Detecting whether the communication line is secured by reading the line state signal again; Transmitting data through a communication line if it is determined in the detecting step that the line is secured; Determining whether transmission is completed by reading a transmission buffer when transmitting data; And A line control method for an RS-485 communication system, comprising the step of notifying the line control line of completion of transmission and determining the end of transmission. 10. The line securing method according to claim 9, further comprising the step of applying a high signal to the reception control terminal before transmission of the data to prevent transmission of the transmitted data. 10. The method of claim 9, wherein the controlling of the communication line comprises: holding a line lock request signal transmitted from CPI to trigger a second flip-flop, and an output signal generated thereby drives the driver of the second transmission end. And a line securing signal to the line control line. 10. The method of claim 9, wherein the output of the second flip-flop has an output opposite to that of the circuit-secure request signal due to the line-secure release signal input to the clear input terminal of the second flip-flop in the circuit-release step. Line control method of RS-485 communication system. 10. The method of claim 9, wherein the circuit initialization step comprises: inputting a line release release signal to a clear input terminal of a second flip-flop, and outputting the second flip-flop accordingly to a second transmission terminal. And a step of outputting a signal for canceling the line seizure and initializing the line state signal.